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https://github.com/WeActStudio/WeActStudio.EpaperModule.git
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572 lines
16 KiB
C
572 lines
16 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32f10x.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2019/10/15
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* Description : CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*********************************************************************************/
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#include "ch32f10x.h"
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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* reset the HSI is used as SYSCLK source).
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* If none of the define below is enabled, the HSI is used as System clock source.
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*/
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/* #define SYSCLK_FREQ_HSE HSE_VALUE */
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/* #define SYSCLK_FREQ_24MHz 24000000 */
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/* #define SYSCLK_FREQ_48MHz 48000000 */
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/* #define SYSCLK_FREQ_56MHz 56000000 */
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#define SYSCLK_FREQ_72MHz 72000000
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/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */
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/* #define VECT_TAB_SRAM */
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/* Vector Table base offset field This value must be a multiple of 0x200 */
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#define VECT_TAB_OFFSET 0x0
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/* Clock Definitions */
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#ifdef SYSCLK_FREQ_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_24MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_48MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_56MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_72MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */
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#else /* HSI Selected as System Clock source */
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uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
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#endif
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/* ch32f10x_system_private_function_proto_types */
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static void SetSysClock( void );
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#ifdef SYSCLK_FREQ_HSE
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static void SetSysClockToHSE( void );
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#elif defined SYSCLK_FREQ_24MHz
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static void SetSysClockTo24( void );
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#elif defined SYSCLK_FREQ_48MHz
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static void SetSysClockTo48( void );
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#elif defined SYSCLK_FREQ_56MHz
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static void SetSysClockTo56( void );
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#elif defined SYSCLK_FREQ_72MHz
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static void SetSysClockTo72( void );
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#endif
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#ifdef DATA_IN_ExtSRAM
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static void SystemInit_ExtMemCtl( void );
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#endif /* DATA_IN_ExtSRAM */
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* the PLL and update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit( void )
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{
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RCC->CTLR |= ( uint32_t )0x00000001;
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RCC->CFGR0 &= ( uint32_t )0xF8FF0000;
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RCC->CTLR &= ( uint32_t )0xFEF6FFFF;
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RCC->CTLR &= ( uint32_t )0xFFFBFFFF;
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RCC->CFGR0 &= ( uint32_t )0xFF80FFFF;
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RCC->INTR = 0x009F0000;
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SetSysClock();
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate( void )
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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tmp = RCC->CFGR0 & RCC_SWS;
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switch( tmp )
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{
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case 0x00:
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04:
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08:
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pllmull = RCC->CFGR0 & RCC_PLLMULL;
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pllsource = RCC->CFGR0 & RCC_PLLSRC;
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pllmull = ( pllmull >> 18 ) + 2;
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if( pllsource == 0x00 )
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{
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SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull;
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}
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else
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{
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if( ( RCC->CFGR0 & RCC_PLLXTPRE ) != ( uint32_t )RESET )
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{
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SystemCoreClock = ( HSE_VALUE >> 1 ) * pllmull;
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}
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else
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{
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SystemCoreClock = HSE_VALUE * pllmull;
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}
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}
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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tmp = AHBPrescTable[( ( RCC->CFGR0 & RCC_HPRE ) >> 4 )];
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SystemCoreClock >>= tmp;
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}
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/*********************************************************************
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* @fn SetSysClock
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*
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClock( void )
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{
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_24MHz
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SetSysClockTo24();
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#elif defined SYSCLK_FREQ_48MHz
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SetSysClockTo48();
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#elif defined SYSCLK_FREQ_56MHz
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SetSysClockTo56();
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#elif defined SYSCLK_FREQ_72MHz
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SetSysClockTo72();
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#endif
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/* If none of the define above is enabled, the HSI is used as System clock
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* source (default after reset)
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*/
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}
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#ifdef DATA_IN_ExtSRAM
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/*********************************************************************
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* @fn SystemInit_ExtMemCtl
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*
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* @brief Setup the external memory controller.
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*
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* @return none
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*/
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void SystemInit_ExtMemCtl( void )
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{
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RCC->AHBENR = 0x00000114;
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RCC->APB2ENR = 0x000001E0;
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GPIOD->CRL = 0x44BB44BB;
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GPIOD->CRH = 0xBBBBBBBB;
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GPIOE->CRL = 0xB44444BB;
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GPIOE->CRH = 0xBBBBBBBB;
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GPIOF->CRL = 0x44BBBBBB;
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GPIOF->CRH = 0xBBBB4444;
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GPIOG->CRL = 0x44BBBBBB;
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GPIOG->CRH = 0x44444B44;
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FSMC_Bank1->BTCR[4] = 0x00001011;
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FSMC_Bank1->BTCR[5] = 0x00000200;
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}
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#endif /* DATA_IN_ExtSRAM */
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#ifdef SYSCLK_FREQ_HSE
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/*********************************************************************
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* @fn SetSysClockToHSE
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*
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* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockToHSE( void )
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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}
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while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
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if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
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{
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HSEStatus = ( uint32_t )0x01;
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}
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else
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{
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HSEStatus = ( uint32_t )0x00;
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}
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if( HSEStatus == ( uint32_t )0x01 )
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{
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 0 wait state */
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FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
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FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_0;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1;
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/* Select HSE as system clock source */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
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RCC->CFGR0 |= ( uint32_t )RCC_SW_HSE;
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/* Wait till HSE is used as system clock source */
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while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x04 )
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{
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}
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}
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else
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_24MHz
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/*********************************************************************
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* @fn SetSysClockTo24
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*
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* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo24( void )
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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}
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while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
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if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
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{
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HSEStatus = ( uint32_t )0x01;
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}
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else
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{
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HSEStatus = ( uint32_t )0x00;
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}
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if( HSEStatus == ( uint32_t )0x01 )
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 0 wait state */
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FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
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FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_0;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1;
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
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RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3 );
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
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RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
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{
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}
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}
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else
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_48MHz
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/*********************************************************************
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* @fn SetSysClockTo48
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*
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* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo48( void )
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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}
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while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
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if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
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{
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HSEStatus = ( uint32_t )0x01;
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}
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else
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{
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HSEStatus = ( uint32_t )0x00;
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}
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if( HSEStatus == ( uint32_t )0x01 )
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 1 wait state */
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FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
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FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_1;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
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RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLMULL6 );
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
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RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
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{
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}
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}
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else
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{
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_56MHz
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/*********************************************************************
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* @fn SetSysClockTo56
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*
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* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo56( void )
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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}
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while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
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if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
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{
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HSEStatus = ( uint32_t )0x01;
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}
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else
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{
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HSEStatus = ( uint32_t )0x00;
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}
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if( HSEStatus == ( uint32_t )0x01 )
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 2 wait state */
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FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
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FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_2;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
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RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLMULL7 );
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
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RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
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{
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}
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}
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else
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{
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_72MHz
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/*********************************************************************
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* @fn SetSysClockTo72
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*
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo72( void )
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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}
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while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
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if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
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{
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HSEStatus = ( uint32_t )0x01;
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}
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else
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{
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HSEStatus = ( uint32_t )0x00;
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}
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if( HSEStatus == ( uint32_t )0x01 )
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 2 wait state */
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FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
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FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_2;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
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|
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
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RCC_PLLMULL ) );
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RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLMULL9 );
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
|
|
{
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}
|
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/* Select PLL as system clock source */
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RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
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RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
|
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{
|
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}
|
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}
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else
|
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{
|
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/*
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* If HSE fails to start-up, the application will have wrong clock
|
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* configuration. User can add here some code to deal with this error
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*/
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while(1);
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}
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}
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#endif
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