mirror of
https://github.com/WeActStudio/WeActStudio.EpaperModule.git
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first commit
This commit is contained in:
YXZhu
@@ -0,0 +1,552 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : core_riscv.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2020/04/30
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* Description : RISC-V Core Peripheral Access Layer Source File
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#include <stdint.h>
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/* define compiler specific symbols */
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#if defined(__CC_ARM)
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#elif defined(__ICCARM__)
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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#elif defined(__GNUC__)
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#elif defined(__TASKING__)
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#endif
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/*********************************************************************
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* @fn __get_FFLAGS
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*
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* @brief Return the Floating-Point Accrued Exceptions
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*
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* @return fflags value
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*/
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uint32_t __get_FFLAGS(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""fflags": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_FFLAGS
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*
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* @brief Set the Floating-Point Accrued Exceptions
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*
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* @param value - set FFLAGS value
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*
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* @return none
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*/
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void __set_FFLAGS(uint32_t value)
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{
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__ASM volatile("csrw fflags, %0":: "r"(value));
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}
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/*********************************************************************
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* @fn __get_FRM
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*
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* @brief Return the Floating-Point Dynamic Rounding Mode
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*
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* @return frm value
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*/
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uint32_t __get_FRM(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""frm": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_FRM
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*
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* @brief Set the Floating-Point Dynamic Rounding Mode
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*
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* @param value - set frm value
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*
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* @return none
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*/
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void __set_FRM(uint32_t value)
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{
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__ASM volatile("csrw frm, %0" :: "r"(value));
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}
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/*********************************************************************
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* @fn __get_FCSR
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*
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* @brief Return the Floating-Point Control and Status Register
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*
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* @return fcsr value
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*/
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uint32_t __get_FCSR(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "fcsr" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_FCSR
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*
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* @brief Set the Floating-Point Dynamic Rounding Mode
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*
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* @param value - set fcsr value
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*
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* @return none
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*/
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void __set_FCSR(uint32_t value)
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{
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__ASM volatile("csrw fcsr, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MSTATUS
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*
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* @brief Return the Machine Status Register
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*
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* @return mstatus value
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*/
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uint32_t __get_MSTATUS(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mstatus": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MSTATUS
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*
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* @brief Set the Machine Status Register
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*
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* @param value - set mstatus value
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*
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* @return none
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*/
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void __set_MSTATUS(uint32_t value)
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{
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__ASM volatile("csrw mstatus, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MISA
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*
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* @brief Return the Machine ISA Register
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*
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* @return misa value
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*/
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uint32_t __get_MISA(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""misa" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MISA
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*
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* @brief Set the Machine ISA Register
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*
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* @param value - set misa value
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*
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* @return none
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*/
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void __set_MISA(uint32_t value)
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{
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__ASM volatile("csrw misa, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MIE
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*
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* @brief Return the Machine Interrupt Enable Register
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*
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* @return mie value
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*/
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uint32_t __get_MIE(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mie": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MISA
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*
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* @brief Set the Machine ISA Register
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*
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* @param value - set mie value
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*
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* @return none
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*/
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void __set_MIE(uint32_t value)
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{
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__ASM volatile("csrw mie, %0": : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MTVEC
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*
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* @brief Return the Machine Trap-Vector Base-Address Register
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*
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* @return mtvec value
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*/
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uint32_t __get_MTVEC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mtvec": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVEC
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*
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* @brief Set the Machine Trap-Vector Base-Address Register
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*
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* @param value - set mtvec value
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*
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* @return none
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*/
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void __set_MTVEC(uint32_t value)
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{
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__ASM volatile("csrw mtvec, %0":: "r"(value));
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}
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/*********************************************************************
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* @fn __get_MTVEC
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*
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* @brief Return the Machine Seratch Register
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*
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* @return mscratch value
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*/
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uint32_t __get_MSCRATCH(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mscratch" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVEC
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*
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* @brief Set the Machine Seratch Register
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*
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* @param value - set mscratch value
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*
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* @return none
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*/
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void __set_MSCRATCH(uint32_t value)
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{
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__ASM volatile("csrw mscratch, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MEPC
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*
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* @brief Return the Machine Exception Program Register
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*
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* @return mepc value
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*/
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uint32_t __get_MEPC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mepc" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Exception Program Register
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*
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* @return mepc value
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*/
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void __set_MEPC(uint32_t value)
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{
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__ASM volatile("csrw mepc, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MCAUSE
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*
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* @brief Return the Machine Cause Register
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*
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* @return mcause value
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*/
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uint32_t __get_MCAUSE(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mcause": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Cause Register
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*
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* @return mcause value
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*/
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void __set_MCAUSE(uint32_t value)
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{
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__ASM volatile("csrw mcause, %0":: "r"(value));
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}
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/*********************************************************************
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* @fn __get_MTVAL
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*
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* @brief Return the Machine Trap Value Register
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*
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* @return mtval value
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*/
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uint32_t __get_MTVAL(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mtval" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVAL
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*
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* @brief Set the Machine Trap Value Register
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*
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* @return mtval value
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*/
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void __set_MTVAL(uint32_t value)
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{
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__ASM volatile("csrw mtval, %0":: "r"(value));
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}
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/*********************************************************************
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* @fn __get_MIP
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*
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* @brief Return the Machine Interrupt Pending Register
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*
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* @return mip value
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*/
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uint32_t __get_MIP(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mip": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MIP
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||||
*
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||||
* @brief Set the Machine Interrupt Pending Register
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*
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* @return mip value
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||||
*/
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void __set_MIP(uint32_t value)
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||||
{
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__ASM volatile("csrw mip, %0":: "r"(value));
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}
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|
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/*********************************************************************
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||||
* @fn __get_MCYCLE
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||||
*
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* @brief Return Lower 32 bits of Cycle counter
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*
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* @return mcycle value
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*/
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uint32_t __get_MCYCLE(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mcycle": "=r"(result));
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return (result);
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}
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||||
|
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/*********************************************************************
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||||
* @fn __set_MCYCLE
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||||
*
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* @brief Set Lower 32 bits of Cycle counter
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*
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* @return mcycle value
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*/
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void __set_MCYCLE(uint32_t value)
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{
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__ASM volatile("csrw mcycle, %0" : : "r"(value));
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||||
}
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||||
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/*********************************************************************
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||||
* @fn __get_MCYCLEH
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||||
*
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* @brief Return Upper 32 bits of Cycle counter
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*
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* @return mcycleh value
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||||
*/
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||||
uint32_t __get_MCYCLEH(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mcycleh" : "=r"(result));
|
||||
return (result);
|
||||
}
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||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MCYCLEH
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||||
*
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||||
* @brief Set Upper 32 bits of Cycle counter
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||||
*
|
||||
* @return mcycleh value
|
||||
*/
|
||||
void __set_MCYCLEH(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mcycleh, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MINSTRET
|
||||
*
|
||||
* @brief Return Lower 32 bits of Instructions-retired counter
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
uint32_t __get_MINSTRET(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""minstret": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MINSTRET
|
||||
*
|
||||
* @brief Set Lower 32 bits of Instructions-retired counter
|
||||
*
|
||||
* @return minstret value
|
||||
*/
|
||||
void __set_MINSTRET(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw minstret, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MINSTRETH
|
||||
*
|
||||
* @brief Return Upper 32 bits of Instructions-retired counter
|
||||
*
|
||||
* @return minstreth value
|
||||
*/
|
||||
uint32_t __get_MINSTRETH(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""minstreth": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MINSTRETH
|
||||
*
|
||||
* @brief Set Upper 32 bits of Instructions-retired counter
|
||||
*
|
||||
* @return minstreth value
|
||||
*/
|
||||
void __set_MINSTRETH(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw minstreth, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MVENDORID
|
||||
*
|
||||
* @brief Return Vendor ID Register
|
||||
*
|
||||
* @return mvendorid value
|
||||
*/
|
||||
uint32_t __get_MVENDORID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mvendorid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MARCHID
|
||||
*
|
||||
* @brief Return Machine Architecture ID Register
|
||||
*
|
||||
* @return marchid value
|
||||
*/
|
||||
uint32_t __get_MARCHID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""marchid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MIMPID
|
||||
*
|
||||
* @brief Return Machine Implementation ID Register
|
||||
*
|
||||
* @return mimpid value
|
||||
*/
|
||||
uint32_t __get_MIMPID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mimpid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MHARTID
|
||||
*
|
||||
* @brief Return Hart ID Register
|
||||
*
|
||||
* @return mhartid value
|
||||
*/
|
||||
uint32_t __get_MHARTID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mhartid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_SP
|
||||
*
|
||||
* @brief Return SP Register
|
||||
*
|
||||
* @return SP value
|
||||
*/
|
||||
uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
asm volatile("mv %0,""sp": "=r"(result):);
|
||||
return (result);
|
||||
}
|
||||
@@ -0,0 +1,397 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/04/30
|
||||
* Description : RISC-V Core Peripheral Access Layer Header File
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*******************************************************************************/
|
||||
#ifndef __CORE_RISCV_H__
|
||||
#define __CORE_RISCV_H__
|
||||
|
||||
/* IO definitions */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< defines 'write only' permissions */
|
||||
#define __IO volatile /*!< defines 'read / write' permissions */
|
||||
|
||||
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||
typedef __I uint32_t vuc32; /* Read Only */
|
||||
typedef __I uint16_t vuc16; /* Read Only */
|
||||
typedef __I uint8_t vuc8; /* Read Only */
|
||||
|
||||
typedef const uint32_t uc32; /* Read Only */
|
||||
typedef const uint16_t uc16; /* Read Only */
|
||||
typedef const uint8_t uc8; /* Read Only */
|
||||
|
||||
typedef __I int32_t vsc32; /* Read Only */
|
||||
typedef __I int16_t vsc16; /* Read Only */
|
||||
typedef __I int8_t vsc8; /* Read Only */
|
||||
|
||||
typedef const int32_t sc32; /* Read Only */
|
||||
typedef const int16_t sc16; /* Read Only */
|
||||
typedef const int8_t sc8; /* Read Only */
|
||||
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
||||
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
#define RV_STATIC_INLINE static inline
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
__IO uint32_t FIBADDRR;
|
||||
__IO uint32_t CFGR;
|
||||
__I uint32_t GISR;
|
||||
uint8_t RESERVED0[0x10];
|
||||
__IO uint32_t FIOFADDRR[4];
|
||||
uint8_t RESERVED1[0x90];
|
||||
__O uint32_t IENR[8];
|
||||
uint8_t RESERVED2[0x60];
|
||||
__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
|
||||
__IO uint32_t SCTLR;
|
||||
}PFIC_Type;
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTLR;
|
||||
__IO uint8_t CNTL0;
|
||||
__IO uint8_t CNTL1;
|
||||
__IO uint8_t CNTL2;
|
||||
__IO uint8_t CNTL3;
|
||||
__IO uint8_t CNTH0;
|
||||
__IO uint8_t CNTH1;
|
||||
__IO uint8_t CNTH2;
|
||||
__IO uint8_t CNTH3;
|
||||
__IO uint8_t CMPLR0;
|
||||
__IO uint8_t CMPLR1;
|
||||
__IO uint8_t CMPLR2;
|
||||
__IO uint8_t CMPLR3;
|
||||
__IO uint8_t CMPHR0;
|
||||
__IO uint8_t CMPHR1;
|
||||
__IO uint8_t CMPHR2;
|
||||
__IO uint8_t CMPHR3;
|
||||
}SysTick_Type;
|
||||
|
||||
|
||||
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
|
||||
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __NOP
|
||||
*
|
||||
* @brief nop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void __NOP()
|
||||
{
|
||||
__asm volatile ("nop");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_EnableIRQ
|
||||
*
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_DisableIRQ
|
||||
*
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->ITHRESDR;
|
||||
NVIC->ITHRESDR = 0x10;
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
NVIC->ITHRESDR = t;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetStatusIRQ
|
||||
*
|
||||
* @brief Get Interrupt Enable State
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Enable
|
||||
* 0 - Interrupt Disable
|
||||
*/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetPendingIRQ
|
||||
*
|
||||
* @brief Get Interrupt Pending State
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPendingIRQ
|
||||
*
|
||||
* @brief Set Interrupt Pending
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_ClearPendingIRQ
|
||||
*
|
||||
* @brief Clear Interrupt Pending
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetActive
|
||||
*
|
||||
* @brief Get Interrupt Active State
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Active
|
||||
* 0 - Interrupt No Active
|
||||
*/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPriority
|
||||
*
|
||||
* @brief Set Interrupt Priority
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
* priority -
|
||||
* bit7 - pre-emption priority
|
||||
* bit6~bit4 - subpriority
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFI
|
||||
*
|
||||
* @brief Wait for Interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
|
||||
asm volatile ("wfi");
|
||||
NVIC->SCTLR |= (1<<3);
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetFastIRQ
|
||||
*
|
||||
* @brief Set VTF Interrupt
|
||||
*
|
||||
* @param add - VTF interrupt service function base address.
|
||||
* IRQn -Interrupt Numbers
|
||||
* num - VTF Interrupt Numbers
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num)
|
||||
{
|
||||
if(num > 3) return ;
|
||||
NVIC->FIBADDRR = addr;
|
||||
NVIC->FIOFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SystemReset
|
||||
*
|
||||
* @brief Initiate a system reset request
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_HaltPushCfg
|
||||
*
|
||||
* @brief Enable Hardware Stack
|
||||
*
|
||||
* @param NewState - DISABLE or ENABLE
|
||||
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY1;
|
||||
}
|
||||
else{
|
||||
NVIC->CFGR = NVIC_KEY1|(1<<0);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_INTNestCfg
|
||||
*
|
||||
* @brief Enable Interrupt Nesting
|
||||
*
|
||||
* @param NewState - DISABLE or ENABLE
|
||||
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY1;
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY1|(1<<1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_FFLAGS(void);
|
||||
extern void __set_FFLAGS(uint32_t value);
|
||||
extern uint32_t __get_FRM(void);
|
||||
extern void __set_FRM(uint32_t value);
|
||||
extern uint32_t __get_FCSR(void);
|
||||
extern void __set_FCSR(uint32_t value);
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MIE(void);
|
||||
extern void __set_MIE(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MIP(void);
|
||||
extern void __set_MIP(uint32_t value);
|
||||
extern uint32_t __get_MCYCLE(void);
|
||||
extern void __set_MCYCLE(uint32_t value);
|
||||
extern uint32_t __get_MCYCLEH(void);
|
||||
extern void __set_MCYCLEH(uint32_t value);
|
||||
extern uint32_t __get_MINSTRET(void);
|
||||
extern void __set_MINSTRET(uint32_t value);
|
||||
extern uint32_t __get_MINSTRETH(void);
|
||||
extern void __set_MINSTRETH(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
|
||||
|
||||
#endif/* __CORE_RISCV_H__ */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user