first commit

Example/EpaperModuleTest_CH32F103/Src/board.c

@@ -0,0 +1,52 @@
+/*---------------------------------------
+- WeAct Studio Official Link
+- taobao: weactstudio.taobao.com
+- aliexpress: weactstudio.aliexpress.com
+- github: github.com/WeActTC
+- gitee: gitee.com/WeAct-TC
+- blog: www.weact-tc.cn
+---------------------------------------*/
+
+#include "board.h"
+
+void board_button_init(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+}
+
+uint8_t board_button_getstate(void)
+{
+    return GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0);
+}
+
+void board_led_init(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+}
+
+void board_led_toggle(void)
+{
+    GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_2) == Bit_SET ? GPIO_ResetBits(GPIOB, GPIO_Pin_2) : GPIO_SetBits(GPIOB, GPIO_Pin_2);
+}
+
+void board_led_set(uint8_t set)
+{
+    if (set)
+        GPIO_SetBits(GPIOB, GPIO_Pin_2);
+    else
+        GPIO_ResetBits(GPIOB, GPIO_Pin_2);
+}

Example/EpaperModuleTest_CH32F103/Src/ch32f10x_it.c

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+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Main Interrupt Service Routines.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#include "ch32f10x_it.h"
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler( void )
+{
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler( void )
+{
+    while( 1 )
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      MemManage_Handler
+ *
+ * @brief   This function handles Memory Manage exception.
+ *
+ * @return  none
+ */
+void MemManage_Handler( void )
+{
+    while( 1 )
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      BusFault_Handler
+ *
+ * @brief   This function handles Bus Fault exception.
+ *
+ * @return  none
+ */
+void BusFault_Handler( void )
+{
+    while( 1 )
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      UsageFault_Handler
+ *
+ * @brief   This function handles Usage Fault exception.
+ *
+ * @return  none
+ */
+void UsageFault_Handler( void )
+{
+    while( 1 )
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      SVC_Handler
+ *
+ * @brief   This function handles SVCall exception.
+ *
+ * @return  none
+ */
+void SVC_Handler( void )
+{
+}
+
+/*********************************************************************
+ * @fn      DebugMon_Handler
+ *
+ * @brief   This function handles Debug Monitor exception.
+ *
+ * @return  none
+ */
+void DebugMon_Handler( void )
+{
+}
+
+/*********************************************************************
+ * @fn      PendSV_Handler
+ *
+ * @brief   This function handles PendSVC exception.
+ *
+ * @return  none
+ */
+void PendSV_Handler( void )
+{
+}
+
+#include "systick.h"
+/*********************************************************************
+ * @fn      SysTick_Handler
+ *
+ * @brief   This function handles SysTick Handler.
+ *
+ * @return  none
+ */
+void SysTick_Handler( void )
+{
+    delay_decrement();
+}
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/Src/main.c

@@ -0,0 +1,150 @@
+/*---------------------------------------
+- WeAct Studio Official Link
+- taobao: weactstudio.taobao.com
+- aliexpress: weactstudio.aliexpress.com
+- github: github.com/WeActTC
+- gitee: gitee.com/WeAct-TC
+- blog: www.weact-tc.cn
+---------------------------------------*/
+
+#include "debug.h"
+#include "board.h"
+#include "systick.h"
+
+#include "epaper.h"
+#include "bmp.h"
+
+#define EPD_BWR
+
+uint8_t image_bw[4000];
+#ifdef EPD_BWR
+uint8_t image_red[4000];
+#endif
+
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+int main(void)
+{
+    uint8_t text[20];
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+
+    SystemCoreClockUpdate();
+
+    systick_config();
+
+    USART_Printf_Init(115200);
+
+    board_button_init();
+    board_led_init();
+
+    printf("\r\nWeAct Studio Core Board\r\n");
+    printf("weactstudio.taobao.com\r\n");
+    printf("weactstudio.aliexpress.com\r\n");
+    printf("wwww.weact-tc.cn\r\n\r\n");
+    printf("SystemClk:%d\r\n", SystemCoreClock);
+    printf("Epaper Module Test\r\n");
+
+    epd_io_init();
+
+    epd_init();
+
+#ifdef EPD_BWR
+    epd_paint_newimage(image_bw, EPD_W, EPD_H, EPD_ROTATE_180, EPD_COLOR_WHITE);
+
+    epd_paint_newimage(image_red, EPD_W, EPD_H, EPD_ROTATE_180, EPD_COLOR_WHITE);
+
+    epd_paint_selectimage(image_bw);
+    epd_paint_clear(EPD_COLOR_WHITE);
+    epd_paint_showPicture(0, 0, 250, 122, gImage_2, EPD_COLOR_BLACK);
+
+    epd_paint_selectimage(image_red);
+    epd_paint_clear(EPD_COLOR_WHITE);
+    epd_paint_showPicture(0, 0, 250, 122, gImage_3, EPD_COLOR_WHITE);
+
+    epd_display(image_bw, image_red);
+
+    delay(8000);
+
+    epd_paint_selectimage(image_bw);
+    epd_paint_clear(EPD_COLOR_WHITE);
+    epd_paint_showString(10, 0, (uint8_t *)&"2.13 Epaper Module", EPD_FONT_SIZE24x12, EPD_COLOR_BLACK);
+    epd_paint_showString(10, 29, (uint8_t *)&"Designed By WeAct Studio", EPD_FONT_SIZE16x8, EPD_COLOR_BLACK);
+    epd_paint_showString(10, 50, (uint8_t *)&"with 250 x 122 resolution", EPD_FONT_SIZE16x8, EPD_COLOR_BLACK);
+
+    epd_paint_selectimage(image_red);
+    epd_paint_clear(EPD_COLOR_WHITE);
+
+    sprintf((char *)&text, ">> Hello World.");
+    epd_paint_showString(10, 71, text, EPD_FONT_SIZE24x12, EPD_COLOR_RED);
+
+#if 0
+    epd_paint_showString(10,100,(uint8_t *)&"CH32F103C8T6 Example",EPD_FONT_SIZE16x8,EPD_COLOR_RED);
+#else
+    epd_paint_drawRectangle(10, 103, 240, 116, EPD_COLOR_RED, 1);
+#endif
+
+    epd_display(image_bw, image_red);
+#else
+    epd_paint_newimage(image_bw, EPD_W, EPD_H, EPD_ROTATE_180, EPD_COLOR_WHITE);
+
+    epd_paint_selectimage(image_bw);
+    epd_paint_clear(EPD_COLOR_WHITE);
+    epd_paint_showPicture(0, 0, 250, 122, gImage_1, EPD_COLOR_WHITE);
+
+    epd_displayBW(image_bw);
+
+    delay(5000);
+
+    epd_paint_selectimage(image_bw);
+    epd_paint_clear(EPD_COLOR_WHITE);
+    epd_paint_showString(10, 0, (uint8_t *)&"2.13 Epaper Module", EPD_FONT_SIZE24x12, EPD_COLOR_BLACK);
+    epd_paint_showString(10, 29, (uint8_t *)&"Designed By WeAct Studio", EPD_FONT_SIZE16x8, EPD_COLOR_BLACK);
+    epd_paint_showString(10, 50, (uint8_t *)&"with 250 x 122 resolution", EPD_FONT_SIZE16x8, EPD_COLOR_BLACK);
+
+    sprintf((char *)&text, ">> Hello World.");
+    epd_paint_showString(10, 71, text, EPD_FONT_SIZE24x12, EPD_COLOR_BLACK);
+
+#if 0
+    epd_paint_showString(10,100,(uint8_t *)&"CH32F103C8T6 Example",EPD_FONT_SIZE16x8,EPD_COLOR_BLACK);
+#else
+    epd_paint_drawRectangle(10, 103, 240, 116, EPD_COLOR_BLACK, 1);
+#endif
+    epd_displayBW(image_bw);
+#endif
+
+    epd_enter_deepsleepmode(EPD_DEEPSLEEP_MODE1);
+
+    uint32_t tick, toggle_tick;
+    tick = 0;
+    toggle_tick = 250;
+    while (1)
+    {
+        tick++;
+        if (tick % toggle_tick == 0)
+        {
+            board_led_toggle();
+        }
+        if (board_button_getstate())
+        {
+            while (board_button_getstate())
+            {
+                Delay_Ms(50);
+            }
+            if (toggle_tick == 250)
+            {
+                toggle_tick = 100;
+            }
+            else
+            {
+                toggle_tick = 250;
+            }
+        }
+        delay(1);
+    }
+}

Example/EpaperModuleTest_CH32F103/Src/system_ch32f10x.c

@@ -0,0 +1,571 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32f10x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32f10x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000  */
+/* #define SYSCLK_FREQ_48MHz  48000000  */
+/* #define SYSCLK_FREQ_56MHz  56000000  */
+#define SYSCLK_FREQ_72MHz  72000000
+
+
+/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */
+/* #define VECT_TAB_SRAM */
+
+/* Vector Table base offset field This value must be a multiple of 0x200 */
+#define VECT_TAB_OFFSET  0x0
+
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
+#else /* HSI Selected as System Clock source */
+uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* ch32f10x_system_private_function_proto_types */
+static void SetSysClock( void );
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_24MHz
+static void SetSysClockTo24( void );
+#elif defined SYSCLK_FREQ_48MHz
+static void SetSysClockTo48( void );
+#elif defined SYSCLK_FREQ_56MHz
+static void SetSysClockTo56( void );
+#elif defined SYSCLK_FREQ_72MHz
+static void SetSysClockTo72( void );
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl( void );
+#endif /* DATA_IN_ExtSRAM */
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit( void )
+{
+    RCC->CTLR |= ( uint32_t )0x00000001;
+    RCC->CFGR0 &= ( uint32_t )0xF8FF0000;
+    RCC->CTLR &= ( uint32_t )0xFEF6FFFF;
+    RCC->CTLR &= ( uint32_t )0xFFFBFFFF;
+    RCC->CFGR0 &= ( uint32_t )0xFF80FFFF;
+    RCC->INTR = 0x009F0000;
+    SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate( void )
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+    tmp = RCC->CFGR0 & RCC_SWS;
+
+    switch( tmp )
+    {
+        case 0x00:
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04:
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08:
+            pllmull = RCC->CFGR0 & RCC_PLLMULL;
+            pllsource = RCC->CFGR0 & RCC_PLLSRC;
+            pllmull = ( pllmull >> 18 ) + 2;
+            if( pllsource == 0x00 )
+            {
+                SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull;
+            }
+            else
+            {
+                if( ( RCC->CFGR0 & RCC_PLLXTPRE ) != ( uint32_t )RESET )
+                {
+                    SystemCoreClock = ( HSE_VALUE >> 1 ) * pllmull;
+                }
+                else
+                {
+                    SystemCoreClock = HSE_VALUE * pllmull;
+                }
+            }
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+
+    tmp = AHBPrescTable[( ( RCC->CFGR0 & RCC_HPRE ) >> 4 )];
+    SystemCoreClock >>= tmp;
+}
+
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock( void )
+{
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+    SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+    SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+    SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+    SetSysClockTo72();
+#endif
+
+    /* If none of the define above is enabled, the HSI is used as System clock
+     * source (default after reset)
+    */
+}
+
+
+#ifdef DATA_IN_ExtSRAM
+
+/*********************************************************************
+ * @fn      SystemInit_ExtMemCtl
+ *
+ * @brief   Setup the external memory controller.
+ *
+ * @return  none
+ */
+void SystemInit_ExtMemCtl( void )
+{
+    RCC->AHBENR = 0x00000114;
+    RCC->APB2ENR = 0x000001E0;
+
+    GPIOD->CRL = 0x44BB44BB;
+    GPIOD->CRH = 0xBBBBBBBB;
+
+    GPIOE->CRL = 0xB44444BB;
+    GPIOE->CRH = 0xBBBBBBBB;
+
+    GPIOF->CRL = 0x44BBBBBB;
+    GPIOF->CRH = 0xBBBB4444;
+
+    GPIOG->CRL = 0x44BBBBBB;
+    GPIOG->CRH = 0x44444B44;
+
+    FSMC_Bank1->BTCR[4] = 0x00001011;
+    FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+        /* Flash 0 wait state */
+        FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
+        FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_0;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1;
+
+        /* Select HSE as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_HSE;
+
+        /* Wait till HSE is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x04 )
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 0 wait state */
+        FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
+        FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_0;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1;
+
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3 );
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 1 wait state */
+        FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
+        FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_1;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLMULL6 );
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
+        FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLMULL7 );
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= ( uint32_t )( ( uint32_t )~FLASH_ACTLR_LATENCY );
+        FLASH->ACTLR |= ( uint32_t )FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+                                    RCC_PLLMULL ) );
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLMULL9 );
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+        while(1);
+    }
+}
+#endif
+
+
+
+

Example/EpaperModuleTest_CH32F103/Src/systick.c

@@ -0,0 +1,121 @@
+/*---------------------------------------
+- WeAct Studio Official Link
+- taobao: weactstudio.taobao.com
+- aliexpress: weactstudio.aliexpress.com
+- github: github.com/WeActTC
+- gitee: gitee.com/WeAct-TC
+- blog: www.weact-tc.cn
+---------------------------------------*/
+
+#include "systick.h"
+#include "ch32f10x.h"
+#include "ch32f10x_pwr.h"
+
+volatile uint32_t _tick = 0;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for (SysTick_Freq) Hz interrupts */
+    if (SysTick_Config(SystemCoreClock / SysTick_Freq))
+    {
+        /* capture error */
+        while (1)
+        {
+        }
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x05U);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay(uint32_t count)
+{
+    uint32_t utick;
+    utick = count + systick_get_tick();
+
+    while (systick_get_tick() < utick)
+    {
+    }
+}
+
+/*!
+    \brief      delay a time in milliseconds with low power
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_lp(uint32_t count)
+{
+    uint32_t utick;
+    utick = count + systick_get_tick();
+
+    while (systick_get_tick() < utick)
+    {
+        PWR_EnterSTANDBYMode();
+    }
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    _tick++;
+}
+
+/*!
+    \brief      get systick tick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+
+uint32_t systick_get_tick(void)
+{
+    return _tick;
+}
+
+void systick_DisableIRQ(void)
+{
+    /* Disable SysTick Interrupt */
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+void systick_EnableIRQ(void)
+{
+    /* Enable SysTick Interrupt */
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+void systick_Disable(void)
+{
+    /* Disable SysTick */
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+void systick_Enable(void)
+{
+    /* Enable SysTick */
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+void systick_deinit(void)
+{
+    SysTick->CTRL = 0;
+    SysTick->LOAD = 0;
+    SysTick->VAL = 0;
+}