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Example/EpaperModuleTest_CH32F103/CH32F103/CMSIS/cmsis_armcc.h

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+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.3.2
+ * @date     27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+  __ISB();
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

Example/EpaperModuleTest_CH32F103/CH32F103/CMSIS/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/CMSIS/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.5
+ * @date     02. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

Example/EpaperModuleTest_CH32F103/CH32F103/CMSIS/core_cm3.c

@@ -0,0 +1,784 @@
+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+  clrex
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+
+#endif /* __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  __ASM("rev16 r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+  __ASM("bx lr"); 
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, psp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, msp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief  Return the Control Register value
+* 
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result=0;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    uint8_t result=0;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    uint16_t result=0;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    uint32_t result=0;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif

Example/EpaperModuleTest_CH32F103/CH32F103/Debug/debug.c

@@ -0,0 +1,181 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : debug.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for UART
+ *                      Printf , Delay functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "debug.h"
+
+/* Support Printf Function Definition */
+//struct __FILE 
+//{ 
+//	int handle; 
+//}; 
+
+//FILE __stdout;
+
+
+static u8  p_us=0;								   
+static u16 p_ms=0;					
+
+/*********************************************************************
+ * @fn      Delay_Init
+ *
+ * @brief   Initializes Delay Funcation.
+ *
+ * @return  none
+ */	
+void Delay_Init(void)
+{
+	SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);	
+	p_us=SystemCoreClock/8000000;			  
+	p_ms=(u16)p_us*1000;					   
+}								    
+
+/*********************************************************************
+ * @fn      Delay_Us
+ *
+ * @brief   Microsecond Delay Time.
+ *
+ * @param   n - Microsecond number.
+ *
+ * @return  None
+ */
+void Delay_Us(u32 n)
+{		
+	u32 i;	
+	
+	SysTick->LOAD=n*p_us; 						  		 
+	SysTick->VAL=0x00;        					
+	SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ;
+	
+	do
+	{
+		i=SysTick->CTRL;
+	}while((i&0x01)&&!(i&(1<<16)));
+	
+	SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk;	
+	SysTick->VAL =0X00;     	 
+}
+
+/*********************************************************************
+ * @fn      Delay_Ms
+ *
+ * @brief   Millisecond Delay Time.
+ *
+ * @param   n - Millisecond number.
+ *
+ * @return  None
+ */
+void Delay_Ms(u16 n)
+{	 		  	  
+	u32 i;	
+	
+	SysTick->LOAD=(u32)n*p_ms;				
+	SysTick->VAL =0x00;							
+	SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ;
+	
+	do
+	{
+		i=SysTick->CTRL;
+	}while((i&0x01)&&!(i&(1<<16)));	
+	
+	SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk;	
+	SysTick->VAL =0X00;        	    
+} 
+
+
+/*********************************************************************
+ * @fn      fputc
+ *
+ * @brief   Support Printf Function 
+ *
+ * @param   data - UART send Data.
+ *          
+ * @return  data - UART send Data.
+ */
+int fputc(int data, FILE *f)
+{
+#if (DEBUG == DEBUG_UART1)
+  while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+	USART_SendData(USART1, (u8) data);
+#elif (DEBUG == DEBUG_UART2)
+  while (USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
+  USART_SendData(USART2, (u8) data);	
+#elif (DEBUG == DEBUG_UART3)
+  while (USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);	
+  USART_SendData(USART3, (u8) data);	
+#endif
+	
+  return data;
+}
+
+/*********************************************************************
+ * @fn      USART_Printf_Init
+ *
+ * @brief   Initializes the USARTx peripheral.
+ *
+ * @param   baudrate - USART communication baud rate.
+ *
+ * @return  None
+ */
+void USART_Printf_Init(u32 baudrate)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  USART_InitTypeDef USART_InitStructure;
+	
+#if (DEBUG == DEBUG_UART1)	
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1|RCC_APB2Periph_GPIOA, ENABLE);	
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;	
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+	
+#elif (DEBUG == DEBUG_UART2)
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);	
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;	
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+	
+#elif (DEBUG == DEBUG_UART3)	
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);	
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;	
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+	
+#endif	
+   
+  USART_InitStructure.USART_BaudRate = baudrate;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+#if (DEBUG == DEBUG_UART1)	
+  USART_Init(USART1, &USART_InitStructure); 
+  USART_Cmd(USART1, ENABLE);  
+	
+#elif (DEBUG == DEBUG_UART2)	
+  USART_Init(USART2, &USART_InitStructure); 
+  USART_Cmd(USART2, ENABLE);
+	
+#elif (DEBUG == DEBUG_UART3)
+  USART_Init(USART3, &USART_InitStructure); 
+  USART_Cmd(USART3, ENABLE);
+	
+#endif	
+}
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/Debug/debug.h

@@ -0,0 +1,64 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : debug.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for UART
+ *                      Printf , Delay and Bit-Banding functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __DEBUG_H
+#define __DEBUG_H 	
+
+#include "ch32f10x.h"
+#include "stdio.h"	
+
+/* GPIO Bit-Banding Macro Definition */
+#define BITBAND(adr, number)  ((adr & 0xF0000000)+0x2000000+((adr &0xFFFFF)<<5)+(number<<2)) 
+#define MEM_ADR(adr)  *((volatile unsigned long  *)(adr)) 
+#define BIT_ADR(adr, number)  MEM_ADR(BITBAND(adr, number)) 
+
+/* GPIO Output Address Mapping */
+#define GPIOA_ODR_Adr    (GPIOA_BASE+12) 						//0x4001080C 
+#define GPIOB_ODR_Adr    (GPIOB_BASE+12) 						//0x40010C0C 
+#define GPIOC_ODR_Adr    (GPIOC_BASE+12) 						//0x4001100C 
+#define GPIOD_ODR_Adr    (GPIOD_BASE+12) 						//0x4001140C 
+    
+/* GPIO Input Address Mapping */
+#define GPIOA_IDR_Adr    (GPIOA_BASE+8) 						//0x40010808 
+#define GPIOB_IDR_Adr    (GPIOB_BASE+8) 						//0x40010C08 
+#define GPIOC_IDR_Adr    (GPIOC_BASE+8) 						//0x40011008 
+#define GPIOD_IDR_Adr    (GPIOD_BASE+8) 						//0x40011408 
+
+/* GPIO Output */
+#define PAout(n)   BIT_ADR(GPIOA_ODR_Adr,n) 
+#define PBout(n)   BIT_ADR(GPIOB_ODR_Adr,n)  
+#define PCout(n)   BIT_ADR(GPIOC_ODR_Adr,n)
+#define PDout(n)   BIT_ADR(GPIOD_ODR_Adr,n) 
+
+/* GPIO Input */
+#define PAin(n)    BIT_ADR(GPIOA_IDR_Adr,n)   
+#define PBin(n)    BIT_ADR(GPIOB_IDR_Adr,n)     
+#define PCin(n)    BIT_ADR(GPIOC_IDR_Adr,n)  
+#define PDin(n)    BIT_ADR(GPIOD_IDR_Adr,n)  
+
+/* UART Printf Definition */
+#define DEBUG_UART1    1
+#define DEBUG_UART2    2
+#define DEBUG_UART3    3
+
+/* DEBUG UATR Definition */
+#define DEBUG   DEBUG_UART1
+//#define DEBUG   DEBUG_UART2
+//#define DEBUG   DEBUG_UART3
+
+void Delay_Init(void);
+void Delay_Us(u32 n);
+void Delay_Ms(u16 n);
+void USART_Printf_Init(u32 baudrate);
+
+#endif /* __DEBUG_H */
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/Startup/startup_ch32f10x.s

@@ -0,0 +1,299 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32f10x.s
+;* Author             : WCH
+;* Version            : V1.0.0
+;* Date               : 2019/10/15
+;* Description        : CH32F10x vector table for MDK-ARM toolchain.
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* SPDX-License-Identifier: Apache-2.0
+;*******************************************************************************/
+
+;/*******************************************************************************
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+;*******************************************************************************/
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+;/*******************************************************************************
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+;*******************************************************************************/
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+;/*******************************************************************************
+; Vector Table Mapped to Address 0 at Reset
+;*******************************************************************************/
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+									
+;/*******************************************************************************
+; External Interrupts
+;*******************************************************************************/
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; TAMPER
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; FLASH
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+                DCD     USBHD_IRQHandler           ; USB host and device
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+;/*******************************************************************************
+; Reset handler
+;*******************************************************************************/
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+;/*******************************************************************************
+; Dummy Exception Handlers (infinite loops which can be modified)
+;*******************************************************************************/
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+                EXPORT  USBHD_IRQHandler           [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+USBHD_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;/*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************/
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_adc.h

@@ -0,0 +1,196 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_adc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      ADC firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_ADC_H
+#define __CH32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+
+/* ADC Init structure definition */
+typedef struct
+{
+  uint32_t ADC_Mode;                      /* Configures the ADC to operate in independent or
+                                             dual mode. 
+                                             This parameter can be a value of @ref ADC_mode */
+
+  FunctionalState ADC_ScanConvMode;       /* Specifies whether the conversion is performed in
+                                             Scan (multichannels) or Single (one channel) mode.
+                                             This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
+                                             Continuous or Single mode.
+                                             This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /* Defines the external trigger used to start the analog
+                                             to digital conversion of regular channels. This parameter
+                                             can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /* Specifies whether the ADC data alignment is left or right.
+                                             This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /* Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+
+/* ADC_mode */
+#define ADC_Mode_Independent                        ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                     ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig                ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl             ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl             ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                        ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                          ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                         ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                         ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                          ((uint32_t)0x00090000)
+
+/* ADC_external_trigger_sources_for_regular_channels_conversion */
+#define ADC_ExternalTrigConv_T1_CC1                 ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigConv_T1_CC2                 ((uint32_t)0x00020000) 
+#define ADC_ExternalTrigConv_T2_CC2                 ((uint32_t)0x00060000) 
+#define ADC_ExternalTrigConv_T3_TRGO                ((uint32_t)0x00080000) 
+#define ADC_ExternalTrigConv_T4_CC4                 ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO     ((uint32_t)0x000C0000) 
+
+#define ADC_ExternalTrigConv_T1_CC3                 ((uint32_t)0x00040000) 
+#define ADC_ExternalTrigConv_None                   ((uint32_t)0x000E0000) 
+
+/* ADC_data_align */
+#define ADC_DataAlign_Right                         ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                          ((uint32_t)0x00000800)
+
+/* ADC_channels */
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+
+/* ADC_sampling_time */
+#define ADC_SampleTime_1Cycles5                     ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                     ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                    ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                    ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                    ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                    ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                    ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                   ((uint8_t)0x07)
+
+/* ADC_external_trigger_sources_for_injected_channels_conversion */
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) 
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) 
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) 
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) 
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) 
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) 
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) 
+
+/* ADC_injected_channel_selection */
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+
+/* ADC_analog_watchdog_selection */
+#define ADC_AnalogWatchdog_SingleRegEnable          ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable        ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable   ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable             ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable           ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable     ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                     ((uint32_t)0x00000000)
+
+/* ADC_interrupts_definition */
+#define ADC_IT_EOC                                  ((uint16_t)0x0220)
+#define ADC_IT_AWD                                  ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                 ((uint16_t)0x0480)
+
+/* ADC_flags_definition */
+#define ADC_FLAG_AWD                                ((uint8_t)0x01)
+#define ADC_FLAG_EOC                                ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                               ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                              ((uint8_t)0x08)
+#define ADC_FLAG_STRT                               ((uint8_t)0x10)
+
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+s32 TempSensor_Volt_To_Temper(s32 Value);
+int16_t Get_CalibrationValue(ADC_TypeDef* ADCx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F10x_ADC_H */
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_bkp.h

@@ -0,0 +1,97 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_bkp.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      BKP firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_BKP_H
+#define __CH32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* Tamper_Pin_active_level */
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+
+/* RTC_output_source_to_output_on_the_Tamper_pin */
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+	 
+/* Data_Backup_Register */
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_BKP_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_can.h

@@ -0,0 +1,366 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_can.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      CAN firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_CAN_H
+#define __CH32F10x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* CAN init structure definition */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /* Specifies the length of a time quantum. 
+                               It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /* Specifies the CAN operating mode.
+                               This parameter can be a value of 
+                              @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /* Specifies the maximum number of time quanta 
+                               the CAN hardware is allowed to lengthen or 
+                               shorten a bit to perform resynchronization.
+                               This parameter can be a value of 
+                               @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /* Specifies the number of time quanta in Bit 
+                               Segment 1. This parameter can be a value of 
+                               @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /* Specifies the number of time quanta in Bit 
+                               Segment 2.
+                               This parameter can be a value of 
+                               @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /* Enable or disable the time triggered 
+                               communication mode. This parameter can be set 
+                               either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /* Enable or disable the automatic bus-off 
+                                management. This parameter can be set either 
+                                to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /* Enable or disable the automatic wake-up mode. 
+                                This parameter can be set either to ENABLE or 
+                                DISABLE. */
+
+  FunctionalState CAN_NART;  /* Enable or disable the no-automatic 
+                                retransmission mode. This parameter can be 
+                                set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /* Enable or disable the Receive FIFO Locked mode.
+                                This parameter can be set either to ENABLE 
+                                or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /* Enable or disable the transmit FIFO priority.
+                                This parameter can be set either to ENABLE 
+                                or DISABLE. */
+} CAN_InitTypeDef;
+
+/* CAN filter init structure definition */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /* Specifies the filter identification number (MSBs for a 32-bit
+                                            configuration, first one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /* Specifies the filter identification number (LSBs for a 32-bit
+                                            configuration, second one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /* Specifies the filter mask number or identification number,
+                                            according to the mode (MSBs for a 32-bit configuration,
+                                            first one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /* Specifies the filter mask number or identification number,
+                                            according to the mode (LSBs for a 32-bit configuration,
+                                            second one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                            This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /* Specifies the filter mode to be initialized.
+                                            This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /* Specifies the filter scale.
+                                            This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
+                                            This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/* CAN Tx message structure definition */
+typedef struct
+{
+  uint32_t StdId;  /* Specifies the standard identifier.
+                      This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /* Specifies the extended identifier.
+                      This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /* Specifies the type of identifier for the message that 
+                      will be transmitted. This parameter can be a value 
+                      of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /* Specifies the type of frame for the message that will 
+                      be transmitted. This parameter can be a value of 
+                      @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /* Specifies the length of the frame that will be 
+                      transmitted. This parameter can be a value between 
+                      0 to 8 */
+
+  uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 
+                       to 0xFF. */
+} CanTxMsg;
+
+/* CAN Rx message structure definition  */
+typedef struct
+{
+  uint32_t StdId;  /* Specifies the standard identifier.
+                      This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /* Specifies the extended identifier.
+                      This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /* Specifies the type of identifier for the message that 
+                      will be received. This parameter can be a value of 
+                      @ref CAN_identifier_type */
+
+  uint8_t RTR;     /* Specifies the type of frame for the received message.
+                      This parameter can be a value of 
+                      @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /* Specifies the length of the frame that will be received.
+                      This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to 
+                      0xFF. */
+
+  uint8_t FMI;     /* Specifies the index of the filter the message stored in 
+                      the mailbox passes through. This parameter can be a 
+                      value between 0 to 0xFF */
+} CanRxMsg;
+
+/* CAN_sleep_constants */
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /* CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /* CAN initialization OK */
+
+/* CAN_Mode */
+#define CAN_Mode_Normal                    ((uint8_t)0x00)  /* normal mode */
+#define CAN_Mode_LoopBack                  ((uint8_t)0x01)  /* loopback mode */
+#define CAN_Mode_Silent                    ((uint8_t)0x02)  /* silent mode */
+#define CAN_Mode_Silent_LoopBack           ((uint8_t)0x03)  /* loopback combined with silent mode */
+
+/* CAN_Operating_Mode */
+#define CAN_OperatingMode_Initialization   ((uint8_t)0x00) /* Initialization mode */
+#define CAN_OperatingMode_Normal           ((uint8_t)0x01) /* Normal mode */
+#define CAN_OperatingMode_Sleep            ((uint8_t)0x02) /* sleep mode */
+
+/* CAN_Mode_Status */
+#define CAN_ModeStatus_Failed              ((uint8_t)0x00)                /* CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success             ((uint8_t)!CAN_ModeStatus_Failed)   /* CAN entering the specific mode Succeed */
+
+/* CAN_synchronisation_jump_width */
+#define CAN_SJW_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_SJW_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_SJW_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_SJW_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_1 */
+#define CAN_BS1_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_BS1_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_BS1_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_BS1_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+#define CAN_BS1_5tq                        ((uint8_t)0x04)  /* 5 time quantum */
+#define CAN_BS1_6tq                        ((uint8_t)0x05)  /* 6 time quantum */
+#define CAN_BS1_7tq                        ((uint8_t)0x06)  /* 7 time quantum */
+#define CAN_BS1_8tq                        ((uint8_t)0x07)  /* 8 time quantum */
+#define CAN_BS1_9tq                        ((uint8_t)0x08)  /* 9 time quantum */
+#define CAN_BS1_10tq                       ((uint8_t)0x09)  /* 10 time quantum */
+#define CAN_BS1_11tq                       ((uint8_t)0x0A)  /* 11 time quantum */
+#define CAN_BS1_12tq                       ((uint8_t)0x0B)  /* 12 time quantum */
+#define CAN_BS1_13tq                       ((uint8_t)0x0C)  /* 13 time quantum */
+#define CAN_BS1_14tq                       ((uint8_t)0x0D)  /* 14 time quantum */
+#define CAN_BS1_15tq                       ((uint8_t)0x0E)  /* 15 time quantum */
+#define CAN_BS1_16tq                       ((uint8_t)0x0F)  /* 16 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_2 */
+#define CAN_BS2_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_BS2_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_BS2_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_BS2_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+#define CAN_BS2_5tq                        ((uint8_t)0x04)  /* 5 time quantum */
+#define CAN_BS2_6tq                        ((uint8_t)0x05)  /* 6 time quantum */
+#define CAN_BS2_7tq                        ((uint8_t)0x06)  /* 7 time quantum */
+#define CAN_BS2_8tq                        ((uint8_t)0x07)  /* 8 time quantum */
+
+/* CAN_filter_mode */
+#define CAN_FilterMode_IdMask              ((uint8_t)0x00)  /* identifier/mask mode */
+#define CAN_FilterMode_IdList              ((uint8_t)0x01)  /* identifier list mode */
+
+/* CAN_filter_scale */
+#define CAN_FilterScale_16bit              ((uint8_t)0x00) /* Two 16-bit filters */
+#define CAN_FilterScale_32bit              ((uint8_t)0x01) /* One 32-bit filter */
+
+/* CAN_filter_FIFO */
+#define CAN_Filter_FIFO0                   ((uint8_t)0x00)  /* Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1                   ((uint8_t)0x01)  /* Filter FIFO 1 assignment for filter x */
+
+/* CAN_identifier_type */
+#define CAN_Id_Standard                    ((uint32_t)0x00000000)  /* Standard Id */
+#define CAN_Id_Extended                    ((uint32_t)0x00000004)  /* Extended Id */
+
+/* CAN_remote_transmission_request */
+#define CAN_RTR_Data                       ((uint32_t)0x00000000)  /* Data frame */
+#define CAN_RTR_Remote                     ((uint32_t)0x00000002)  /* Remote frame */
+
+/* CAN_transmit_constants */
+#define CAN_TxStatus_Failed                ((uint8_t)0x00)/* CAN transmission failed */
+#define CAN_TxStatus_Ok                    ((uint8_t)0x01) /* CAN transmission succeeded */
+#define CAN_TxStatus_Pending               ((uint8_t)0x02) /* CAN transmission pending */
+#define CAN_TxStatus_NoMailBox             ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
+
+/* CAN_receive_FIFO_number_constants */
+#define CAN_FIFO0                          ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
+#define CAN_FIFO1                          ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
+
+/* CAN_sleep_constants */
+#define CAN_Sleep_Failed                   ((uint8_t)0x00) /* CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok                       ((uint8_t)0x01) /* CAN entered the sleep mode */
+
+/* CAN_wake_up_constants */
+#define CAN_WakeUp_Failed                  ((uint8_t)0x00) /* CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok                      ((uint8_t)0x01) /* CAN leaved the sleep mode */
+ 
+/* CAN_Error_Code_constants */                                                               
+#define CAN_ErrorCode_NoErr                ((uint8_t)0x00) /* No Error */ 
+#define	CAN_ErrorCode_StuffErr             ((uint8_t)0x10) /* Stuff Error */ 
+#define	CAN_ErrorCode_FormErr              ((uint8_t)0x20) /* Form Error */ 
+#define	CAN_ErrorCode_ACKErr               ((uint8_t)0x30) /* Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr      ((uint8_t)0x40) /* Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr       ((uint8_t)0x50) /* Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr               ((uint8_t)0x60) /* CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr       ((uint8_t)0x70) /* Software Set Error */ 
+
+
+/* CAN_flags */
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0                     ((uint32_t)0x38000001) /* Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1                     ((uint32_t)0x38000100) /* Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2                     ((uint32_t)0x38010000) /* Request MailBox2 Flag */
+
+/* Receive Flags */ 
+#define CAN_FLAG_FMP0                      ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0                       ((uint32_t)0x32000008) /* FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0                      ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1                      ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1                       ((uint32_t)0x34000008) /* FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1                      ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU                       ((uint32_t)0x31000008) /* Wake up Flag */
+#define CAN_FLAG_SLAK                      ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
+
+/* Error Flags */
+#define CAN_FLAG_EWG                       ((uint32_t)0x10F00001) /* Error Warning Flag   */
+#define CAN_FLAG_EPV                       ((uint32_t)0x10F00002) /* Error Passive Flag   */
+#define CAN_FLAG_BOF                       ((uint32_t)0x10F00004) /* Bus-Off Flag         */
+#define CAN_FLAG_LEC                       ((uint32_t)0x30F00070) /* Last error code Flag */
+
+
+/* CAN_interrupts */
+#define CAN_IT_TME                         ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                        ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                         ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                        ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                        ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                         ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                        ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                         ((uint32_t)0x00010000) /* Wake-up Interrupt*/
+#define CAN_IT_SLK                         ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                         ((uint32_t)0x00000100) /* Error warning Interrupt*/
+#define CAN_IT_EPV                         ((uint32_t)0x00000200) /* Error passive Interrupt*/
+#define CAN_IT_BOF                         ((uint32_t)0x00000400) /* Bus-off Interrupt*/
+#define CAN_IT_LEC                         ((uint32_t)0x00000800) /* Last error code Interrupt*/
+#define CAN_IT_ERR                         ((uint32_t)0x00008000) /* Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0    CAN_IT_TME
+#define CAN_IT_RQCP1    CAN_IT_TME
+#define CAN_IT_RQCP2    CAN_IT_TME
+
+/* CAN_Legacy */
+#define CANINITFAILED               CAN_InitStatus_Failed
+#define CANINITOK                   CAN_InitStatus_Success
+#define CAN_FilterFIFO0             CAN_Filter_FIFO0
+#define CAN_FilterFIFO1             CAN_Filter_FIFO1
+#define CAN_ID_STD                  CAN_Id_Standard           
+#define CAN_ID_EXT                  CAN_Id_Extended
+#define CAN_RTR_DATA                CAN_RTR_Data         
+#define CAN_RTR_REMOTE              CAN_RTR_Remote
+#define CANTXFAILE                  CAN_TxStatus_Failed
+#define CANTXOK                     CAN_TxStatus_Ok
+#define CANTXPENDING                CAN_TxStatus_Pending
+#define CAN_NO_MB                   CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED              CAN_Sleep_Failed
+#define CANSLEEPOK                  CAN_Sleep_Ok
+#define CANWAKEUPFAILED             CAN_WakeUp_Failed        
+#define CANWAKEUPOK                 CAN_WakeUp_Ok        
+
+
+void CAN_DeInit(CAN_TypeDef* CANx); 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_CAN_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_crc.h

@@ -0,0 +1,37 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_crc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      CRC firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_CRC_H
+#define __CH32F10x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+	 
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_CRC_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_dac.h

@@ -0,0 +1,122 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_dac.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      DAC firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32F10x_DAC_H
+#define __CH32F10x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* DAC Init structure definition */
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /* Specifies the external trigger for the selected DAC channel.
+                                                This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /* Specifies whether DAC channel noise waves or triangle waves
+                                                are generated, or whether no wave is generated.
+                                                This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or
+                                                the maximum amplitude triangle generation for the DAC channel. 
+                                                This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /* Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+
+/* DAC_trigger_selection */
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                     has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                     only in High-density devices*/
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                     only in Connectivity line, Medium-density and Low-density Value Line devices */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /* TIM15 TRGO selected as external conversion trigger for DAC channel 
+                                                                     only in Medium-density and Low-density Value Line devices*/
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */
+
+/* DAC_wave_generation */
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+
+
+/* DAC_lfsrunmask_triangleamplitude */
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */
+
+/* DAC_output_buffer */
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+
+/* DAC_Channel_selection */
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+																 
+/* DAC_data_alignment */
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+
+/* DAC_wave_generation */
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F10x_DAC_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_dbgmcu.h

@@ -0,0 +1,64 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_dbgmcu.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      DBGMCU firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_DBGMCU_H
+#define __CH32F10x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+	 
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000400)
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00002000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00020000)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00040000)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00080000)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
+#define DBGMCU_TIM15_STOP            ((uint32_t)0x00400000)
+#define DBGMCU_TIM16_STOP            ((uint32_t)0x00800000)
+#define DBGMCU_TIM17_STOP            ((uint32_t)0x01000000)
+#define DBGMCU_TIM12_STOP            ((uint32_t)0x02000000)
+#define DBGMCU_TIM13_STOP            ((uint32_t)0x04000000)
+#define DBGMCU_TIM14_STOP            ((uint32_t)0x08000000)
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x10000000)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x20000000)
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x40000000)
+                                              
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_DBGMCU_H */
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_dma.h

@@ -0,0 +1,218 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_dma.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      DMA firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/  
+#ifndef __CH32F10x_DMA_H
+#define __CH32F10x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+ 
+/* DMA Init structure definition */
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
+
+  uint32_t DMA_MemoryBaseAddr;     /* Specifies the memory base address for DMAy Channelx. */
+
+  uint32_t DMA_DIR;                /* Specifies if the peripheral is the source or destination.
+                                      This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /* Specifies the buffer size, in data unit, of the specified Channel. 
+                                      The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                      or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /* Specifies whether the Peripheral address register is incremented or not.
+                                      This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /* Specifies whether the memory address register is incremented or not.
+                                      This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /* Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /* Specifies the operation mode of the DMAy Channelx.
+                                      This parameter can be a value of @ref DMA_circular_normal_mode.
+                                      @note: The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /* Specifies the software priority for the DMAy Channelx.
+                                      This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_M2M;                /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                      This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* DMA_data_transfer_direction */
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+
+/* DMA_peripheral_incremented_mode */
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+											
+/* DMA_memory_incremented_mode */
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+										
+/* DMA_peripheral_data_size */
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+
+/* DMA_memory_data_size */
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+
+/* DMA_circular_normal_mode */
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+
+/* DMA_priority_level */
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+/* DMA_memory_to_memory */
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+
+/* DMA_interrupts_definition */
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+
+/* DMA_flags_definition */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F10x_DMA_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_exti.h

@@ -0,0 +1,90 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_exti.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      EXTI firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_EXTI_H
+#define __CH32F10x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* EXTI mode enumeration */
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+/* EXTI Trigger enumeration */
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+/* EXTI Init Structure definition */
+typedef struct
+{
+  uint32_t EXTI_Line;               /* Specifies the EXTI lines to be enabled or disabled.
+                                       This parameter can be any combination of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /* Specifies the mode for the EXTI lines.
+                                       This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
+                                       This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /* Specifies the new state of the selected EXTI lines.
+                                       This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+
+/* EXTI_Lines */
+#define EXTI_Line0       ((uint32_t)0x00001)  /* External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)  /* External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)  /* External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)  /* External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)  /* External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)  /* External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)  /* External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)  /* External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)  /* External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)  /* External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)  /* External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)  /* External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)  /* External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)  /* External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)  /* External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)  /* External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)  /* External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)  /* External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)  /* External interrupt line 18 Connected to the USB Device/USB OTG FS
+                                                 Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)  /* External interrupt line 19 Connected to the USBHD Wakeup event */
+                                                            
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_EXTI_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_flash.h

@@ -0,0 +1,159 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_flash.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the FLASH  
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_FLASH_H
+#define __CH32F10x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* FLASH Status */
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+
+/* Flash_Latency */
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /* FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint32_t)0x00000001)  /* FLASH One Latency cycle */
+#define FLASH_Latency_2                ((uint32_t)0x00000002)  /* FLASH Two Latency cycles */
+
+/* Half_Cycle_Enable_Disable */
+#define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /* FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /* FLASH Half Cycle Disable */ 
+
+/* Prefetch_Buffer_Enable_Disable */
+#define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /* FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /* FLASH Prefetch Buffer Disable */ 
+
+/* Values to be used with CH32F10x Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 28 to 31 */
+                                                                   
+/* Values to be used with CH32F10x Medium-density devices */       
+#define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /* CH32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /* CH32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /* CH32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /* CH32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /* CH32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /* CH32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /* CH32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /* CH32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /* CH32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /* CH32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /* CH32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /* CH32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /* CH32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /* CH32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /* CH32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 124 to 127 */
+                                                                   
+#define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
+
+/* Option_Bytes_IWatchdog */
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /* Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /* Hardware IWDG selected */
+
+/* Option_Bytes_nRST_STOP */
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+
+/* Option_Bytes_nRST_STDBY  */
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+
+/* FLASH_Interrupts */	
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /* FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /* End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /* FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /* End of FLASH BANK1 Operation Interrupt source */
+
+/* FLASH_Flags */	
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /* FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /* FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /* FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /* FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /* FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /* FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /* FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /* FLASH BANK1 Write protected error flag */
+ 
+ 
+/*Functions used for all CH32F10x devices*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+void FLASH_Unlock_Fast(void);
+void FLASH_Lock_Fast(void);
+void FLASH_BufReset(void);
+void FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3);
+void FLASH_ErasePage_Fast(uint32_t Page_Address);
+void FLASH_ProgramPage_Fast(uint32_t Page_Address);
+
+/* New function used for all CH32F10x devices */
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __CH32F10x_FLASH_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_gpio.h

@@ -0,0 +1,167 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_gpio.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      GPIO firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_GPIO_H
+#define __CH32F10x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+                                 
+/* Output Maximum frequency selection */
+typedef enum
+{ 
+  GPIO_Speed_10MHz = 1,
+  GPIO_Speed_2MHz, 
+  GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+
+/* Configuration Mode enumeration */
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IPD = 0x28,
+  GPIO_Mode_IPU = 0x48,
+  GPIO_Mode_Out_OD = 0x14,
+  GPIO_Mode_Out_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+/* GPIO Init structure definition */
+typedef struct
+{
+  uint16_t GPIO_Pin;             /* Specifies the GPIO pins to be configured.
+                                    This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOSpeed_TypeDef GPIO_Speed;  /* Specifies the speed for the selected pins.
+                                    This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOMode_TypeDef GPIO_Mode;    /* Specifies the operating mode for the selected pins.
+                                    This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{
+	Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+/* GPIO_pins_define */
+#define GPIO_Pin_0                  ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                  ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                  ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                  ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                  ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                  ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                  ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                  ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                  ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                  ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                 ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                 ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                 ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                 ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                 ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                 ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All                ((uint16_t)0xFFFF)  /* All pins selected */
+
+/* GPIO_Remap_define */
+#define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /* USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /* PD01 Alternate Function mapping */
+#define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+                                                               to TIM2 Internal Trigger 1 for calibration
+                                                               (only for Connectivity line devices) */
+#define GPIO_Remap_TIM1_DMA         ((uint32_t)0x80000010)  /* TIM1 DMA requests mapping (only for Value line devices) */
+#define GPIO_Remap_TIM67_DAC_DMA    ((uint32_t)0x80000800)  /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
+#define GPIO_Remap_MISC             ((uint32_t)0x80002000)  /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
+                                                                 only for High density Value line devices) */                                                       
+
+/* GPIO_Port_Sources */
+#define GPIO_PortSourceGPIOA        ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB        ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC        ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD        ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE        ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF        ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG        ((uint8_t)0x06)
+
+/* GPIO_Pin_sources */
+#define GPIO_PinSource0             ((uint8_t)0x00)
+#define GPIO_PinSource1             ((uint8_t)0x01)
+#define GPIO_PinSource2             ((uint8_t)0x02)
+#define GPIO_PinSource3             ((uint8_t)0x03)
+#define GPIO_PinSource4             ((uint8_t)0x04)
+#define GPIO_PinSource5             ((uint8_t)0x05)
+#define GPIO_PinSource6             ((uint8_t)0x06)
+#define GPIO_PinSource7             ((uint8_t)0x07)
+#define GPIO_PinSource8             ((uint8_t)0x08)
+#define GPIO_PinSource9             ((uint8_t)0x09)
+#define GPIO_PinSource10            ((uint8_t)0x0A)
+#define GPIO_PinSource11            ((uint8_t)0x0B)
+#define GPIO_PinSource12            ((uint8_t)0x0C)
+#define GPIO_PinSource13            ((uint8_t)0x0D)
+#define GPIO_PinSource14            ((uint8_t)0x0E)
+#define GPIO_PinSource15            ((uint8_t)0x0F)                                 
+
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_GPIO_H */
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_i2c.h

@@ -0,0 +1,210 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_i2c.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      I2C firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_I2C_H
+#define __CH32F10x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* I2C Init structure definition  */
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /* Specifies the clock frequency.
+                                       This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /* Specifies the I2C mode.
+                                       This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /* Specifies the I2C fast mode duty cycle.
+                                       This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /* Specifies the first device own address.
+                                       This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /* Enables or disables the acknowledgement.
+                                       This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
+                                       This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* I2C_mode */
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+
+/* I2C_duty_cycle_in_fast_mode */
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
+
+/* I2C_acknowledgement */
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+
+/* I2C_transfer_direction */
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+
+/* I2C_acknowledged_address */
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+
+/* I2C_registers */
+#define I2C_Register_CTLR1              ((uint8_t)0x00)
+#define I2C_Register_CTLR2              ((uint8_t)0x04)
+#define I2C_Register_OADDR1             ((uint8_t)0x08)
+#define I2C_Register_OADDR2             ((uint8_t)0x0C)
+#define I2C_Register_DATAR              ((uint8_t)0x10)
+#define I2C_Register_STAR1              ((uint8_t)0x14)
+#define I2C_Register_STAR2              ((uint8_t)0x18)
+#define I2C_Register_CKCFGR             ((uint8_t)0x1C)
+#define I2C_Register_RTR                ((uint8_t)0x20)
+
+/* I2C_SMBus_alert_pin_level */
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+
+/* I2C_PEC_position */
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+
+/* I2C_NACK_position */
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+/* SR2 register flags  */
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/* SR1 register flags */
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+
+/****************I2C Master Events (Events grouped in order of communication)********************/
+
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/******************I2C Slave Events (Events grouped in order of communication)******************/
+
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
+/****************************************************************************************
+*                         I2C State Monitoring Functions                     
+****************************************************************************************/
+
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F10x_I2C_H */
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_iwdg.h

@@ -0,0 +1,56 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_iwdg.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      IWDG firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_IWDG_H
+#define __CH32F10x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* IWDG_WriteAccess */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+
+/* IWDG_prescaler */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+
+/* IWDG_Flag */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_IWDG_H */
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_misc.h

@@ -0,0 +1,80 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_misc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      miscellaneous firmware library functions (add-on to CMSIS functions).
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/   
+#ifndef __CH32F10X_MISC_H
+#define __CH32F10X_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* NVIC Init Structure definition */	 
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /* Specifies the IRQ channel to be enabled or disabled.
+                                                 This parameter can be a value of @ref IRQn_Type 
+                                                 (For the complete CH32 Devices IRQ Channels list, please
+                                                  refer to ch32f10x.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /* Specifies the pre-emption priority for the IRQ channel
+                                                 specified in NVIC_IRQChannel. This parameter can be a value
+                                                 between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /* Specifies the subpriority level for the IRQ channel specified
+                                                 in NVIC_IRQChannel. This parameter can be a value
+                                                 between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  FunctionalState NVIC_IRQChannelCmd;         /* Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                 will be enabled or disabled. 
+                                                 This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+
+/* Vector_Table_Base */
+#define NVIC_VectTab_RAM               ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH             ((uint32_t)0x08000000)
+
+/* System_Low_Power */
+#define NVIC_LP_SEVONPEND              ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP              ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT            ((uint8_t)0x02)
+
+
+/* Preemption_Priority_Group */
+#define NVIC_PriorityGroup_0           ((uint32_t)0x700) /* 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1           ((uint32_t)0x600) /* 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2           ((uint32_t)0x500) /* 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3           ((uint32_t)0x400) /* 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4           ((uint32_t)0x300) /* 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+/* SysTick_clock_source */
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_MISC_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_pwr.h

@@ -0,0 +1,59 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_pwr.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the PWR  
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_PWR_H
+#define __CH32F10x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* PVD_detection_level  */
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+	 
+/* Regulator_state_is_STOP_mode */
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+
+/* STOP_mode_entry */
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+ 
+/* PWR_Flag */
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_PWR_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_rcc.h

@@ -0,0 +1,230 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_rcc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the RCC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_RCC_H
+#define __CH32F10x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* RCC_Exported_Types */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;  /* returns SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;    /* returns HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;   /* returns PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;   /* returns PCLK2 clock frequency expressed in Hz */
+  uint32_t ADCCLK_Frequency;  /* returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/* HSE_configuration */
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+
+/* PLL_entry_clock_source */
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
+#define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
+
+/* PLL_multiplication_factor */
+#define RCC_PLLMul_2                     ((uint32_t)0x00000000)
+#define RCC_PLLMul_3                     ((uint32_t)0x00040000)
+#define RCC_PLLMul_4                     ((uint32_t)0x00080000)
+#define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6                     ((uint32_t)0x00100000)
+#define RCC_PLLMul_7                     ((uint32_t)0x00140000)
+#define RCC_PLLMul_8                     ((uint32_t)0x00180000)
+#define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10                    ((uint32_t)0x00200000)
+#define RCC_PLLMul_11                    ((uint32_t)0x00240000)
+#define RCC_PLLMul_12                    ((uint32_t)0x00280000)
+#define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14                    ((uint32_t)0x00300000)
+#define RCC_PLLMul_15                    ((uint32_t)0x00340000)
+#define RCC_PLLMul_16                    ((uint32_t)0x00380000)
+                            
+/* System_clock_source */
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+
+/* AHB_clock_source */
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+
+/* APB1_APB2_clock_source */
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+
+/* RCC_Interrupt_source */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+/* USB_Device_clock_source */
+#define RCC_USBCLKSource_PLLCLK_1Div5    ((uint8_t)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1     ((uint8_t)0x01)
+
+/* ADC_clock_source */
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+
+/* LSE_configuration */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+
+/* RTC_clock_source */
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+
+/* AHB_peripheral */
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+#define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
+#define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
+#define RCC_AHBPeriph_USBHD              ((uint32_t)0x00001000)
+
+/* APB2_peripheral */
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
+
+/* APB1_peripheral */
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
+
+/* Clock_source_to_output_on_MCO_pin */
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+
+/* RCC_Flag */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_RCC_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_rtc.h

@@ -0,0 +1,54 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_rtc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the RTC  
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_RTC_H
+#define __CH32F10x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+
+/* RTC_interrupts_define */
+#define RTC_IT_OW            ((uint16_t)0x0004)  /* Overflow interrupt */
+#define RTC_IT_ALR           ((uint16_t)0x0002)  /* Alarm interrupt */
+#define RTC_IT_SEC           ((uint16_t)0x0001)  /* Second interrupt */
+
+/* RTC_interrupts_flags */
+#define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF         ((uint16_t)0x0008)  /* Registers Synchronized flag */
+#define RTC_FLAG_OW          ((uint16_t)0x0004)  /* Overflow flag */
+#define RTC_FLAG_ALR         ((uint16_t)0x0002)  /* Alarm flag */
+#define RTC_FLAG_SEC         ((uint16_t)0x0001)  /* Second flag */
+	 
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_RTC_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_spi.h

@@ -0,0 +1,229 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_spi.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      SPI firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_SPI_H
+#define __CH32F10x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* SPI Init structure definition */
+typedef struct
+{
+  uint16_t SPI_Direction;           /* Specifies the SPI unidirectional or bidirectional data mode.
+                                       This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /* Specifies the SPI operating mode.
+                                       This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /* Specifies the SPI data size.
+                                       This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /* Specifies the serial clock steady state.
+                                       This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /* Specifies the clock active edge for the bit capture.
+                                       This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /* Specifies whether the NSS signal is managed by
+                                       hardware (NSS pin) or by software using the SSI bit.
+                                       This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /* Specifies the Baud Rate prescaler value which will be
+                                       used to configure the transmit and receive SCK clock.
+                                       This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                       @note The communication clock is derived from the master
+                                             clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /* Specifies whether data transfers start from MSB or LSB bit.
+                                       This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /* Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/* I2S Init structure definition */
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /* Specifies the I2S operating mode.
+                                This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /* Specifies the standard used for the I2S communication.
+                                This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /* Specifies the data format for the I2S communication.
+                                This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /* Specifies whether the I2S MCLK output is enabled or not.
+                                This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /* Specifies the frequency selected for the I2S communication.
+                                This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /* Specifies the idle state of the I2S clock.
+                                This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* SPI_data_direction */  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+
+/* SPI_mode */
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+
+/* SPI_data_size */
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+
+/* SPI_Clock_Polarity */
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+
+/* SPI_Clock_Phase */
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+
+/* SPI_Slave_Select_management */
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+
+/* SPI_BaudRate_Prescaler */
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+
+/* SPI_MSB_LSB_transmission */
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+
+/* I2S_Mode */
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+
+/* I2S_Standard */
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+
+/* I2S_Data_Format */
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+
+/* I2S_MCLK_Output */
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+
+/* I2S_Audio_Frequency */
+#define I2S_AudioFreq_192k              ((uint32_t)192000)
+#define I2S_AudioFreq_96k               ((uint32_t)96000)
+#define I2S_AudioFreq_48k               ((uint32_t)48000)
+#define I2S_AudioFreq_44k               ((uint32_t)44100)
+#define I2S_AudioFreq_32k               ((uint32_t)32000)
+#define I2S_AudioFreq_22k               ((uint32_t)22050)
+#define I2S_AudioFreq_16k               ((uint32_t)16000)
+#define I2S_AudioFreq_11k               ((uint32_t)11025)
+#define I2S_AudioFreq_8k                ((uint32_t)8000)
+#define I2S_AudioFreq_Default           ((uint32_t)2)
+
+/* I2S_Clock_Polarity */
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+
+/* SPI_I2S_DMA_transfer_requests */
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+
+/* SPI_NSS_internal_software_management */
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+
+/* SPI_CRC_Transmit_Receive */
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+
+/* SPI_direction_transmit_receive */
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+
+/* SPI_I2S_interrupts_definition */
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+
+/* SPI_I2S_flags_definition */
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F10x_SPI_H */
+
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_tim.h

@@ -0,0 +1,515 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_tim.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      TIM firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_TIM_H
+#define __CH32F10x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+/* TIM Time Base Init structure definition */
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /* Specifies the prescaler value used to divide the TIM clock.
+                                     This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /* Specifies the counter mode.
+                                     This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint16_t TIM_Period;            /* Specifies the period value to be loaded into the active
+                                     Auto-Reload Register at the next update event.
+                                     This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
+  uint16_t TIM_ClockDivision;     /* Specifies the clock division.
+                                    This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /* Specifies the repetition counter value. Each time the RCR downcounter
+                                     reaches zero, an update event is generated and counting restarts
+                                     from the RCR value (N).
+                                     This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     This parameter must be a number between 0x00 and 0xFF. 
+                                     @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;       
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+  uint16_t TIM_OCMode;        /* Specifies the TIM mode.
+                                 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /* Specifies the TIM Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_state */
+
+  uint16_t TIM_OutputNState;  /* Specifies the TIM complementary Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_Pulse;         /* Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                 This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_OCPolarity;    /* Specifies the output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /* Specifies the complementary output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCIdleState;   /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCNIdleState;  /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+  uint16_t TIM_Channel;      /* Specifies the TIM channel.
+                                This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /* Specifies the active edge of the input signal.
+                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /* Specifies the input.
+                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /* Specifies the Input Capture Prescaler.
+                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /* Specifies the input capture filter.
+                                This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+  uint16_t TIM_OSSRState;        /* Specifies the Off-State selection used in Run mode.
+                                    This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /* Specifies the Off-State used in Idle state.
+                                    This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /* Specifies the LOCK level parameters.
+                                    This parameter can be a value of @ref Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /* Specifies the delay time between the switching-off and the
+                                    switching-on of the outputs.
+                                    This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /* Specifies whether the TIM Break input is enabled or not. 
+                                    This parameter can be a value of @ref Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /* Specifies the TIM Break Input pin polarity.
+                                    This parameter can be a value of @ref Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /* Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                    This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* TIM_Output_Compare_and_PWM_modes */
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+
+/* TIM_One_Pulse_Mode */
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+
+/* TIM_Channel */
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+
+/* TIM_Clock_Division_CKD */
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+
+/* TIM_Counter_Mode */
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+
+/* TIM_Output_Compare_Polarity */
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+
+/* TIM_Output_Compare_N_Polarity */  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+
+/* TIM_Output_Compare_state */
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+
+/* TIM_Output_Compare_N_state */
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+
+/* TIM_Capture_Compare_state */
+#define TIM_CCx_Enable                     ((uint16_t)0x0001)
+#define TIM_CCx_Disable                    ((uint16_t)0x0000)
+
+/* TIM_Capture_Compare_N_state */
+#define TIM_CCxN_Enable                    ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                   ((uint16_t)0x0000)
+
+/* Break_Input_enable_disable */
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+
+/* Break_Polarity */
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+
+/* TIM_AOE_Bit_Set_Reset */
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+
+/* Lock_level */
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+
+/* OSSI_Off_State_Selection_for_Idle_mode_state */
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+
+/* OSSR_Off_State_Selection_for_Run_mode_state */
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Idle_State */
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_N_Idle_State */
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+
+/* TIM_Input_Capture_Polarity */
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+                                     
+/* TIM_Input_Capture_Selection */
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                 connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be
+                                                                 connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+
+/* TIM_Input_Capture_Prescaler */
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /* Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /* Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /* Capture performed once every 8 events. */
+
+/* TIM_interrupt_sources */
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+
+/* TIM_DMA_Base_address */
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+
+/* TIM_DMA_Burst_Length */
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+
+/* TIM_DMA_sources */
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+
+/* TIM_External_Trigger_Prescaler */
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+
+/* TIM_Internal_Trigger_Selection */
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+
+/* TIM_TIx_External_Clock_Source */
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/* TIM_External_Trigger_Polarity */
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+
+/* TIM_Prescaler_Reload_Mode */
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+
+/* TIM_Forced_Action */
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+
+/* TIM_Encoder_Mode */
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+
+/* TIM_Event_Source */
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+
+/* TIM_Update_Source */
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow
+                                                                 or the setting of UG bit, or an update generation
+                                                                 through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
+
+/* TIM_Output_Compare_Preload_State */
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Fast_State */
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Clear_State */
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+
+/* TIM_Trigger_Output_Source */
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+
+/* TIM_Slave_Mode */
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+
+/* TIM_Master_Slave_Mode */
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+
+/* TIM_Flags */
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+
+/* TIM_Legacy */
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F10x_TIM_H */
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_usart.h

@@ -0,0 +1,195 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_usart.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the 
+ *                      USART firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_USART_H
+#define __CH32F10x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+ 
+
+/* USART Init Structure definition */  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /* This member configures the USART communication baud rate.
+                                         The baud rate is computed using the following formula:
+                                          - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                          - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+  uint16_t USART_WordLength;          /* Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /* Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /* Specifies the parity mode.
+                                         This parameter can be a value of @ref USART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /* Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/* USART Clock Init Structure definition */  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /* Specifies whether the USART clock is enabled or disabled.
+                             This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /* Specifies the steady state value of the serial clock.
+                             This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /* Specifies the clock transition on which the bit capture is made.
+                             This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
+                             data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                             This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* USART_Word_Length */ 
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+/* USART_Stop_Bits */  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+
+/* USART_Parity */  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+
+/* USART_Mode */ 
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+
+/* USART_Hardware_Flow_Control */
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+
+/* USART_Clock */
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+
+/* USART_Clock_Polarity */  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+
+/* USART_Clock_Phase */
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+
+/* USART_Last_Bit */
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+
+/* USART_Interrupt_definition */  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325) 
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+#define USART_IT_ORE                          USART_IT_ORE_ER 
+
+/* USART_DMA_Requests */
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+
+/* USART_WakeUp_methods */
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+
+/* USART_LIN_Break_Detection_Length */
+#define USART_LINBreakDetectLength_10b       ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b       ((uint16_t)0x0020)
+
+/* USART_IrDA_Low_Power */
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+
+/* USART_Flags */
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_USART_H */
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_usb.h

@@ -0,0 +1,657 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_usb.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the USB 
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_USB_H
+#define __CH32F10x_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef NULL
+#define NULL                    0
+#endif
+
+#ifndef VOID
+#define VOID                    void
+#endif
+#ifndef CONST
+#define CONST                   const
+#endif
+#ifndef BOOL
+typedef unsigned char           BOOL;
+#endif
+#ifndef BOOLEAN
+typedef unsigned char           BOOLEAN;
+#endif
+#ifndef CHAR
+typedef char                    CHAR;
+#endif
+#ifndef INT8
+typedef char                    INT8;
+#endif
+#ifndef INT16
+typedef short                   INT16;
+#endif
+#ifndef INT32
+typedef long                    INT32;
+#endif
+#ifndef UINT8
+typedef unsigned char           UINT8;
+#endif
+#ifndef UINT16
+typedef unsigned short          UINT16;
+#endif
+#ifndef UINT32
+typedef unsigned long           UINT32;
+#endif
+#ifndef UINT8V
+typedef unsigned char volatile  UINT8V;
+#endif
+#ifndef UINT16V
+typedef unsigned short volatile UINT16V;
+#endif
+#ifndef UINT32V
+typedef unsigned long volatile  UINT32V;
+#endif
+
+#ifndef PVOID
+typedef void                    *PVOID;
+#endif
+#ifndef PCHAR
+typedef char                    *PCHAR;
+#endif
+#ifndef PCHAR
+typedef const char              *PCCHAR;
+#endif
+#ifndef PINT8
+typedef char                    *PINT8;
+#endif
+#ifndef PINT16
+typedef short                   *PINT16;
+#endif
+#ifndef PINT32
+typedef long                    *PINT32;
+#endif
+#ifndef PUINT8
+typedef unsigned char           *PUINT8;
+#endif
+#ifndef PUINT16
+typedef unsigned short          *PUINT16;
+#endif
+#ifndef PUINT32
+typedef unsigned long           *PUINT32;
+#endif
+#ifndef PUINT8V
+typedef volatile unsigned char  *PUINT8V;
+#endif
+#ifndef PUINT16V
+typedef volatile unsigned short *PUINT16V;
+#endif
+#ifndef PUINT32V
+typedef volatile unsigned long  *PUINT32V;
+#endif
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/*       USB  */
+#define	R32_USB_CONTROL		(*((PUINT32V)(0x40023400)))	// USB control & interrupt enable & device address
+#define	R8_USB_CTRL			(*((PUINT8V)(0x40023400)))	// USB base control
+#define 	RB_UC_HOST_MODE     0x80      // enable USB host mode: 0=device mode, 1=host mode
+#define 	RB_UC_LOW_SPEED     0x40      // enable USB low speed: 0=12Mbps, 1=1.5Mbps
+#define 	RB_UC_DEV_PU_EN     0x20      // USB device enable and internal pullup resistance enable
+#define 	RB_UC_SYS_CTRL1     0x20      // USB system control high bit
+#define 	RB_UC_SYS_CTRL0     0x10      // USB system control low bit
+#define 	MASK_UC_SYS_CTRL  	0x30      // bit mask of USB system control
+// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control
+//   0 00: disable USB device and disable internal pullup resistance
+//   0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
+//   0 1x: enable USB device and enable internal pullup resistance
+//   1 00: enable USB host and normal status
+//   1 01: enable USB host and force UDP/UDM output SE0 state
+//   1 10: enable USB host and force UDP/UDM output J state
+//   1 11: enable USB host and force UDP/UDM output resume or K state
+#define 	RB_UC_INT_BUSY      0x08      // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
+#define 	RB_UC_RESET_SIE     0x04      // force reset USB SIE, need software clear
+#define 	RB_UC_CLR_ALL       0x02      // force clear FIFO and count of USB
+#define 	RB_UC_DMA_EN        0x01      // DMA enable and DMA interrupt enable for USB
+
+#define	R8_UDEV_CTRL		(*((PUINT8V)(0x40023401)))	// USB device physical prot control
+#define 	RB_UD_PD_DIS        0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define 	RB_UD_DP_PIN        0x20      // ReadOnly: indicate current UDP pin level
+#define 	RB_UD_DM_PIN        0x10      // ReadOnly: indicate current UDM pin level
+#define 	RB_UD_LOW_SPEED     0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
+#define 	RB_UD_GP_BIT        0x02      // general purpose bit
+#define 	RB_UD_PORT_EN       0x01      // enable USB physical port I/O: 0=disable, 1=enable
+
+#define	R8_UHOST_CTRL		R8_UDEV_CTRL				// USB host physical prot control
+#define 	RB_UH_PD_DIS        0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define 	RB_UH_DP_PIN        0x20      // ReadOnly: indicate current UDP pin level
+#define 	RB_UH_DM_PIN        0x10      // ReadOnly: indicate current UDM pin level
+#define 	RB_UH_LOW_SPEED     0x04      // enable USB port low speed: 0=full speed, 1=low speed
+#define 	RB_UH_BUS_RESET     0x02      // control USB bus reset: 0=normal, 1=force bus reset
+#define 	RB_UH_PORT_EN       0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
+
+#define	R8_USB_INT_EN		(*((PUINT8V)(0x40023402)))	// USB interrupt enable
+#define 	RB_UIE_DEV_SOF      0x80      // enable interrupt for SOF received for USB device mode
+#define 	RB_UIE_DEV_NAK      0x40      // enable interrupt for NAK responded for USB device mode
+#define 	RB_UIE_FIFO_OV      0x10      // enable interrupt for FIFO overflow
+#define 	RB_UIE_HST_SOF      0x08      // enable interrupt for host SOF timer action for USB host mode
+#define 	RB_UIE_SUSPEND      0x04      // enable interrupt for USB suspend or resume event
+#define 	RB_UIE_TRANSFER     0x02      // enable interrupt for USB transfer completion
+#define 	RB_UIE_DETECT       0x01      // enable interrupt for USB device detected event for USB host mode
+#define 	RB_UIE_BUS_RST      0x01      // enable interrupt for USB bus reset event for USB device mode
+
+#define	R8_USB_DEV_AD		(*((PUINT8V)(0x40023403)))	// USB device address
+#define 	RB_UDA_GP_BIT       0x80      // general purpose bit
+#define 	MASK_USB_ADDR      	0x7F      // bit mask for USB device address
+
+#define	R32_USB_STATUS		(*((PUINT32V)(0x40023404)))	// USB miscellaneous status & interrupt flag & interrupt status
+#define	R8_USB_MIS_ST		(*((PUINT8V)(0x40023405)))	// USB miscellaneous status
+#define 	RB_UMS_SOF_PRES     0x80      // RO, indicate host SOF timer presage status
+#define 	RB_UMS_SOF_ACT      0x40      // RO, indicate host SOF timer action status for USB host
+#define 	RB_UMS_SIE_FREE     0x20      // RO, indicate USB SIE free status
+#define 	RB_UMS_R_FIFO_RDY   0x10      // RO, indicate USB receiving FIFO ready status (not empty)
+#define 	RB_UMS_BUS_RESET    0x08      // RO, indicate USB bus reset status
+#define 	RB_UMS_SUSPEND      0x04      // RO, indicate USB suspend status
+#define 	RB_UMS_DM_LEVEL     0x02      // RO, indicate UDM level saved at device attached to USB host
+#define 	RB_UMS_DEV_ATTACH   0x01      // RO, indicate device attached status on USB host
+
+#define	R8_USB_INT_FG		(*((PUINT8V)(0x40023406)))	// USB interrupt flag
+#define 	RB_U_IS_NAK		    	0x80	// RO, indicate current USB transfer is NAK received
+#define 	RB_U_TOG_OK 	    	0x40	// RO, indicate current USB transfer toggle is OK
+#define 	RB_U_SIE_FREE   	  0x20	// RO, indicate USB SIE free status
+#define 	RB_UIF_FIFO_OV		  0x10	// FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
+#define 	RB_UIF_HST_SOF		  0x08	// host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
+#define 	RB_UIF_SUSPEND		  0x04	// USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
+#define 	RB_UIF_TRANSFER		  0x02	// USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
+#define 	RB_UIF_DETECT		    0x01	// device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
+#define 	RB_UIF_BUS_RST		  0x01	// bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
+
+#define	R8_USB_INT_ST		(*((PUINT8V)(0x40023407)))	// USB interrupt status
+#define 	RB_UIS_IS_NAK       0x80      // RO, indicate current USB transfer is NAK received for USB device mode
+#define 	RB_UIS_TOG_OK       0x40      // RO, indicate current USB transfer toggle is OK
+#define 	RB_UIS_TOKEN1       0x20      // RO, current token PID code bit 1 received for USB device mode
+#define 	RB_UIS_TOKEN0       0x10      // RO, current token PID code bit 0 received for USB device mode
+#define 	MASK_UIS_TOKEN    	0x30      // RO, bit mask of current token PID code received for USB device mode
+#define 	UIS_TOKEN_OUT     	0x00
+#define 	UIS_TOKEN_SOF     	0x10
+#define 	UIS_TOKEN_IN      	0x20
+#define 	UIS_TOKEN_SETUP   	0x30
+// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
+//   00: OUT token PID received
+//   01: SOF token PID received
+//   10: IN token PID received
+//   11: SETUP token PID received
+#define 	MASK_UIS_ENDP      	0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
+#define 	MASK_UIS_H_RES    	0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
+
+#define	R8_USB_RX_LEN		(*((PUINT8V)(0x40023408)))	// USB receiving length
+#define	R32_USB_BUF_MODE	(*((PUINT32V)(0x4002340c)))	// USB endpoint buffer mode
+#define	R8_UEP4_1_MOD		(*((PUINT8V)(0x4002340c)))	// endpoint 4/1 mode
+#define 	RB_UEP1_RX_EN       0x80      // enable USB endpoint 1 receiving (OUT)
+#define 	RB_UEP1_TX_EN       0x40      // enable USB endpoint 1 transmittal (IN)
+#define 	RB_UEP1_BUF_MOD     0x10      // buffer mode of USB endpoint 1
+// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
+//   0 0 x:  disable endpoint and disable buffer
+//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
+//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
+//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
+//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
+//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
+//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
+#define 	RB_UEP4_RX_EN       0x08      // enable USB endpoint 4 receiving (OUT)
+#define 	RB_UEP4_TX_EN       0x04      // enable USB endpoint 4 transmittal (IN)
+// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
+//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
+//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
+//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
+
+#define	R8_UEP2_3_MOD		(*((PUINT8V)(0x4002340d)))	// endpoint 2/3 mode
+#define 	RB_UEP3_RX_EN       0x80      // enable USB endpoint 3 receiving (OUT)
+#define 	RB_UEP3_TX_EN       0x40      // enable USB endpoint 3 transmittal (IN)
+#define 	RB_UEP3_BUF_MOD     0x10      // buffer mode of USB endpoint 3
+#define 	RB_UEP2_RX_EN       0x08      // enable USB endpoint 2 receiving (OUT)
+#define 	RB_UEP2_TX_EN       0x04      // enable USB endpoint 2 transmittal (IN)
+#define 	RB_UEP2_BUF_MOD     0x01      // buffer mode of USB endpoint 2
+
+#define	R8_UH_EP_MOD		R8_UEP2_3_MOD				//host endpoint mode
+#define 	RB_UH_EP_TX_EN      0x40      // enable USB host OUT endpoint transmittal
+#define 	RB_UH_EP_TBUF_MOD   0x10      // buffer mode of USB host OUT endpoint
+// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
+//   0 x:  disable endpoint and disable buffer
+//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
+//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
+#define 	RB_UH_EP_RX_EN      0x08      // enable USB host IN endpoint receiving
+#define 	RB_UH_EP_RBUF_MOD   0x01      // buffer mode of USB host IN endpoint
+// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
+//   0 x:  disable endpoint and disable buffer
+//   1 0:  64 bytes buffer for receiving (IN endpoint)
+//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
+
+#define	R16_UEP0_DMA		(*((PUINT16V)(0x40023410)))	// endpoint 0 DMA buffer address
+#define	R16_UEP1_DMA		(*((PUINT16V)(0x40023414)))	// endpoint 1 DMA buffer address
+#define	R16_UEP2_DMA		(*((PUINT16V)(0x40023418)))	// endpoint 2 DMA buffer address
+#define	R16_UH_RX_DMA		R16_UEP2_DMA				// host rx endpoint buffer high address
+#define	R16_UEP3_DMA		(*((PUINT16V)(0x4002341c)))	// endpoint 3 DMA buffer address
+#define	R16_UH_TX_DMA		R16_UEP3_DMA				// host tx endpoint buffer high address
+#define	R32_USB_EP0_CTRL	(*((PUINT32V)(0x40023420)))	// endpoint 0 control & transmittal length
+#define	R8_UEP0_T_LEN		(*((PUINT8V)(0x40023420)))	// endpoint 0 transmittal length
+#define	R8_UEP0_CTRL		(*((PUINT8V)(0x40023422)))	// endpoint 0 control
+#define	R32_USB_EP1_CTRL	(*((PUINT32V)(0x40023424)))	// endpoint 1 control & transmittal length
+#define	R8_UEP1_T_LEN		(*((PUINT8V)(0x40023424)))	// endpoint 1 transmittal length
+#define	R8_UEP1_CTRL		(*((PUINT8V)(0x40023426)))	// endpoint 1 control
+#define 	RB_UEP_R_TOG        0x80      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
+#define 	RB_UEP_T_TOG        0x40      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
+#define 	RB_UEP_AUTO_TOG     0x10      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
+#define 	RB_UEP_R_RES1       0x08      // handshake response type high bit for USB endpoint X receiving (OUT)
+#define 	RB_UEP_R_RES0       0x04      // handshake response type low bit for USB endpoint X receiving (OUT)
+#define     MASK_UEP_R_RES    	0x0C      // bit mask of handshake response type for USB endpoint X receiving (OUT)
+#define     UEP_R_RES_ACK     	0x00
+#define     UEP_R_RES_TOUT    	0x04
+#define     UEP_R_RES_NAK     	0x08
+#define     UEP_R_RES_STALL   	0x0C
+// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
+//   00: ACK (ready)
+//   01: no response, time out to host, for non-zero endpoint isochronous transactions
+//   10: NAK (busy)
+//   11: STALL (error)
+#define 	RB_UEP_T_RES1       0x02      // handshake response type high bit for USB endpoint X transmittal (IN)
+#define 	RB_UEP_T_RES0       0x01      // handshake response type low bit for USB endpoint X transmittal (IN)
+#define 	MASK_UEP_T_RES    	0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
+#define 	UEP_T_RES_ACK     	0x00
+#define 	UEP_T_RES_TOUT    	0x01
+#define 	UEP_T_RES_NAK     	0x02
+#define 	UEP_T_RES_STALL   	0x03
+// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
+//   00: DATA0 or DATA1 then expecting ACK (ready)
+//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
+//   10: NAK (busy)
+//   11: STALL (error)
+
+#define	R8_UH_SETUP		    R8_UEP1_CTRL				// host aux setup
+#define 	RB_UH_PRE_PID_EN    0x80      // USB host PRE PID enable for low speed device via hub
+#define 	RB_UH_SOF_EN        0x40      // USB host automatic SOF enable
+
+#define	R32_USB_EP2_CTRL	(*((PUINT32V)(0x40023428)))	// endpoint 2 control & transmittal length
+#define	R8_UEP2_T_LEN		(*((PUINT8V)(0x40023428)))	// endpoint 2 transmittal length
+#define	R8_UEP2_CTRL		(*((PUINT8V)(0x4002342a)))	// endpoint 2 control
+
+#define	R8_UH_EP_PID		R8_UEP2_T_LEN				// host endpoint and PID
+#define 	MASK_UH_TOKEN     	0xF0      // bit mask of token PID for USB host transfer
+#define 	MASK_UH_ENDP      	0x0F      // bit mask of endpoint number for USB host transfer
+
+#define	R8_UH_RX_CTRL		R8_UEP2_CTRL				// host receiver endpoint control
+#define 	RB_UH_R_TOG         0x80      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
+#define 	RB_UH_R_AUTO_TOG    0x10      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define 	RB_UH_R_RES         0x04      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
+
+#define	R32_USB_EP3_CTRL	(*((PUINT32V)(0x4002342c)))	// endpoint 3 control & transmittal length
+#define	R8_UEP3_T_LEN		(*((PUINT8V)(0x4002342c)))	// endpoint 3 transmittal length
+#define	R8_UEP3_CTRL		(*((PUINT8V)(0x4002342e)))	// endpoint 3 control
+#define	R8_UH_TX_LEN		R8_UEP3_T_LEN				// host transmittal endpoint transmittal length
+
+#define	R8_UH_TX_CTRL		R8_UEP3_CTRL				// host transmittal endpoint control
+#define 	RB_UH_T_TOG         0x40      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
+#define 	RB_UH_T_AUTO_TOG    0x10      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define 	RB_UH_T_RES         0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
+
+#define	R32_USB_EP4_CTRL	(*((PUINT32V)(0x40023430)))	// endpoint 4 control & transmittal length
+#define	R8_UEP4_T_LEN		(*((PUINT8V)(0x40023430)))	// endpoint 4 transmittal length
+#define	R8_UEP4_CTRL		(*((PUINT8V)(0x40023432)))	// endpoint 4 control
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	//__CH32F10x_USB_H
+
+
+#ifndef __USB_TYPE__
+#define __USB_TYPE__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USB constant and structure define */
+
+/* USB PID */
+#ifndef USB_PID_SETUP
+#define USB_PID_NULL            0x00    /* reserved PID */
+#define USB_PID_SOF             0x05
+#define USB_PID_SETUP           0x0D
+#define USB_PID_IN              0x09
+#define USB_PID_OUT             0x01
+#define USB_PID_ACK             0x02
+#define USB_PID_NAK             0x0A
+#define USB_PID_STALL           0x0E
+#define USB_PID_DATA0           0x03
+#define USB_PID_DATA1           0x0B
+#define USB_PID_PRE             0x0C
+#endif
+
+/* USB standard device request code */
+#ifndef USB_GET_DESCRIPTOR
+#define USB_GET_STATUS          0x00
+#define USB_CLEAR_FEATURE       0x01
+#define USB_SET_FEATURE         0x03
+#define USB_SET_ADDRESS         0x05
+#define USB_GET_DESCRIPTOR      0x06
+#define USB_SET_DESCRIPTOR      0x07
+#define USB_GET_CONFIGURATION   0x08
+#define USB_SET_CONFIGURATION   0x09
+#define USB_GET_INTERFACE       0x0A
+#define USB_SET_INTERFACE       0x0B
+#define USB_SYNCH_FRAME         0x0C
+#endif
+
+/* USB hub class request code */
+#ifndef HUB_GET_DESCRIPTOR
+#define HUB_GET_STATUS          0x00
+#define HUB_CLEAR_FEATURE       0x01
+#define HUB_GET_STATE           0x02
+#define HUB_SET_FEATURE         0x03
+#define HUB_GET_DESCRIPTOR      0x06
+#define HUB_SET_DESCRIPTOR      0x07
+#endif
+
+/* USB HID class request code */
+#ifndef HID_GET_REPORT
+#define HID_GET_REPORT          0x01
+#define HID_GET_IDLE            0x02
+#define HID_GET_PROTOCOL        0x03
+#define HID_SET_REPORT          0x09
+#define HID_SET_IDLE            0x0A
+#define HID_SET_PROTOCOL        0x0B
+#endif
+
+/* Bit define for USB request type */
+#ifndef USB_REQ_TYP_MASK
+#define USB_REQ_TYP_IN          0x80            /* control IN, device to host */
+#define USB_REQ_TYP_OUT         0x00            /* control OUT, host to device */
+#define USB_REQ_TYP_READ        0x80            /* control read, device to host */
+#define USB_REQ_TYP_WRITE       0x00            /* control write, host to device */
+#define USB_REQ_TYP_MASK        0x60            /* bit mask of request type */
+#define USB_REQ_TYP_STANDARD    0x00
+#define USB_REQ_TYP_CLASS       0x20
+#define USB_REQ_TYP_VENDOR      0x40
+#define USB_REQ_TYP_RESERVED    0x60
+#define USB_REQ_RECIP_MASK      0x1F            /* bit mask of request recipient */
+#define USB_REQ_RECIP_DEVICE    0x00
+#define USB_REQ_RECIP_INTERF    0x01
+#define USB_REQ_RECIP_ENDP      0x02
+#define USB_REQ_RECIP_OTHER     0x03
+#endif
+
+/* USB request type for hub class request */
+#ifndef HUB_GET_HUB_DESCRIPTOR
+#define HUB_CLEAR_HUB_FEATURE   0x20
+#define HUB_CLEAR_PORT_FEATURE  0x23
+#define HUB_GET_BUS_STATE       0xA3
+#define HUB_GET_HUB_DESCRIPTOR  0xA0
+#define HUB_GET_HUB_STATUS      0xA0
+#define HUB_GET_PORT_STATUS     0xA3
+#define HUB_SET_HUB_DESCRIPTOR  0x20
+#define HUB_SET_HUB_FEATURE     0x20
+#define HUB_SET_PORT_FEATURE    0x23
+#endif
+
+/* Hub class feature selectors */
+#ifndef HUB_PORT_RESET
+#define HUB_C_HUB_LOCAL_POWER   0
+#define HUB_C_HUB_OVER_CURRENT  1
+#define HUB_PORT_CONNECTION     0
+#define HUB_PORT_ENABLE         1
+#define HUB_PORT_SUSPEND        2
+#define HUB_PORT_OVER_CURRENT   3
+#define HUB_PORT_RESET          4
+#define HUB_PORT_POWER          8
+#define HUB_PORT_LOW_SPEED      9
+#define HUB_C_PORT_CONNECTION   16
+#define HUB_C_PORT_ENABLE       17
+#define HUB_C_PORT_SUSPEND      18
+#define HUB_C_PORT_OVER_CURRENT 19
+#define HUB_C_PORT_RESET        20
+#endif
+
+/* USB descriptor type */
+#ifndef USB_DESCR_TYP_DEVICE
+#define USB_DESCR_TYP_DEVICE    0x01
+#define USB_DESCR_TYP_CONFIG    0x02
+#define USB_DESCR_TYP_STRING    0x03
+#define USB_DESCR_TYP_INTERF    0x04
+#define USB_DESCR_TYP_ENDP      0x05
+#define USB_DESCR_TYP_QUALIF    0x06
+#define USB_DESCR_TYP_SPEED     0x07
+#define USB_DESCR_TYP_OTG       0x09
+#define USB_DESCR_TYP_HID       0x21
+#define USB_DESCR_TYP_REPORT    0x22
+#define USB_DESCR_TYP_PHYSIC    0x23
+#define USB_DESCR_TYP_CS_INTF   0x24
+#define USB_DESCR_TYP_CS_ENDP   0x25
+#define USB_DESCR_TYP_HUB       0x29
+#endif
+
+/* USB device class */
+#ifndef USB_DEV_CLASS_HUB
+#define USB_DEV_CLASS_RESERVED  0x00
+#define USB_DEV_CLASS_AUDIO     0x01
+#define USB_DEV_CLASS_COMMUNIC  0x02
+#define USB_DEV_CLASS_HID       0x03
+#define USB_DEV_CLASS_MONITOR   0x04
+#define USB_DEV_CLASS_PHYSIC_IF 0x05
+#define USB_DEV_CLASS_POWER     0x06
+#define USB_DEV_CLASS_PRINTER   0x07
+#define USB_DEV_CLASS_STORAGE   0x08
+#define USB_DEV_CLASS_HUB       0x09
+#define USB_DEV_CLASS_VEN_SPEC  0xFF
+#endif
+
+/* USB endpoint type and attributes */
+#ifndef USB_ENDP_TYPE_MASK
+#define USB_ENDP_DIR_MASK       0x80
+#define USB_ENDP_ADDR_MASK      0x0F
+#define USB_ENDP_TYPE_MASK      0x03
+#define USB_ENDP_TYPE_CTRL      0x00
+#define USB_ENDP_TYPE_ISOCH     0x01
+#define USB_ENDP_TYPE_BULK      0x02
+#define USB_ENDP_TYPE_INTER     0x03
+#endif
+
+#ifndef USB_DEVICE_ADDR
+#define	USB_DEVICE_ADDR		     	0x02	
+#endif
+#ifndef DEFAULT_ENDP0_SIZE
+#define DEFAULT_ENDP0_SIZE      8       /* default maximum packet size for endpoint 0 */
+#endif
+#ifndef MAX_PACKET_SIZE
+#define MAX_PACKET_SIZE         64      /* maximum packet size */
+#endif
+#ifndef USB_BO_CBW_SIZE
+#define USB_BO_CBW_SIZE			    0x1F	
+#define USB_BO_CSW_SIZE			    0x0D	
+#endif
+#ifndef USB_BO_CBW_SIG0
+#define USB_BO_CBW_SIG0         0x55    
+#define USB_BO_CBW_SIG1         0x53
+#define USB_BO_CBW_SIG2         0x42
+#define USB_BO_CBW_SIG3         0x43
+#define USB_BO_CSW_SIG0         0x55   
+#define USB_BO_CSW_SIG1         0x53
+#define USB_BO_CSW_SIG2         0x42
+#define USB_BO_CSW_SIG3         0x53
+#endif
+
+#ifndef __PACKED
+#define	__PACKED			__packed	
+#endif
+
+typedef struct _USB_SETUP_REQ {
+    UINT8 bRequestType;
+    UINT8 bRequest;
+    UINT16 wValue;
+    UINT16 wIndex;
+    UINT16 wLength;
+} __attribute__((packed)) USB_SETUP_REQ, *PUSB_SETUP_REQ;
+
+
+typedef struct _USB_DEVICE_DESCR {
+    UINT8 bLength;
+    UINT8 bDescriptorType;
+    UINT16 bcdUSB;
+    UINT8 bDeviceClass;
+    UINT8 bDeviceSubClass;
+    UINT8 bDeviceProtocol;
+    UINT8 bMaxPacketSize0;
+    UINT16 idVendor;
+    UINT16 idProduct;
+    UINT16 bcdDevice;
+    UINT8 iManufacturer;
+    UINT8 iProduct;
+    UINT8 iSerialNumber;
+    UINT8 bNumConfigurations;
+}__attribute__((packed)) USB_DEV_DESCR, *PUSB_DEV_DESCR;
+
+
+typedef struct _USB_CONFIG_DESCR {
+    UINT8 bLength;
+    UINT8 bDescriptorType;
+    UINT16 wTotalLength;
+    UINT8 bNumInterfaces;
+    UINT8 bConfigurationValue;
+    UINT8 iConfiguration;
+    UINT8 bmAttributes;
+    UINT8 MaxPower;
+}__attribute__((packed)) USB_CFG_DESCR, *PUSB_CFG_DESCR;
+
+
+typedef struct _USB_INTERF_DESCR {
+    UINT8 bLength;
+    UINT8 bDescriptorType;
+    UINT8 bInterfaceNumber;
+    UINT8 bAlternateSetting;
+    UINT8 bNumEndpoints;
+    UINT8 bInterfaceClass;
+    UINT8 bInterfaceSubClass;
+    UINT8 bInterfaceProtocol;
+    UINT8 iInterface;
+}__attribute__((packed)) USB_ITF_DESCR, *PUSB_ITF_DESCR;
+
+
+typedef struct _USB_ENDPOINT_DESCR {
+    UINT8 bLength;
+    UINT8 bDescriptorType;
+    UINT8 bEndpointAddress;
+    UINT8 bmAttributes;
+    UINT16 wMaxPacketSize;
+    UINT8 bInterval;
+}__attribute__((packed)) USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
+
+
+typedef struct _USB_CONFIG_DESCR_LONG {
+    USB_CFG_DESCR   cfg_descr;
+    USB_ITF_DESCR   itf_descr;
+    USB_ENDP_DESCR  endp_descr[1];
+}__attribute__((packed)) USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
+
+
+typedef struct _USB_HUB_DESCR {
+    UINT8 bDescLength;
+    UINT8 bDescriptorType;
+    UINT8 bNbrPorts;
+    UINT8 wHubCharacteristicsL;
+    UINT8 wHubCharacteristicsH;
+    UINT8 bPwrOn2PwrGood;
+    UINT8 bHubContrCurrent;
+    UINT8 DeviceRemovable;
+    UINT8 PortPwrCtrlMask;
+}__attribute__((packed)) USB_HUB_DESCR, *PUSB_HUB_DESCR;
+
+
+typedef struct _USB_HID_DESCR {
+    UINT8 bLength;
+    UINT8 bDescriptorType;
+    UINT16 bcdHID;
+    UINT8 bCountryCode;
+    UINT8 bNumDescriptors;
+    UINT8 bDescriptorTypeX;
+    UINT8 wDescriptorLengthL;
+    UINT8 wDescriptorLengthH;
+}__attribute__((packed)) USB_HID_DESCR, *PUSB_HID_DESCR;
+
+
+typedef struct _UDISK_BOC_CBW {/* command of BulkOnly USB-FlashDisk */
+    UINT32 mCBW_Sig;
+    UINT32 mCBW_Tag;
+    UINT32 mCBW_DataLen;                /* uppest byte of data length, always is 0 */
+    UINT8 mCBW_Flag;                    /* transfer direction and etc. */
+    UINT8 mCBW_LUN;
+    UINT8 mCBW_CB_Len;                  /* length of command block */
+    UINT8 mCBW_CB_Buf[16];              /* command block buffer */
+}__attribute__((packed)) UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
+
+
+typedef struct _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */
+    UINT32 mCBW_Sig;
+    UINT32 mCBW_Tag;
+    UINT32 mCSW_Residue;                /* return: remainder bytes */         /* uppest byte of remainder length, always is 0 */
+    UINT8 mCSW_Status;                  /* return: result status */
+}__attribute__((packed)) UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
+
+
+extern PUINT8  pEP0_RAM_Addr;						//ep0(64)+ep4_out(64)+ep4_in(64)
+extern PUINT8  pEP1_RAM_Addr;						//ep1_out(64)+ep1_in(64)
+extern PUINT8  pEP2_RAM_Addr;						//ep2_out(64)+ep2_in(64)
+extern PUINT8  pEP3_RAM_Addr;						//ep3_out(64)+ep3_in(64)
+
+#define	pSetupReqPak		((PUSB_SETUP_REQ)pEP0_RAM_Addr)
+#define pEP0_DataBuf		(pEP0_RAM_Addr)
+#define pEP1_OUT_DataBuf	(pEP1_RAM_Addr)
+#define pEP1_IN_DataBuf		(pEP1_RAM_Addr+64)
+#define pEP2_OUT_DataBuf	(pEP2_RAM_Addr)
+#define pEP2_IN_DataBuf		(pEP2_RAM_Addr+64)
+#define pEP3_OUT_DataBuf	(pEP3_RAM_Addr)
+#define pEP3_IN_DataBuf		(pEP3_RAM_Addr+64)
+#define pEP4_OUT_DataBuf	(pEP0_RAM_Addr+64)
+#define pEP4_IN_DataBuf		(pEP0_RAM_Addr+128)	 
+	 
+
+	 
+void USB_DeviceInit( void );			
+void USB_DevTransProcess( void );		 
+	 
+void DevEP1_OUT_Deal( UINT8 l );		
+void DevEP2_OUT_Deal( UINT8 l );	
+void DevEP3_OUT_Deal( UINT8 l );		
+void DevEP4_OUT_Deal( UINT8 l );
+
+void DevEP1_IN_Deal( UINT8 l );		
+void DevEP2_IN_Deal( UINT8 l );		
+void DevEP3_IN_Deal( UINT8 l );		
+void DevEP4_IN_Deal( UINT8 l );		       
+
+#define EP1_GetINSta()		(R8_UEP1_CTRL&UEP_T_RES_NAK)		
+#define EP2_GetINSta()		(R8_UEP2_CTRL&UEP_T_RES_NAK)		
+#define EP3_GetINSta()		(R8_UEP3_CTRL&UEP_T_RES_NAK)		
+#define EP4_GetINSta()		(R8_UEP4_CTRL&UEP_T_RES_NAK)	
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __USB_TYPE__
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_usb_host.h

@@ -0,0 +1,98 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_usb_host.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the USB firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32F10x_USBHOST_H__
+#define __CH32F10x_USBHOST_H__
+
+#include "ch32f10x_usb.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define ERR_SUCCESS          0x00    
+#define ERR_USB_CONNECT      0x15   
+#define ERR_USB_DISCON       0x16    
+#define ERR_USB_BUF_OVER     0x17   
+#define ERR_USB_DISK_ERR     0x1F   
+#define ERR_USB_TRANSFER     0x20    
+#define ERR_USB_UNSUPPORT    0xFB    
+#define ERR_USB_UNKNOWN      0xFE    
+#define ERR_AOA_PROTOCOL     0x41    
+
+#define ROOT_DEV_DISCONNECT  0
+#define ROOT_DEV_CONNECTED   1
+#define ROOT_DEV_FAILED      2
+#define ROOT_DEV_SUCCESS     3
+#define DEV_TYPE_KEYBOARD   ( USB_DEV_CLASS_HID | 0x20 )
+#define DEV_TYPE_MOUSE      ( USB_DEV_CLASS_HID | 0x30 )
+#define DEF_AOA_DEVICE       0xF0
+#define DEV_TYPE_UNKNOW 	   0xFF
+
+#define HUB_MAX_PORTS          	4
+#define WAIT_USB_TOUT_200US     3000  
+
+typedef struct
+{
+    UINT8   DeviceStatus;          
+    UINT8   DeviceAddress;             
+    UINT8   DeviceSpeed;               
+    UINT8   DeviceType;                
+		UINT16  DeviceVID;
+		UINT16  DevicePID;
+    UINT8   GpVar[4];                    
+    UINT8   GpHUBPortNum;                
+} _RootHubDev;
+
+
+extern _RootHubDev  ThisUsbDev;
+extern UINT8  UsbDevEndp0Size;            
+extern UINT8  FoundNewDev;
+
+extern PUINT8  pHOST_RX_RAM_Addr;
+extern PUINT8  pHOST_TX_RAM_Addr;
+#define pSetupReq   ((PUSB_SETUP_REQ)pHOST_TX_RAM_Addr)
+
+extern const UINT8  SetupGetDevDescr[];   
+extern const UINT8  SetupGetCfgDescr[];   
+extern const UINT8  SetupSetUsbAddr[];    
+extern const UINT8  SetupSetUsbConfig[];  
+extern const UINT8  SetupSetUsbInterface[];
+extern const UINT8  SetupClrEndpStall[];   
+
+
+void  DisableRootHubPort(void)  ;           
+UINT8   AnalyzeRootHub( void ) ;        
+void    SetHostUsbAddr( UINT8 addr );               
+void    SetUsbSpeed( UINT8 FullSpeed );           
+void    ResetRootHubPort(void);                          
+UINT8   EnableRootHubPort(void);                         
+void    SelectHubPort( UINT8 HubPortIndex );
+UINT8   WaitUSB_Interrupt( void );               
+UINT8   USBHostTransact( UINT8 endp_pid, UINT8 tog, UINT32 timeout ); 
+UINT8   HostCtrlTransfer( PUINT8 DataBuf, PUINT8 RetLen );  
+void CopySetupReqPkg( const UINT8 *pReqPkt );          
+UINT8 CtrlGetDeviceDescr( PUINT8 DataBuf );               
+UINT8 CtrlGetConfigDescr( PUINT8 DataBuf );                  
+UINT8 CtrlSetUsbAddress( UINT8 addr );              
+UINT8 CtrlSetUsbConfig( UINT8 cfg );               
+UINT8 CtrlClearEndpStall( UINT8 endp ) ;            
+UINT8 CtrlSetUsbIntercace( UINT8 cfg );				
+
+void    USB_HostInit( void );                     
+UINT8 InitRootDevice( PUINT8 DataBuf ); 
+UINT8   HubGetPortStatus( UINT8 HubPortIndex );        // 查询HUB端口状态,返回在TxBuffer中
+UINT8   HubSetPortFeature( UINT8 HubPortIndex, UINT8 FeatureSelt );  // 设置HUB端口特性
+UINT8   HubClearPortFeature( UINT8 HubPortIndex, UINT8 FeatureSelt );  // 清除HUB端口特性
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __CH32F10x_USBHOST_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/inc/ch32f10x_wwdg.h

@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_wwdg.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the WWDG 
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#ifndef __CH32F10x_WWDG_H
+#define __CH32F10x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+
+/* WWDG_Prescaler */  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+
+  
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32F10x_WWDG_H */
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_bkp.c

@@ -0,0 +1,242 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_bkp.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the BKP firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_bkp.h"
+#include "ch32f10x_rcc.h"
+
+/* BKP registers bit address in the alias region */
+#define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
+
+/* TPCTLR Register */
+
+/* Alias word address of TPAL bit */
+#define TPCTLR_OFFSET         (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber    0x01
+#define TPCTLR_TPAL_BB        (PERIPH_BB_BASE + (TPCTLR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber     0x00
+#define TPCTLR_TPE_BB         (PERIPH_BB_BASE + (TPCTLR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* TPCSR Register */
+
+/* Alias word address of TPIE bit */
+#define TPCSR_OFFSET        (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber    0x02
+#define TPCSR_TPIE_BB       (PERIPH_BB_BASE + (TPCSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber     0x09
+#define TPCSR_TIF_BB        (PERIPH_BB_BASE + (TPCSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber     0x08
+#define TPCSR_TEF_BB        (PERIPH_BB_BASE + (TPCSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+/* BKP registers bit mask */
+
+/* OCTLR register bit mask */
+#define OCTLR_CAL_MASK    ((uint16_t)0xFF80)
+#define OCTLR_MASK        ((uint16_t)0xFC7F)
+
+/*********************************************************************
+ * @fn      BKP_DeInit
+ *
+ * @brief   Deinitializes the BKP peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void BKP_DeInit( void )
+{
+    RCC_BackupResetCmd( ENABLE );
+    RCC_BackupResetCmd( DISABLE );
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinLevelConfig
+ *
+ * @brief   Configures the Tamper Pin active level.
+ *
+ * @param   BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ *            BKP_TamperPinLevel_High - Tamper pin active on high level.
+ *            BKP_TamperPinLevel_Low - Tamper pin active on low level.
+ *
+ * @return  none
+ */
+void BKP_TamperPinLevelConfig( uint16_t BKP_TamperPinLevel )
+{
+    *( __IO uint32_t * ) TPCTLR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinCmd
+ *
+ * @brief   Enables or disables the Tamper Pin activation.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_TamperPinCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) TPCTLR_TPE_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      BKP_ITConfig
+ *
+ * @brief   Enables or disables the Tamper Pin Interrupt.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_ITConfig( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) TPCSR_TPIE_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      BKP_RTCOutputConfig
+ *
+ * @brief   Select the RTC output source to output on the Tamper pin.
+ *
+ * @param   BKP_RTCOutputSource - specifies the RTC output source.
+ *            BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
+ *            BKP_RTCOutputSource_CalibClock - output the RTC clock with
+ *        frequency divided by 64 on the Tamper pin.
+ *            BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
+ *        on the Tamper pin.
+ *            BKP_RTCOutputSource_Second - output the RTC Second pulse
+ *        signal on the Tamper pin.
+ *
+ * @return  none
+ */
+void BKP_RTCOutputConfig( uint16_t BKP_RTCOutputSource )
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_MASK;
+    tmpreg |= BKP_RTCOutputSource;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_SetRTCCalibrationValue
+ *
+ * @brief   Sets RTC Clock Calibration value.
+ *
+ * @param   CalibrationValue - specifies the RTC Clock Calibration value.
+ *            This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void BKP_SetRTCCalibrationValue( uint8_t CalibrationValue )
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_CAL_MASK;
+    tmpreg |= CalibrationValue;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_WriteBackupRegister
+ *
+ * @brief   Writes user data to the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *          Data - data to write.
+ *
+ * @return  none
+ */
+void BKP_WriteBackupRegister( uint16_t BKP_DR, uint16_t Data )
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = ( uint32_t )BKP_BASE;
+    tmp += BKP_DR;
+    *( __IO uint32_t * ) tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      BKP_ReadBackupRegister
+ *
+ * @brief   Reads data from the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *            This parameter can be BKP_DRx where x=[1, 42].
+ *
+ * @return  none
+ */
+uint16_t BKP_ReadBackupRegister( uint16_t BKP_DR )
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = ( uint32_t )BKP_BASE;
+    tmp += BKP_DR;
+
+    return ( *( __IO uint16_t * ) tmp );
+}
+
+/*********************************************************************
+ * @fn      BKP_GetFlagStatus
+ *
+ * @brief   Checks whether the Tamper Pin Event flag is set or not.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus BKP_GetFlagStatus( void )
+{
+    return ( FlagStatus )( *( __IO uint32_t * ) TPCSR_TEF_BB );
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearFlag
+ *
+ * @brief   Clears Tamper Pin Event pending flag.
+ *
+ * @return  none
+ */
+void BKP_ClearFlag( void )
+{
+    BKP->TPCSR |= BKP_CTE;
+}
+
+/*********************************************************************
+ * @fn      BKP_GetITStatus
+ *
+ * @brief   Checks whether the Tamper Pin Interrupt has occurred or not.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus BKP_GetITStatus( void )
+{
+    return ( ITStatus )( *( __IO uint32_t * ) TPCSR_TIF_BB );
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearITPendingBit
+ *
+ * @brief   Clears Tamper Pin Interrupt pending bit.
+ *
+ * @return  none
+ */
+void BKP_ClearITPendingBit( void )
+{
+    BKP->TPCSR |= BKP_CTI;
+}
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_crc.c

@@ -0,0 +1,107 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_crc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the CRC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_crc.h"
+
+
+/*********************************************************************
+ * @fn      CRC_ResetDR
+ *
+ * @brief   Resets the CRC Data register (DR).
+ *
+ * @return  none
+ */
+void CRC_ResetDR( void )
+{
+    CRC->CTLR = CRC_CTLR_RESET;
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given data word(32-bit).
+ *
+ * @param   Data - data word(32-bit) to compute its CRC.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcCRC( uint32_t Data )
+{
+    CRC->DATAR = Data;
+
+    return ( CRC->DATAR );
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcBlockCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ *
+ * @param   pBuffer - pointer to the buffer containing the data to be computed.
+ *          BufferLength - length of the buffer to be computed.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcBlockCRC( uint32_t pBuffer[], uint32_t BufferLength )
+{
+    uint32_t index = 0;
+
+    for( index = 0; index < BufferLength; index++ )
+    {
+        CRC->DATAR = pBuffer[index];
+    }
+
+    return ( CRC->DATAR );
+}
+
+/*********************************************************************
+ * @fn      CRC_GetCRC
+ *
+ * @brief   Returns the current CRC value.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_GetCRC( void )
+{
+    return ( CRC->IDATAR );
+}
+
+/*********************************************************************
+ * @fn      CRC_SetIDRegister
+ *
+ * @brief   Stores a 8-bit data in the Independent Data(ID) register.
+ *
+ * @param   IDValue - 8-bit value to be stored in the ID register.
+ *
+ * @return  none
+ */
+void CRC_SetIDRegister( uint8_t IDValue )
+{
+    CRC->IDATAR = IDValue;
+}
+
+/*********************************************************************
+ * @fn      CRC_GetIDRegister
+ *
+ * @brief   Returns the 8-bit data stored in the Independent Data(ID) register.
+ *
+ * @return  8-bit value of the ID register.
+ */
+uint8_t CRC_GetIDRegister( void )
+{
+    return ( CRC->IDATAR );
+}
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_dac.c

@@ -0,0 +1,253 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_dac.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the DAC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ****************************************************************************************/
+#include "ch32f10x_dac.h"
+#include "ch32f10x_rcc.h"
+
+/* CTLR register Mask */
+#define CTLR_CLEAR_MASK            ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTR masks */
+#define DUAL_SWTR_SET              ((uint32_t)0x00000003)
+#define DUAL_SWTR_RESET            ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+
+
+/*********************************************************************
+ * @fn      DAC_DeInit
+ *
+ * @brief   Deinitializes the DAC peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void DAC_DeInit( void )
+{
+    RCC_APB1PeriphResetCmd( RCC_APB1Periph_DAC, ENABLE );
+    RCC_APB1PeriphResetCmd( RCC_APB1Periph_DAC, DISABLE );
+}
+
+/*********************************************************************
+ * @fn      DAC_Init
+ *
+ * @brief   Initializes the DAC peripheral according to the specified parameters in
+ *        the DAC_InitStruct.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          DAC_InitStruct - pointer to a DAC_InitTypeDef structure.
+ *
+ * @return  none
+ */
+void DAC_Init( uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct )
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+    tmpreg1 = DAC->CTLR;
+    tmpreg1 &= ~( CTLR_CLEAR_MASK << DAC_Channel );
+    tmpreg2 = ( DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+                DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer );
+    tmpreg1 |= tmpreg2 << DAC_Channel;
+    DAC->CTLR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      DAC_StructInit
+ *
+ * @brief   Fills each DAC_InitStruct member with its default value.
+ *
+ * @param   DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized.
+ *
+ * @return  none
+ */
+void DAC_StructInit( DAC_InitTypeDef *DAC_InitStruct )
+{
+    DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+    DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+    DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+    DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/*********************************************************************
+ * @fn      DAC_Cmd
+ *
+ * @brief   Enables or disables the specified DAC channel.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_Cmd( uint32_t DAC_Channel, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        DAC->CTLR |= ( DAC_EN1 << DAC_Channel );
+    }
+    else
+    {
+        DAC->CTLR &= ~( DAC_EN1 << DAC_Channel );
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_DMACmd
+ *
+ * @brief   Enables or disables the specified DAC channel DMA request.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_DMACmd( uint32_t DAC_Channel, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        DAC->CTLR |= ( DAC_DMAEN1 << DAC_Channel );
+    }
+    else
+    {
+        DAC->CTLR &= ~( DAC_DMAEN1 << DAC_Channel );
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_SoftwareTriggerCmd
+ *
+ * @brief   Enables or disables the selected DAC channel software trigger.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_SoftwareTriggerCmd( uint32_t DAC_Channel, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        DAC->SWTR |= ( uint32_t )DAC_SWTRIG1 << ( DAC_Channel >> 4 );
+    }
+    else
+    {
+        DAC->SWTR &= ~( ( uint32_t )DAC_SWTRIG1 << ( DAC_Channel >> 4 ) );
+    }
+}
+
+
+/*********************************************************************
+ * @fn      DAC_WaveGenerationCmd
+ *
+ * @brief   Enables or disables the selected DAC channel wave generation.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          DAC_Wave - Specifies the wave type to enable or disable.
+ *            DAC_Wave_Noise - noise wave generation
+ *            DAC_Wave_Triangle - triangle wave generation
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_WaveGenerationCmd( uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        DAC->CTLR |= DAC_Wave << DAC_Channel;
+    }
+    else
+    {
+        DAC->CTLR &= ~( DAC_Wave << DAC_Channel );
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_SetChannel1Data
+ *
+ * @brief   Set the specified data holding register value for DAC channel1.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *          Data - Data to be loaded in the selected data holding register.
+ *
+ * @return  none
+ */
+void DAC_SetChannel1Data( uint32_t DAC_Align, uint16_t Data )
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = ( uint32_t )DAC_BASE;
+    tmp += DHR12R1_OFFSET + DAC_Align;
+
+    *( __IO uint32_t * ) tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      DAC_SetChannel2Data
+ *
+ * @brief   Set the specified data holding register value for DAC channel2.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *            Data - Data to be loaded in the selected data holding register.
+ *
+ * @return  none
+ */
+void DAC_SetChannel2Data( uint32_t DAC_Align, uint16_t Data )
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = ( uint32_t )DAC_BASE;
+    tmp += DHR12R2_OFFSET + DAC_Align;
+
+    *( __IO uint32_t * )tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      DAC_GetDataOutputValue
+ *
+ * @brief   Returns the last data output value of the selected DAC channel.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *
+ * @return  none
+ */
+uint16_t DAC_GetDataOutputValue( uint32_t DAC_Channel )
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = ( uint32_t ) DAC_BASE ;
+    tmp += DOR_OFFSET + ( ( uint32_t )DAC_Channel >> 2 );
+
+    return ( uint16_t )( *( __IO uint32_t * ) tmp );
+}
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_dbgmcu.c

@@ -0,0 +1,92 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_dbgmcu.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the DBGMCU firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ****************************************************************************************/
+#include "ch32f10x_dbgmcu.h"
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/*********************************************************************
+ * @fn      DBGMCU_GetREVID
+ *
+ * @brief   Returns the device identifier.
+ *
+ * @return Revision identifier.
+ */
+uint32_t DBGMCU_GetREVID( void )
+{
+    return( DBGMCU->IDCODE >> 16 );
+}
+
+/*********************************************************************
+ * @fn      DBGMCU_GetDEVID
+ *
+ * @brief   Returns the device identifier.
+ *
+ * @return Device identifier.
+ */
+uint32_t DBGMCU_GetDEVID( void )
+{
+    return( DBGMCU->IDCODE & IDCODE_DEVID_MASK );
+}
+
+/*********************************************************************
+ * @fn      DBGMCU_Config
+ *
+ * @brief   Configures the specified peripheral and low power mode behavior
+ *        when the MCU under Debug mode.
+ *
+ * @param   DBGMCU_Periph - specifies the peripheral and low power mode.
+ *          DBGMCU_SLEEP -  Keep debugger connection during SLEEP mode
+ *          DBGMCU_STOP - Keep debugger connection during STOP mode
+ *          DBGMCU_STANDBY -  Keep debugger connection during STANDBY mode
+ *          DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
+ *          DBGMCU_WWDG_STOP -  Debug WWDG stopped when Core is halted
+ *          DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
+ *          DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
+ *          DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted
+ *          DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted
+ *          DBGMCU_CAN1_STOP -Debug CAN2 stopped when Core is halted
+ *          DBGMCU_I2C1_SMBUS_TIMEOUT - I2C1 SMBUS timeout mode stopped when Core is halted
+ *          DBGMCU_I2C2_SMBUS_TIMEOUT - I2C2 SMBUS timeout mode stopped when Core is halted
+ *          DBGMCU_TIM5_STOP - TIM5 counter stopped when Core is halted
+ *          DBGMCU_TIM6_STOP - TIM6 counter stopped when Core is halted
+ *          DBGMCU_TIM7_STOP - TIM7 counter stopped when Core is halted
+ *          DBGMCU_TIM8_STOP - TIM8 counter stopped when Core is halted
+ *          DBGMCU_CAN2_STOP - Debug CAN2 stopped when Core is halted
+ *          DBGMCU_TIM15_STOP - TIM15 counter stopped when Core is halted
+ *          DBGMCU_TIM16_STOP - TIM16 counter stopped when Core is halted
+ *          DBGMCU_TIM17_STOP - TIM17 counter stopped when Core is halted
+ *          DBGMCU_TIM9_STOP - TIM9 counter stopped when Core is halted
+ *          DBGMCU_TIM10_STOP - TIM10 counter stopped when Core is halted
+ *          DBGMCU_TIM11_STOP - TIM11 counter stopped when Core is halted
+ *          DBGMCU_TIM12_STOP - TIM12 counter stopped when Core is halted
+ *          DBGMCU_TIM13_STOP -  TIM13 counter stopped when Core is halted
+ *          DBGMCU_TIM14_STOP - TIM14 counter stopped when Core is halted
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void DBGMCU_Config( uint32_t DBGMCU_Periph, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        DBGMCU->CFGR |= DBGMCU_Periph;
+    }
+    else
+    {
+        DBGMCU->CFGR &= ~DBGMCU_Periph;
+    }
+}
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_dma.c

@@ -0,0 +1,555 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_dma.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the DMA firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32f10x_dma.h"
+#include "ch32f10x_rcc.h"
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CFGR_CLEAR_Mask          ((uint32_t)0xFFFF800F)
+
+
+/*********************************************************************
+ * @fn      DMA_DeInit
+ *
+ * @brief   Deinitializes the DMAy Channelx registers to their default
+ *        reset values.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_DeInit( DMA_Channel_TypeDef *DMAy_Channelx )
+{
+    DMAy_Channelx->CFGR &= ( uint16_t )( ~DMA_CFGR1_EN );
+    DMAy_Channelx->CFGR  = 0;
+    DMAy_Channelx->CNTR = 0;
+    DMAy_Channelx->PADDR  = 0;
+    DMAy_Channelx->MADDR = 0;
+    if( DMAy_Channelx == DMA1_Channel1 )
+    {
+        DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA1_Channel2 )
+    {
+        DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA1_Channel3 )
+    {
+        DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA1_Channel4 )
+    {
+        DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA1_Channel5 )
+    {
+        DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA1_Channel6 )
+    {
+        DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA1_Channel7 )
+    {
+        DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA2_Channel1 )
+    {
+        DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA2_Channel2 )
+    {
+        DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA2_Channel3 )
+    {
+        DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
+    }
+    else if( DMAy_Channelx == DMA2_Channel4 )
+    {
+        DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
+    }
+    else
+    {
+        if( DMAy_Channelx == DMA2_Channel5 )
+        {
+            DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
+        }
+    }
+}
+
+
+/*********************************************************************
+ * @fn      DMA_Init
+ *
+ * @brief   Initializes the DMAy Channelx according to the specified
+ *        parameters in the DMA_InitStruct.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_Init( DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = DMAy_Channelx->CFGR;
+    tmpreg &= CFGR_CLEAR_Mask;
+    tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+              DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+              DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+              DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+    DMAy_Channelx->CFGR = tmpreg;
+    DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
+    DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+    DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/*********************************************************************
+ * @fn      DMA_StructInit
+ *
+ * @brief   Fills each DMA_InitStruct member with its default value.
+ *
+ * @param   DMA_InitStruct - pointer to a DMA_InitTypeDef structure which will
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the be initialized.
+ *
+ * @return  none
+ */
+void DMA_StructInit( DMA_InitTypeDef *DMA_InitStruct )
+{
+    DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+    DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+    DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+    DMA_InitStruct->DMA_BufferSize = 0;
+    DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+    DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+    DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+    DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+
+/*********************************************************************
+ * @fn      DMA_Cmd
+ *
+ * @brief   Enables or disables the specified DMAy Channelx.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_Cmd( DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= ( uint16_t )( ~DMA_CFGR1_EN );
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_ITConfig
+ *
+ * @brief   Enables or disables the specified DMAy Channelx interrupts.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          DMA_IT - specifies the DMA interrupts sources to be enabled
+ *        or disabled.
+ *           DMA_IT_TC - Transfer complete interrupt mask
+ *           DMA_IT_HT - Half transfer interrupt mask
+ *           DMA_IT_TE -  Transfer error interrupt mask
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_ITConfig( DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        DMAy_Channelx->CFGR |= DMA_IT;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= ~DMA_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_SetCurrDataCounter
+ *
+ * @brief   Sets the number of data units in the current DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          DataNumber - The number of data units in the current DMAy Channelx
+ *        transfer.
+ *
+ * @return  none
+ */
+void DMA_SetCurrDataCounter( DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber )
+{
+    DMAy_Channelx->CNTR = DataNumber;
+}
+
+/*********************************************************************
+ * @fn      DMA_GetCurrDataCounter
+ *
+ * @brief   Returns the number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *
+ * @return  DataNumber - The number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ */
+uint16_t DMA_GetCurrDataCounter( DMA_Channel_TypeDef *DMAy_Channelx )
+{
+    return ( ( uint16_t )( DMAy_Channelx->CNTR ) );
+}
+
+
+/*********************************************************************
+ * @fn      DMA_GetFlagStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx flag is set or not.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus( uint32_t DMAy_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+
+    if( ( DMAy_FLAG & FLAG_Mask ) != ( uint32_t )RESET )
+    {
+        tmpreg = DMA2->INTFR ;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR ;
+    }
+
+    if( ( tmpreg & DMAy_FLAG ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return  bitstatus;
+}
+
+
+/*********************************************************************
+ * @fn      DMA_ClearFlag
+ *
+ * @brief   Clears the DMAy Channelx's pending flags.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearFlag( uint32_t DMAy_FLAG )
+{
+    if( ( DMAy_FLAG & FLAG_Mask ) != ( uint32_t )RESET )
+    {
+        DMA2->INTFCR = DMAy_FLAG;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_FLAG;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_GetITStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx interrupt has
+ *        occurred or not.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus( uint32_t DMAy_IT )
+{
+    ITStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+
+    if( ( DMAy_IT & FLAG_Mask ) != ( uint32_t )RESET )
+    {
+        tmpreg = DMA2->INTFR;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR;
+    }
+
+    if( ( tmpreg & DMAy_IT ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return  bitstatus;
+}
+
+
+/*********************************************************************
+ * @fn      DMA_ClearITPendingBit
+ *
+ * @brief   Clears the DMAy Channelx's interrupt pending bits.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearITPendingBit( uint32_t DMAy_IT )
+{
+    if( ( DMAy_IT & FLAG_Mask ) != ( uint32_t )RESET )
+    {
+        DMA2->INTFCR = DMAy_IT;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_IT;
+    }
+}
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_exti.c

@@ -0,0 +1,182 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_exti.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the EXTI firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ***************************************************************************************/
+#include "ch32f10x_exti.h"
+
+/* No interrupt selected */
+#define EXTI_LINENONE    ((uint32_t)0x00000)
+
+
+/*********************************************************************
+ * @fn      EXTI_DeInit
+ *
+ * @brief   Deinitializes the EXTI peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none.
+ */
+void EXTI_DeInit( void )
+{
+    EXTI->INTENR = 0x00000000;
+    EXTI->EVENR = 0x00000000;
+    EXTI->RTENR = 0x00000000;
+    EXTI->FTENR = 0x00000000;
+    EXTI->INTFR = 0x000FFFFF;
+}
+
+/*********************************************************************
+ * @fn      EXTI_Init
+ *
+ * @brief   Initializes the EXTI peripheral according to the specified
+ *        parameters in the EXTI_InitStruct.
+ *
+ * @param   EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_Init( EXTI_InitTypeDef *EXTI_InitStruct )
+{
+    uint32_t tmp = 0;
+
+    tmp = ( uint32_t )EXTI_BASE;
+    if( EXTI_InitStruct->EXTI_LineCmd != DISABLE )
+    {
+        EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *( __IO uint32_t * ) tmp |= EXTI_InitStruct->EXTI_Line;
+        EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
+        if( EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling )
+        {
+            EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
+            EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
+        }
+        else
+        {
+            tmp = ( uint32_t )EXTI_BASE;
+            tmp += EXTI_InitStruct->EXTI_Trigger;
+            *( __IO uint32_t * ) tmp |= EXTI_InitStruct->EXTI_Line;
+        }
+    }
+    else
+    {
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *( __IO uint32_t * ) tmp &= ~EXTI_InitStruct->EXTI_Line;
+    }
+}
+
+/*********************************************************************
+ * @fn      EXTI_StructInit
+ *
+ * @brief   Fills each EXTI_InitStruct member with its reset value.
+ *
+ * @param   EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_StructInit( EXTI_InitTypeDef *EXTI_InitStruct )
+{
+    EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+    EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GenerateSWInterrupt
+ *
+ * @brief   Generates a Software interrupt.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none.
+ */
+void EXTI_GenerateSWInterrupt( uint32_t EXTI_Line )
+{
+    EXTI->SWIEVR |= EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetFlagStatus
+ *
+ * @brief   Checks whether the specified EXTI line flag is set or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus( uint32_t EXTI_Line )
+{
+    FlagStatus bitstatus = RESET;
+    if( ( EXTI->INTFR & EXTI_Line ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearFlag
+ *
+ * @brief   Clears the EXTI's line pending flags.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  None
+ */
+void EXTI_ClearFlag( uint32_t EXTI_Line )
+{
+    EXTI->INTFR = EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetITStatus
+ *
+ * @brief   Checks whether the specified EXTI line is asserted or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus( uint32_t EXTI_Line )
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus =  EXTI->INTENR & EXTI_Line;
+    if( ( ( EXTI->INTFR & EXTI_Line ) != ( uint32_t )RESET ) && ( enablestatus != ( uint32_t )RESET ) )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearITPendingBit
+ *
+ * @brief   Clears the EXTI's line pending bits.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none
+ */
+void EXTI_ClearITPendingBit( uint32_t EXTI_Line )
+{
+    EXTI->INTFR = EXTI_Line;
+}
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_flash.c

@@ -0,0 +1,979 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_flash.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the FLASH firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ***************************************************************************************/
+#include "ch32f10x_flash.h"
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask         ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask          ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask          ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask          ((uint32_t)0x00000020)
+
+/* Flash Control Register bits */
+#define CR_PG_Set                ((uint32_t)0x00000001)
+#define CR_PG_Reset              ((uint32_t)0x00001FFE)
+#define CR_PER_Set               ((uint32_t)0x00000002)
+#define CR_PER_Reset             ((uint32_t)0x00001FFD)
+#define CR_MER_Set               ((uint32_t)0x00000004)
+#define CR_MER_Reset             ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set             ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset           ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set             ((uint32_t)0x00000020)
+#define CR_OPTER_Reset           ((uint32_t)0x00001FDF)
+#define CR_STRT_Set              ((uint32_t)0x00000040)
+#define CR_LOCK_Set              ((uint32_t)0x00000080)
+#define CR_PAGE_PG 	             ((uint32_t)0x00010000)
+#define CR_PAGE_ER				       ((uint32_t)0x00020000)
+#define CR_BUF_LOAD 	           ((uint32_t)0x00040000)
+#define CR_BUF_RST 					     ((uint32_t)0x00080000)
+
+/* FLASH Status Register bits */
+#define SR_BSY 					         ((uint32_t)0x00000001)
+#define SR_PGERR 					       ((uint32_t)0x00000004)
+#define SR_WRPRTERR 					   ((uint32_t)0x00000010)
+#define SR_EOP 					         ((uint32_t)0x00000020)
+
+/* FLASH Mask */
+#define RDPRT_Mask               ((uint32_t)0x00000002)
+#define WRP0_Mask                ((uint32_t)0x000000FF)
+#define WRP1_Mask                ((uint32_t)0x0000FF00)
+#define WRP2_Mask                ((uint32_t)0x00FF0000)
+#define WRP3_Mask                ((uint32_t)0xFF000000)
+#define OB_USER_BFB2             ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS  ((uint32_t)0x807FFFF)
+
+/* Delay definition */
+#define EraseTimeout             ((uint32_t)0x000B0000)
+#define ProgramTimeout           ((uint32_t)0x00002000)
+
+/* Flash Program Vaild Address */
+#define ValidAddrStart           (FLASH_BASE)
+#define ValidAddrEnd             (FLASH_BASE + 0x10000)
+
+
+/********************************************************************************
+  * @fn            FLASH_SetLatency
+  *
+  * @brief         Sets the code latency value.
+  *
+  * @param         FLASH_Latency - specifies the FLASH Latency value.
+  *                    FLASH_Latency_0 - FLASH Zero Latency cycle
+  *                    FLASH_Latency_1 - FLASH One Latency cycle
+  *                    FLASH_Latency_2 - FLASH Two Latency cycles
+  *
+  * @return         None
+  */
+void FLASH_SetLatency( uint32_t FLASH_Latency )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = FLASH->ACTLR;
+    tmpreg &= ACR_LATENCY_Mask;
+    tmpreg |= FLASH_Latency;
+    FLASH->ACTLR = tmpreg;
+}
+
+
+/********************************************************************************
+ * @fn            FLASH_HalfCycleAccessCmd
+ *
+ * @brief          Enables or disables the Half cycle flash access.
+ *
+ * @param          FLASH_HalfCycleAccess - specifies the FLASH Half cycle Access mode.
+ *                   FLASH_HalfCycleAccess_Enable - FLASH Half Cycle Enable
+ *                   FLASH_HalfCycleAccess_Disable - FLASH Half Cycle Disable
+ *
+ * @return         None
+ */
+void FLASH_HalfCycleAccessCmd( uint32_t FLASH_HalfCycleAccess )
+{
+    FLASH->ACTLR &= ACR_HLFCYA_Mask;
+    FLASH->ACTLR |= FLASH_HalfCycleAccess;
+}
+
+/********************************************************************************
+ * @fn             FLASH_PrefetchBufferCmd
+ *
+ * @brief          Enables or disables the Prefetch Buffer.
+ *
+ * @param          FLASH_PrefetchBuffer - specifies the Prefetch buffer status.
+ *                   FLASH_PrefetchBuffer_Enable - FLASH Prefetch Buffer Enable
+ *                   FLASH_PrefetchBuffer_Disable - FLASH Prefetch Buffer Disable
+ *
+ * @return         None
+ */
+void FLASH_PrefetchBufferCmd( uint32_t FLASH_PrefetchBuffer )
+{
+    FLASH->ACTLR &= ACR_PRFTBE_Mask;
+    FLASH->ACTLR |= FLASH_PrefetchBuffer;
+}
+
+
+/********************************************************************************
+ * @fn             FLASH_Unlock
+ *
+ * @brief          Unlocks the FLASH Program Erase Controller.
+ *
+ * @return         None
+ */
+void FLASH_Unlock( void )
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+
+/********************************************************************************
+ * @fn             FLASH_UnlockBank1
+ *
+ * @brief          Unlocks the FLASH Bank1 Program Erase Controller.
+ *                 equivalent to FLASH_Unlock function.
+ *
+ * @return         None
+ */
+void FLASH_UnlockBank1( void )
+{
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/********************************************************************************
+ * @fn             FLASH_Lock
+ *
+ * @brief          Locks the FLASH Program Erase Controller.
+ *
+ * @return         None
+ */
+void FLASH_Lock( void )
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/********************************************************************************
+ * @fn             FLASH_LockBank1
+ *
+ * @brief          Locks the FLASH Bank1 Program Erase Controller.
+ *
+ * @return         None
+ */
+void FLASH_LockBank1( void )
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+
+/********************************************************************************
+ * @fn             FLASH_ErasePage
+ *
+ * @brief          Erases a specified FLASH page.
+ *
+ * @param          Page_Address - The page address to be erased.
+ *
+ * @return         FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage( uint32_t Page_Address )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation( EraseTimeout );
+
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->CTLR |= CR_PER_Set;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation( EraseTimeout );
+
+        FLASH->CTLR &= CR_PER_Reset;
+    }
+
+    *( __IO uint32_t * )0x40022034 = *( __IO uint32_t * )( Page_Address ^ 0x00000100 );
+
+    return status;
+}
+
+
+/********************************************************************************
+ * @fn             FLASH_EraseAllPages
+ *
+ * @brief          Erases all FLASH pages.
+ *
+ * @return         FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages( void )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation( EraseTimeout );
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation( EraseTimeout );
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+
+    return status;
+}
+
+/********************************************************************************
+ * @fn             FLASH_EraseAllBank1Pages
+ *
+ * @brief          Erases all Bank1 FLASH pages.
+ *
+ * @return         FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank1Pages( void )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastBank1Operation( EraseTimeout );
+
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastBank1Operation( EraseTimeout );
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+    return status;
+}
+
+/********************************************************************************
+ * @fn             FLASH_EraseOptionBytes
+ *
+ * @brief          Erases the FLASH option bytes.
+ *
+ * @return         FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes( void )
+{
+    uint16_t rdptmp = RDP_Key;
+
+    FLASH_Status status = FLASH_COMPLETE;
+    if( FLASH_GetReadOutProtectionStatus() != RESET )
+    {
+        rdptmp = 0x00;
+    }
+    status = FLASH_WaitForLastOperation( EraseTimeout );
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        status = FLASH_WaitForLastOperation( EraseTimeout );
+
+        if( status == FLASH_COMPLETE )
+        {
+            FLASH->CTLR &= CR_OPTER_Reset;
+            FLASH->CTLR |= CR_OPTPG_Set;
+            OB->RDPR = ( uint16_t )rdptmp;
+            status = FLASH_WaitForLastOperation( ProgramTimeout );
+
+            if( status != FLASH_TIMEOUT )
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if( status != FLASH_TIMEOUT )
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn         FLASH_ProgramWord
+ *
+ * @brief       Programs a word at a specified address.
+ *
+ * @param       Address - specifies the address to be programmed.
+ *              Data - specifies the data to be programmed.
+ *
+ * @return       FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *              FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord( uint32_t Address, uint32_t Data )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    __IO uint32_t tmp = 0;
+
+    status = FLASH_WaitForLastOperation( ProgramTimeout );
+
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->CTLR |= CR_PG_Set;
+
+        *( __IO uint16_t * )Address = ( uint16_t )Data;
+        status = FLASH_WaitForLastOperation( ProgramTimeout );
+
+        if( status == FLASH_COMPLETE )
+        {
+            tmp = Address + 2;
+            *( __IO uint16_t * ) tmp = Data >> 16;
+            status = FLASH_WaitForLastOperation( ProgramTimeout );
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+        else
+        {
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+    }
+
+    *( __IO uint32_t * )0x40022034 = *( __IO uint32_t * )( Address ^ 0x00000100 );
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn         FLASH_ProgramHalfWord
+ *
+ * @brief       Programs a half word at a specified address.
+ *
+ * @param       Address - specifies the address to be programmed.
+ *              Data - specifies the data to be programmed.
+ *
+ * @return      FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *             FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord( uint32_t Address, uint16_t Data )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation( ProgramTimeout );
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->CTLR |= CR_PG_Set;
+        *( __IO uint16_t * )Address = Data;
+        status = FLASH_WaitForLastOperation( ProgramTimeout );
+        FLASH->CTLR &= CR_PG_Reset;
+    }
+
+    //*( __IO uint32_t * )0x40022034 = *( __IO uint32_t * )( Address ^ 0x00000100 );
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn        FLASH_ProgramOptionByteData
+ *
+ * @brief     Programs a half word at a specified Option Byte Data address.
+ *
+ * @param     Address - specifies the address to be programmed.
+ *            Data - specifies the data to be programmed.
+ *
+ * @return    FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *           FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData( uint32_t Address, uint8_t Data )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastOperation( ProgramTimeout );
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+        FLASH->CTLR |= CR_OPTPG_Set;
+        *( __IO uint16_t * )Address = Data;
+        status = FLASH_WaitForLastOperation( ProgramTimeout );
+        if( status != FLASH_TIMEOUT )
+        {
+            FLASH->CTLR &= CR_OPTPG_Reset;
+        }
+    }
+
+    *( __IO uint32_t * )0x40022034 = *( __IO uint32_t * )( Address ^ 0x00000100 );
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EnableWriteProtection
+ *
+ * @brief   Write protects the desired sectors
+ *
+ * @param   FLASH_Sectors - specifies the address of the pages to be write protected.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection( uint32_t FLASH_Pages )
+{
+    uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+    FLASH_Status status = FLASH_COMPLETE;
+
+    FLASH_Pages = ( uint32_t )( ~FLASH_Pages );
+    WRP0_Data = ( uint16_t )( FLASH_Pages & WRP0_Mask );
+    WRP1_Data = ( uint16_t )( ( FLASH_Pages & WRP1_Mask ) >> 8 );
+    WRP2_Data = ( uint16_t )( ( FLASH_Pages & WRP2_Mask ) >> 16 );
+    WRP3_Data = ( uint16_t )( ( FLASH_Pages & WRP3_Mask ) >> 24 );
+
+    status = FLASH_WaitForLastOperation( ProgramTimeout );
+
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+        FLASH->CTLR |= CR_OPTPG_Set;
+        if( WRP0_Data != 0xFF )
+        {
+            OB->WRPR0 = WRP0_Data;
+            status = FLASH_WaitForLastOperation( ProgramTimeout );
+        }
+        if( ( status == FLASH_COMPLETE ) && ( WRP1_Data != 0xFF ) )
+        {
+            OB->WRPR1 = WRP1_Data;
+            status = FLASH_WaitForLastOperation( ProgramTimeout );
+        }
+        if( ( status == FLASH_COMPLETE ) && ( WRP2_Data != 0xFF ) )
+        {
+            OB->WRPR2 = WRP2_Data;
+            status = FLASH_WaitForLastOperation( ProgramTimeout );
+        }
+
+        if( ( status == FLASH_COMPLETE ) && ( WRP3_Data != 0xFF ) )
+        {
+            OB->WRPR3 = WRP3_Data;
+            status = FLASH_WaitForLastOperation( ProgramTimeout );
+        }
+
+        if( status != FLASH_TIMEOUT )
+        {
+            FLASH->CTLR &= CR_OPTPG_Reset;
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ReadOutProtection
+ *
+ * @brief   Enables or disables the read out protection.
+ *
+ * @param   Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection( FunctionalState NewState )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastOperation( EraseTimeout );
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        status = FLASH_WaitForLastOperation( EraseTimeout );
+        if( status == FLASH_COMPLETE )
+        {
+            FLASH->CTLR &= CR_OPTER_Reset;
+            FLASH->CTLR |= CR_OPTPG_Set;
+            if( NewState != DISABLE )
+            {
+                OB->RDPR = 0x00;
+            }
+            else
+            {
+                OB->RDPR = RDP_Key;
+            }
+            status = FLASH_WaitForLastOperation( EraseTimeout );
+
+            if( status != FLASH_TIMEOUT )
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if( status != FLASH_TIMEOUT )
+            {
+                FLASH->CTLR &= CR_OPTER_Reset;
+            }
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UserOptionByteConfig
+ *
+ * @brief   Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY.
+ *
+ * @param   OB_IWDG - Selects the IWDG mode
+ *            OB_IWDG_SW - Software IWDG selected
+ *            OB_IWDG_HW - Hardware IWDG selected
+ *          OB_STOP - Reset event when entering STOP mode.
+ *            OB_STOP_NoRST - No reset generated when entering in STOP
+ *            OB_STOP_RST - Reset generated when entering in STOP
+ *          OB_STDBY - Reset event when entering Standby mode.
+ *            OB_STDBY_NoRST - No reset generated when entering in STANDBY
+ *            OB_STDBY_RST - Reset generated when entering in STANDBY
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig( uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    FLASH->OBKEYR = FLASH_KEY1;
+    FLASH->OBKEYR = FLASH_KEY2;
+    status = FLASH_WaitForLastOperation( ProgramTimeout );
+
+    if( status == FLASH_COMPLETE )
+    {
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        OB->USER = OB_IWDG | ( uint16_t )( OB_STOP | ( uint16_t )( OB_STDBY | ( ( uint16_t )0xF8 ) ) );
+
+        status = FLASH_WaitForLastOperation( ProgramTimeout );
+        if( status != FLASH_TIMEOUT )
+        {
+            FLASH->CTLR &= CR_OPTPG_Reset;
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetUserOptionByte
+ *
+ * @brief   Returns the FLASH User Option Bytes values.
+ *
+ * @return  The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ *        and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte( void )
+{
+    return ( uint32_t )( FLASH->OBR >> 2 );
+}
+
+
+/*********************************************************************
+ * @fn      FLASH_GetWriteProtectionOptionByte
+ *
+ * @brief   Returns the FLASH Write Protection Option Bytes Register value.
+ *
+ * @return  The FLASH Write Protection Option Bytes Register value.
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte( void )
+{
+    return ( uint32_t )( FLASH->WPR );
+}
+
+
+/*********************************************************************
+ * @fn      FLASH_GetReadOutProtectionStatus
+ *
+ * @brief   Checks whether the FLASH Read Out Protection Status is set or not.
+ *
+ * @return  FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus( void )
+{
+    FlagStatus readoutstatus = RESET;
+    if( ( FLASH->OBR & RDPRT_Mask ) != ( uint32_t )RESET )
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetPrefetchBufferStatus
+ *
+ * @brief   Checks whether the FLASH Prefetch Buffer status is set or not.
+ *
+ * @return  FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetPrefetchBufferStatus( void )
+{
+    FlagStatus bitstatus = RESET;
+
+    if( ( FLASH->ACTLR & ACR_PRFTBS_Mask ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ITConfig
+ *
+ * @brief   Enables or disables the specified FLASH interrupts.
+ *
+ * @param   FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled.
+ *            FLASH_IT_ERROR - FLASH Error Interrupt
+ *            FLASH_IT_EOP - FLASH end of operation Interrupt
+ *          NewState - new state of the specified Flash interrupts(ENABLE or DISABLE).
+ *
+ * @return  FLASH Prefetch Buffer Status (SET or RESET).
+ */
+void FLASH_ITConfig( uint32_t FLASH_IT, FunctionalState NewState )
+{
+
+    if( NewState != DISABLE )
+    {
+        FLASH->CTLR |= FLASH_IT;
+    }
+    else
+    {
+        FLASH->CTLR &= ~( uint32_t )FLASH_IT;
+    }
+
+}
+
+
+/*********************************************************************
+ * @fn      FLASH_GetFlagStatus
+ *
+ * @brief   Checks whether the specified FLASH flag is set or not.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flag to check.
+ *            FLASH_FLAG_BSY - FLASH Busy flag
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *            FLASH_FLAG_OPTERR - FLASH Option Byte error flag
+ *
+ * @return  The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus( uint32_t FLASH_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+
+    if( FLASH_FLAG == FLASH_FLAG_OPTERR )
+    {
+        if( ( FLASH->OBR & FLASH_FLAG_OPTERR ) != ( uint32_t )RESET )
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if( ( FLASH->STATR & FLASH_FLAG ) != ( uint32_t )RESET )
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ClearFlag
+ *
+ * @brief   Clears the FLASH's pending flags.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flags to clear.
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *
+ * @return  none
+ */
+void FLASH_ClearFlag( uint32_t FLASH_FLAG )
+{
+
+    FLASH->STATR = FLASH_FLAG;
+
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetStatus
+ *
+ * @brief   Returns the FLASH Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetStatus( void )
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if( ( FLASH->STATR & FLASH_FLAG_BSY ) == FLASH_FLAG_BSY )
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if( ( FLASH->STATR & FLASH_FLAG_PGERR ) != 0 )
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if( ( FLASH->STATR & FLASH_FLAG_WRPRTERR ) != 0 )
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetBank1Status
+ *
+ * @brief   Returns the FLASH Bank1 Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetBank1Status( void )
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if( ( FLASH->STATR & FLASH_FLAG_BANK1_BSY ) == FLASH_FLAG_BSY )
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if( ( FLASH->STATR & FLASH_FLAG_BANK1_PGERR ) != 0 )
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if( ( FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR ) != 0 )
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastOperation
+ *
+ * @brief   Waits for a Flash operation to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastOperation( uint32_t Timeout )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while( ( status == FLASH_BUSY ) && ( Timeout != 0x00 ) )
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if( Timeout == 0x00 )
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastBank1Operation
+ *
+ * @brief   Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastBank1Operation( uint32_t Timeout )
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while( ( status == FLASH_FLAG_BANK1_BSY ) && ( Timeout != 0x00 ) )
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if( Timeout == 0x00 )
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Unlock_Fast
+ *
+ * @brief   Unlocks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Unlock_Fast( void )
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+
+    /* Fast program mode unlock */
+    FLASH->MODEKEYR = FLASH_KEY1;
+    FLASH->MODEKEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Lock_Fast
+ *
+ * @brief   Locks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Lock_Fast( void )
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Unlock_Fast
+ *
+ * @brief   Unlocks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_BufReset( void )
+{
+    FLASH->CTLR |= CR_PAGE_PG;
+    FLASH->CTLR |= CR_BUF_RST;
+    while( FLASH->STATR & SR_BSY );
+    FLASH->CTLR &= ~CR_PAGE_PG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_BufLoad
+ *
+ * @brief   Flash Buffer load(128 bit).
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data0 - specifies the data0 to be programmed.
+ *          Data1 - specifies the data1 to be programmed.
+ *          Data2 - specifies the data2 to be programmed.
+ *          Data3 - specifies the data3 to be programmed.
+ *
+ * @return  none
+ */
+void FLASH_BufLoad( uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3 )
+{
+    if( ( Address >= ValidAddrStart ) && ( Address < ValidAddrEnd ) )
+    {
+        FLASH->CTLR |= CR_PAGE_PG;
+        *( __IO uint32_t * )( Address + 0x00 ) = Data0;
+        *( __IO uint32_t * )( Address + 0x04 ) = Data1;
+        *( __IO uint32_t * )( Address + 0x08 ) = Data2;
+        *( __IO uint32_t * )( Address + 0x0C ) = Data3;
+        FLASH->CTLR |= CR_BUF_LOAD;
+        while( FLASH->STATR & SR_BSY );
+        FLASH->CTLR &= ~CR_PAGE_PG;
+
+        *( __IO uint32_t * )0x40022034 = *( __IO uint32_t * )( Address ^ 0x00000100 );
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage_Fast
+ *
+ * @brief   Erases a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_ErasePage_Fast( uint32_t Page_Address )
+{
+    if( ( Page_Address >= ValidAddrStart ) && ( Page_Address < ValidAddrEnd ) )
+    {
+        FLASH->CTLR |= CR_PAGE_ER;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+        while( FLASH->STATR & SR_BSY );
+        FLASH->CTLR &= ~CR_PAGE_ER;
+
+        *( __IO uint32_t * )0x40022034 = *( __IO uint32_t * )( Page_Address ^ 0x00000100 );
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramPage_Fast
+ *
+ * @brief   Program a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be programed.
+ *
+ * @return  none
+ */
+void FLASH_ProgramPage_Fast( uint32_t Page_Address )
+{
+    if( ( Page_Address >= ValidAddrStart ) && ( Page_Address < ValidAddrEnd ) )
+    {
+        FLASH->CTLR |= CR_PAGE_PG;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+        while( FLASH->STATR & SR_BSY );
+        FLASH->CTLR &= ~CR_PAGE_PG;
+
+        *( __IO uint32_t * )0x40022034 = *( __IO uint32_t * )( Page_Address ^ 0x00000100 );
+    }
+}

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_gpio.c

@@ -0,0 +1,534 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_gpio.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the GPIO firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_gpio.h"
+#include "ch32f10x_rcc.h"
+
+
+/* RCC registers bit address in the alias region */
+#define AFIO_OFFSET                  (AFIO_BASE - PERIPH_BASE)
+
+/* ECR Register */
+/* Alias word address of EVOE bit */
+#define ECR_OFFSET                   (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber               ((uint8_t)0x07)
+#define ECR_EVOE_BB                  (PERIPH_BB_BASE + (ECR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* PCFR1 Register */
+/* Alias word address of MII_RMII_SEL bit */
+#define PCFR1_OFFSET                 (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber       ((u8)0x17)
+#define PCFR1_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (PCFR1_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+#define ECR_PORTPINCONFIG_MASK      ((uint16_t)0xFF80)
+#define LSB_MASK                    ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
+
+
+/*********************************************************************
+ * @fn      GPIO_DeInit
+ *
+ * @brief   Deinitializes the GPIOx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_DeInit( GPIO_TypeDef *GPIOx )
+{
+    if( GPIOx == GPIOA )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOA, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOA, DISABLE );
+    }
+    else if( GPIOx == GPIOB )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOB, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOB, DISABLE );
+    }
+    else if( GPIOx == GPIOC )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOC, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOC, DISABLE );
+    }
+    else if( GPIOx == GPIOD )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOD, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOD, DISABLE );
+    }
+    else if( GPIOx == GPIOE )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOE, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOE, DISABLE );
+    }
+    else if( GPIOx == GPIOF )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOF, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOF, DISABLE );
+    }
+    else
+    {
+        if( GPIOx == GPIOG )
+        {
+            RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOG, ENABLE );
+            RCC_APB2PeriphResetCmd( RCC_APB2Periph_GPIOG, DISABLE );
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_AFIODeInit
+ *
+ * @brief   Deinitializes the Alternate Functions (remap, event control
+ *        and EXTI configuration) registers to their default reset values.
+ *
+ * @return  none
+ */
+void GPIO_AFIODeInit( void )
+{
+    RCC_APB2PeriphResetCmd( RCC_APB2Periph_AFIO, ENABLE );
+    RCC_APB2PeriphResetCmd( RCC_APB2Periph_AFIO, DISABLE );
+}
+
+/*********************************************************************
+ * @fn      GPIO_Init
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
+ *        contains the configuration information for the specified GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_Init( GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct )
+{
+    uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+    uint32_t tmpreg = 0x00, pinmask = 0x00;
+
+    currentmode = ( ( uint32_t )GPIO_InitStruct->GPIO_Mode ) & ( ( uint32_t )0x0F );
+
+    if( ( ( ( uint32_t )GPIO_InitStruct->GPIO_Mode ) & ( ( uint32_t )0x10 ) ) != 0x00 )
+    {
+        currentmode |= ( uint32_t )GPIO_InitStruct->GPIO_Speed;
+    }
+
+    if( ( ( uint32_t )GPIO_InitStruct->GPIO_Pin & ( ( uint32_t )0x00FF ) ) != 0x00 )
+    {
+        tmpreg = GPIOx->CFGLR;
+
+        for( pinpos = 0x00; pinpos < 0x08; pinpos++ )
+        {
+            pos = ( ( uint32_t )0x01 ) << pinpos;
+            currentpin = ( GPIO_InitStruct->GPIO_Pin ) & pos;
+
+            if( currentpin == pos )
+            {
+                pos = pinpos << 2;
+                pinmask = ( ( uint32_t )0x0F ) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= ( currentmode << pos );
+
+                if( GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD )
+                {
+                    GPIOx->BCR = ( ( ( uint32_t )0x01 ) << pinpos );
+                }
+                else
+                {
+                    if( GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU )
+                    {
+                        GPIOx->BSHR = ( ( ( uint32_t )0x01 ) << pinpos );
+                    }
+                }
+            }
+        }
+        GPIOx->CFGLR = tmpreg;
+    }
+
+    if( GPIO_InitStruct->GPIO_Pin > 0x00FF )
+    {
+        tmpreg = GPIOx->CFGHR;
+
+        for( pinpos = 0x00; pinpos < 0x08; pinpos++ )
+        {
+            pos = ( ( ( uint32_t )0x01 ) << ( pinpos + 0x08 ) );
+            currentpin = ( ( GPIO_InitStruct->GPIO_Pin ) & pos );
+
+            if( currentpin == pos )
+            {
+                pos = pinpos << 2;
+                pinmask = ( ( uint32_t )0x0F ) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= ( currentmode << pos );
+
+                if( GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD )
+                {
+                    GPIOx->BCR = ( ( ( uint32_t )0x01 ) << ( pinpos + 0x08 ) );
+                }
+
+                if( GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU )
+                {
+                    GPIOx->BSHR = ( ( ( uint32_t )0x01 ) << ( pinpos + 0x08 ) );
+                }
+            }
+        }
+        GPIOx->CFGHR = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_StructInit
+ *
+ * @brief   Fills each GPIO_InitStruct member with its default
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
+ *      which will be initialized.
+ *
+ * @return  none
+ */
+void GPIO_StructInit( GPIO_InitTypeDef *GPIO_InitStruct )
+{
+    GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputDataBit
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param    GPIO_Pin - specifies the port bit to read.
+ *             This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit( GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin )
+{
+    uint8_t bitstatus = 0x00;
+
+    if( ( GPIOx->INDR & GPIO_Pin ) != ( uint32_t )Bit_RESET )
+    {
+        bitstatus = ( uint8_t )Bit_SET;
+    }
+    else
+    {
+        bitstatus = ( uint8_t )Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputData
+ *
+ * @brief   Reads the specified GPIO input data port.
+ *
+ * @param   GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  The input port pin value.
+ */
+uint16_t GPIO_ReadInputData( GPIO_TypeDef *GPIOx )
+{
+    return ( ( uint16_t )GPIOx->INDR );
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputDataBit
+ *
+ * @brief   Reads the specified output data port bit.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to read.
+ *            This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+uint8_t GPIO_ReadOutputDataBit( GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin )
+{
+    uint8_t bitstatus = 0x00;
+
+    if( ( GPIOx->OUTDR & GPIO_Pin ) != ( uint32_t )Bit_RESET )
+    {
+        bitstatus = ( uint8_t )Bit_SET;
+    }
+    else
+    {
+        bitstatus = ( uint8_t )Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputData
+ *
+ * @brief   Reads the specified GPIO output data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  GPIO output port pin value.
+ */
+uint16_t GPIO_ReadOutputData( GPIO_TypeDef *GPIOx )
+{
+    return ( ( uint16_t )GPIOx->OUTDR );
+}
+
+/*********************************************************************
+ * @fn      GPIO_SetBits
+ *
+ * @brief   Sets the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_SetBits( GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin )
+{
+    GPIOx->BSHR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ResetBits
+ *
+ * @brief   Clears the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_ResetBits( GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin )
+{
+    GPIOx->BCR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_WriteBit
+ *
+ * @brief   Sets or clears the selected data port bit.
+ *
+ * @param   GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ *          BitVal - specifies the value to be written to the selected bit.
+ *            Bit_SetL - to clear the port pin.
+ *            Bit_SetH - to set the port pin.
+ *
+ * @return  none
+ */
+void GPIO_WriteBit( GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal )
+{
+    if( BitVal != Bit_RESET )
+    {
+        GPIOx->BSHR = GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->BCR = GPIO_Pin;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_Write
+ *
+ * @brief   Writes data to the specified GPIO data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          PortVal - specifies the value to be written to the port output data register.
+ *
+ * @return  none
+ */
+void GPIO_Write( GPIO_TypeDef *GPIOx, uint16_t PortVal )
+{
+    GPIOx->OUTDR = PortVal;
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinLockConfig
+ *
+ * @brief   Locks GPIO Pins configuration registers.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_PinLockConfig( GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin )
+{
+    uint32_t tmp = 0x00010000;
+
+    tmp |= GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    GPIOx->LCKR =  GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    tmp = GPIOx->LCKR;
+    tmp = GPIOx->LCKR;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputConfig
+ *
+ * @brief   Selects the GPIO pin used as Event output.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source
+ *        for Event output.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ *          GPIO_PinSource - specifies the pin for the Event output.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EventOutputConfig( uint8_t GPIO_PortSource, uint8_t GPIO_PinSource )
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = AFIO->ECR;
+    tmpreg &= ECR_PORTPINCONFIG_MASK;
+    tmpreg |= ( uint32_t )GPIO_PortSource << 0x04;
+    tmpreg |= GPIO_PinSource;
+    AFIO->ECR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputCmd
+ *
+ * @brief   Enables or disables the Event Output.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_EventOutputCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) ECR_EVOE_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinRemapConfig
+ *
+ * @brief   Changes the mapping of the specified pin.
+ *
+ * @param   GPIO_Remap - selects the pin to remap.
+ *            GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
+ *            GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
+ *            GPIO_Remap_USART1 - USART1 Alternate Function mapping
+ *            GPIO_Remap_USART2 - USART2 Alternate Function mapping
+ *            GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
+ *            GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
+ *            GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
+ *            GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
+ *            GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
+ *            GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap_PD01 - PD01 Alternate Function mapping
+ *            GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ *            GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled
+ *            GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP)
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ *      connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices).If the
+ *      is enabled the TIM2 ITR1 is connected to Ethernet PTP output. When Reset TIM2 ITR1 is connected
+ *      to USB OTG SOF output.
+ *            GPIO_Remap_TIM1_DMA: TIM1 DMA requests mapping (only for Value line devices)
+ *            GPIO_Remap_TIM67_DAC_DMA: TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
+ *            GPIO_Remap_MISC: Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
+ *      only for High density Value line devices)
+ *             NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_PinRemapConfig( uint32_t GPIO_Remap, FunctionalState NewState )
+{
+    uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+    if( ( GPIO_Remap & 0x80000000 ) == 0x80000000 )
+    {
+        tmpreg = AFIO->PCFR2;
+    }
+    else
+    {
+        tmpreg = AFIO->PCFR1;
+    }
+
+    tmpmask = ( GPIO_Remap & DBGAFR_POSITION_MASK ) >> 0x10;
+    tmp = GPIO_Remap & LSB_MASK;
+
+    if( ( GPIO_Remap & ( DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK ) ) == ( DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK ) )
+    {
+        tmpreg &= DBGAFR_SWJCFG_MASK;
+        AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
+    }
+    else if( ( GPIO_Remap & DBGAFR_NUMBITS_MASK ) == DBGAFR_NUMBITS_MASK )
+    {
+        tmp1 = ( ( uint32_t )0x03 ) << tmpmask;
+        tmpreg &= ~tmp1;
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+    }
+    else
+    {
+        tmpreg &= ~( tmp << ( ( GPIO_Remap >> 0x15 ) * 0x10 ) );
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+    }
+
+    if( NewState != DISABLE )
+    {
+        tmpreg |= ( tmp << ( ( GPIO_Remap >> 0x15 ) * 0x10 ) );
+    }
+
+    if( ( GPIO_Remap & 0x80000000 ) == 0x80000000 )
+    {
+        AFIO->PCFR2 = tmpreg;
+    }
+    else
+    {
+        AFIO->PCFR1 = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_EXTILineConfig
+ *
+ * @brief   Selects the GPIO pin used as EXTI Line.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ *          GPIO_PinSource - specifies the EXTI line to be configured.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EXTILineConfig( uint8_t GPIO_PortSource, uint8_t GPIO_PinSource )
+{
+    uint32_t tmp = 0x00;
+
+    tmp = ( ( uint32_t )0x0F ) << ( 0x04 * ( GPIO_PinSource & ( uint8_t )0x03 ) );
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] |= ( ( ( uint32_t )GPIO_PortSource ) << ( 0x04 * ( GPIO_PinSource & ( uint8_t )0x03 ) ) );
+}
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_i2c.c

@@ -0,0 +1,985 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_i2c.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the I2C firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_i2c.h"
+#include "ch32f10x_rcc.h"
+
+
+/* I2C SPE mask */
+#define CTLR1_PE_Set              ((uint16_t)0x0001)
+#define CTLR1_PE_Reset            ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTLR1_START_Set           ((uint16_t)0x0100)
+#define CTLR1_START_Reset         ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTLR1_STOP_Set            ((uint16_t)0x0200)
+#define CTLR1_STOP_Reset          ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTLR1_ACK_Set             ((uint16_t)0x0400)
+#define CTLR1_ACK_Reset           ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTLR1_ENGC_Set            ((uint16_t)0x0040)
+#define CTLR1_ENGC_Reset          ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTLR1_SWRST_Set           ((uint16_t)0x8000)
+#define CTLR1_SWRST_Reset         ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTLR1_PEC_Set             ((uint16_t)0x1000)
+#define CTLR1_PEC_Reset           ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTLR1_ENPEC_Set           ((uint16_t)0x0020)
+#define CTLR1_ENPEC_Reset         ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTLR1_ENARP_Set           ((uint16_t)0x0010)
+#define CTLR1_ENARP_Reset         ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTLR1_NOSTRETCH_Set       ((uint16_t)0x0080)
+#define CTLR1_NOSTRETCH_Reset     ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTLR1_CLEAR_Mask          ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTLR2_DMAEN_Set           ((uint16_t)0x0800)
+#define CTLR2_DMAEN_Reset         ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTLR2_LAST_Set            ((uint16_t)0x1000)
+#define CTLR2_LAST_Reset          ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTLR2_FREQ_Reset          ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADD0_Set           ((uint16_t)0x0001)
+#define OADDR1_ADD0_Reset         ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_ENDUAL_Set         ((uint16_t)0x0001)
+#define OADDR2_ENDUAL_Reset       ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADD2_Reset         ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CKCFGR_FS_Set             ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CKCFGR_CCR_Set            ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask                 ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask                 ((uint32_t)0x07000000)
+
+
+/*********************************************************************
+ * @fn      I2C_DeInit
+ *
+ * @brief   Deinitializes the I2Cx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_DeInit( I2C_TypeDef *I2Cx )
+{
+    if( I2Cx == I2C1 )
+    {
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_I2C1, ENABLE );
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_I2C1, DISABLE );
+    }
+    else
+    {
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_I2C2, ENABLE );
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_I2C2, DISABLE );
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_Init
+ *
+ * @brief   Initializes the I2Cx peripheral according to the specified
+ *        parameters in the I2C_InitStruct.
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_InitStruct - pointer to a I2C_InitTypeDef structure that
+ *        contains the configuration information for the specified I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_Init( I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct )
+{
+    uint16_t tmpreg = 0, freqrange = 0;
+    uint16_t result = 0x04;
+    uint32_t pclk1 = 8000000;
+
+    RCC_ClocksTypeDef  rcc_clocks;
+
+    tmpreg = I2Cx->CTLR2;
+    tmpreg &= CTLR2_FREQ_Reset;
+    RCC_GetClocksFreq( &rcc_clocks );
+    pclk1 = rcc_clocks.PCLK1_Frequency;
+    freqrange = ( uint16_t )( pclk1 / 1000000 );
+    tmpreg |= freqrange;
+    I2Cx->CTLR2 = tmpreg;
+
+    I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    tmpreg = 0;
+
+    if( I2C_InitStruct->I2C_ClockSpeed <= 100000 )
+    {
+        result = ( uint16_t )( pclk1 / ( I2C_InitStruct->I2C_ClockSpeed << 1 ) );
+
+        if( result < 0x04 )
+        {
+            result = 0x04;
+        }
+
+        tmpreg |= result;
+        I2Cx->RTR = freqrange + 1;
+    }
+    else
+    {
+        if( I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2 )
+        {
+            result = ( uint16_t )( pclk1 / ( I2C_InitStruct->I2C_ClockSpeed * 3 ) );
+        }
+        else
+        {
+            result = ( uint16_t )( pclk1 / ( I2C_InitStruct->I2C_ClockSpeed * 25 ) );
+            result |= I2C_DutyCycle_16_9;
+        }
+
+        if( ( result & CKCFGR_CCR_Set ) == 0 )
+        {
+            result |= ( uint16_t )0x0001;
+        }
+
+        tmpreg |= ( uint16_t )( result | CKCFGR_FS_Set );
+        I2Cx->RTR = ( uint16_t )( ( ( freqrange * ( uint16_t )300 ) / ( uint16_t )1000 ) + ( uint16_t )1 );
+    }
+
+    I2Cx->CKCFGR = tmpreg;
+    I2Cx->CTLR1 |= CTLR1_PE_Set;
+
+
+    tmpreg = I2Cx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= ( uint16_t )( ( uint32_t )I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack );
+    I2Cx->CTLR1 = tmpreg;
+
+    I2Cx->OADDR1 = ( I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1 );
+}
+
+/*********************************************************************
+ * @fn      I2C_StructInit
+ *
+ * @brief   Fills each I2C_InitStruct member with its default value.
+ *
+ * @param   I2C_InitStruct - pointer to an I2C_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2C_StructInit( I2C_InitTypeDef *I2C_InitStruct )
+{
+    I2C_InitStruct->I2C_ClockSpeed = 5000;
+    I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+    I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+    I2C_InitStruct->I2C_OwnAddress1 = 0;
+    I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+    I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/*********************************************************************
+ * @fn      I2C_Cmd
+ *
+ * @brief   Enables or disables the specified I2C peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_Cmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_PE_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMACmd
+ *
+ * @brief   Enables or disables the specified I2C DMA requests.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMACmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMALastTransferCmd
+ *
+ * @brief   Specifies if the next DMA transfer will be the last one.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMALastTransferCmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR2 |= CTLR2_LAST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_LAST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTART
+ *
+ * @brief   Generates I2Cx communication START condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTART( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_START_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_START_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTOP
+ *
+ * @brief   Generates I2Cx communication STOP condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTOP( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_STOP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_STOP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_AcknowledgeConfig
+ *
+ * @brief   Enables or disables the specified I2C acknowledge feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_AcknowledgeConfig( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_ACK_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_OwnAddress2Config
+ *
+ * @brief   Configures the specified I2C own address2.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the 7bit I2C own address2.
+ *
+ * @return  none
+ */
+void I2C_OwnAddress2Config( I2C_TypeDef *I2Cx, uint8_t Address )
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = I2Cx->OADDR2;
+    tmpreg &= OADDR2_ADD2_Reset;
+    tmpreg |= ( uint16_t )( ( uint16_t )Address & ( uint16_t )0x00FE );
+    I2Cx->OADDR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      I2C_DualAddressCmd
+ *
+ * @brief   Enables or disables the specified I2C dual addressing mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DualAddressCmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
+    }
+    else
+    {
+        I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GeneralCallCmd
+ *
+ * @brief   Enables or disables the specified I2C general call feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GeneralCallCmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_ENGC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_ITConfig
+ *
+ * @brief   Enables or disables the specified I2C interrupts.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the I2C interrupts sources to be enabled or disabled.
+ *            I2C_IT_BUF - Buffer interrupt mask.
+ *            I2C_IT_EVT - Event interrupt mask.
+ *            I2C_IT_ERR - Error interrupt mask.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_ITConfig( I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR2 |= I2C_IT;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= ( uint16_t )~I2C_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SendData
+ *
+ * @brief   Sends a data byte through the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Data - Byte to be transmitted.
+ *
+ * @return  none
+ */
+void I2C_SendData( I2C_TypeDef *I2Cx, uint8_t Data )
+{
+    I2Cx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The value of the received data.
+ */
+uint8_t I2C_ReceiveData( I2C_TypeDef *I2Cx )
+{
+    return ( uint8_t )I2Cx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      I2C_Send7bitAddress
+ *
+ * @brief   Transmits the address byte to select the slave device.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the slave address which will be transmitted.
+ *          I2C_Direction - specifies whether the I2C device will be a
+ *        Transmitter or a Receiver.
+ *            I2C_Direction_Transmitter - Transmitter mode.
+ *            I2C_Direction_Receiver - Receiver mode.
+ *
+ * @return  none
+ */
+void I2C_Send7bitAddress( I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction )
+{
+    if( I2C_Direction != I2C_Direction_Transmitter )
+    {
+        Address |= OADDR1_ADD0_Set;
+    }
+    else
+    {
+        Address &= OADDR1_ADD0_Reset;
+    }
+
+    I2Cx->DATAR = Address;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReadRegister
+ *
+ * @brief   Reads the specified I2C register and returns its value.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_Register - specifies the register to read.
+ *            I2C_Register_CTLR1.
+ *            I2C_Register_CTLR2.
+ *            I2C_Register_OADDR1.
+ *            I2C_Register_OADDR2.
+ *            I2C_Register_DATAR.
+ *            I2C_Register_STAR1.
+ *            I2C_Register_STAR2.
+ *            I2C_Register_CKCFGR.
+ *            I2C_Register_RTR.
+ *
+ * @return  none
+ */
+uint16_t I2C_ReadRegister( I2C_TypeDef *I2Cx, uint8_t I2C_Register )
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = ( uint32_t ) I2Cx;
+    tmp += I2C_Register;
+
+    return ( *( __IO uint16_t * ) tmp );
+}
+
+/*********************************************************************
+ * @fn      I2C_SoftwareResetCmd
+ *
+ * @brief   Enables or disables the specified I2C software reset.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_SoftwareResetCmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_SWRST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_NACKPositionConfig
+ *
+ * @brief   Selects the specified I2C NACK position in master receiver mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_NACKPosition - specifies the NACK position.
+ *            I2C_NACKPosition_Next - indicates that the next byte will be
+ *        the last received byte.
+ *            I2C_NACKPosition_Current - indicates that current byte is the
+ *        last received byte.
+ *
+ * @return  none
+ */
+void I2C_NACKPositionConfig( I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition )
+{
+    if( I2C_NACKPosition == I2C_NACKPosition_Next )
+    {
+        I2Cx->CTLR1 |= I2C_NACKPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_NACKPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SMBusAlertConfig
+ *
+ * @brief   Drives the SMBusAlert pin high or low for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_SMBusAlert - specifies SMBAlert pin level.
+ *            I2C_SMBusAlert_Low - SMBAlert pin driven low.
+ *            I2C_SMBusAlert_High - SMBAlert pin driven high.
+ *
+ * @return  none
+ */
+void I2C_SMBusAlertConfig( I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert )
+{
+    if( I2C_SMBusAlert == I2C_SMBusAlert_Low )
+    {
+        I2Cx->CTLR1 |= I2C_SMBusAlert_Low;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_SMBusAlert_High;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_TransmitPEC
+ *
+ * @brief   Enables or disables the specified I2C PEC transfer.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_TransmitPEC( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_PEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_PECPositionConfig
+ *
+ * @brief   Selects the specified I2C PEC position.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_PECPosition - specifies the PEC position.
+ *            I2C_PECPosition_Next - indicates that the next byte is PEC.
+ *            I2C_PECPosition_Current - indicates that current byte is PEC.
+ *
+ * @return  none
+ */
+void I2C_PECPositionConfig( I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition )
+{
+    if( I2C_PECPosition == I2C_PECPosition_Next )
+    {
+        I2Cx->CTLR1 |= I2C_PECPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_PECPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_CalculatePEC
+ *
+ * @brief   Enables or disables the PEC value calculation of the transferred bytes.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_CalculatePEC( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GetPEC
+ *
+ * @brief   Returns the PEC value for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The PEC value.
+ */
+uint8_t I2C_GetPEC( I2C_TypeDef *I2Cx )
+{
+    return ( ( I2Cx->STAR2 ) >> 8 );
+}
+
+/*********************************************************************
+ * @fn      I2C_ARPCmd
+ *
+ * @brief   Enables or disables the specified I2C ARP.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *            NewState - ENABLE or DISABLE.
+ *
+ * @return  The PEC value.
+ */
+void I2C_ARPCmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_ENARP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_StretchClockCmd
+ *
+ * @brief   Enables or disables the specified I2C Clock stretching.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_StretchClockCmd( I2C_TypeDef *I2Cx, FunctionalState NewState )
+{
+    if( NewState == DISABLE )
+    {
+        I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_FastModeDutyCycleConfig
+ *
+ * @brief   Selects the specified I2C fast mode duty cycle.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_DutyCycle - specifies the fast mode duty cycle.
+ *            I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2.
+ *            I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9.
+ *
+ * @return  none
+ */
+void I2C_FastModeDutyCycleConfig( I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle )
+{
+    if( I2C_DutyCycle != I2C_DutyCycle_16_9 )
+    {
+        I2Cx->CKCFGR &= I2C_DutyCycle_2;
+    }
+    else
+    {
+        I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
+    }
+}
+
+
+/*********************************************************************
+ * @fn      I2C_CheckEvent
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_EVENT: specifies the event to be checked.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2.
+ *             I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3.
+ *             I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2.
+ *             I2C_EVENT_SLAVE_STOP_DETECTED - EV4.
+ *             I2C_EVENT_MASTER_MODE_SELECT - EV5.
+ *             I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_BYTE_RECEIVED - EV7.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2.
+ *             I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9.
+ *
+ * @return  ErrorStatus - SUCCESS or ERROR.
+ */
+ErrorStatus I2C_CheckEvent( I2C_TypeDef *I2Cx, uint32_t I2C_EVENT )
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0, flag2 = 0;
+    ErrorStatus status = ERROR;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+
+    lastevent = ( flag1 | flag2 ) & FLAG_Mask;
+
+    if( ( lastevent & I2C_EVENT ) == I2C_EVENT )
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    return status;
+}
+
+
+/*********************************************************************
+ * @fn      I2C_GetLastEvent
+ *
+ * @brief   Returns the last I2Cx Event.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+uint32_t I2C_GetLastEvent( I2C_TypeDef *I2Cx )
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0, flag2 = 0;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+    lastevent = ( flag1 | flag2 ) & FLAG_Mask;
+
+    return lastevent;
+}
+
+
+/*********************************************************************
+ * @fn      I2C_GetFlagStatus
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to check.
+ *            I2C_FLAG_DUALF - Dual flag (Slave mode).
+ *            I2C_FLAG_SMBHOST - SMBus host header (Slave mode).
+ *            I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode).
+ *            I2C_FLAG_GENCALL - General call header flag (Slave mode).
+ *            I2C_FLAG_TRA - Transmitter/Receiver flag.
+ *            I2C_FLAG_BUSY - Bus busy flag.
+ *            I2C_FLAG_MSL - Master/Slave flag.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *            I2C_FLAG_TXE - Data register empty flag (Transmitter).
+ *            I2C_FLAG_RXNE- Data register not empty (Receiver) flag.
+ *            I2C_FLAG_STOPF - Stop detection flag (Slave mode).
+ *            I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_FLAG_BTF - Byte transfer finished flag.
+ *            I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL"
+ *        Address matched flag (Slave mode)"ENDA".
+ *            I2C_FLAG_SB - Start bit flag (Master mode).
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus I2C_GetFlagStatus( I2C_TypeDef *I2Cx, uint32_t I2C_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+    __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+    i2cxbase = ( uint32_t )I2Cx;
+    i2creg = I2C_FLAG >> 28;
+    I2C_FLAG &= FLAG_Mask;
+
+    if( i2creg != 0 )
+    {
+        i2cxbase += 0x14;
+    }
+    else
+    {
+        I2C_FLAG = ( uint32_t )( I2C_FLAG >> 16 );
+        i2cxbase += 0x18;
+    }
+
+    if( ( ( *( __IO uint32_t * )i2cxbase ) & I2C_FLAG ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearFlag
+ *
+ * @brief   Clears the I2Cx's pending flags.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to clear.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *
+ * @return  none
+ */
+void I2C_ClearFlag( I2C_TypeDef *I2Cx, uint32_t I2C_FLAG )
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_FLAG & FLAG_Mask;
+    I2Cx->STAR1 = ( uint16_t )~flagpos;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetITStatus
+ *
+ * @brief   Checks whether the specified I2C interrupt has occurred or not.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          II2C_IT - specifies the interrupt source to check.
+ *            I2C_IT_SMBALERT - SMBus Alert flag.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_IT_PECERR - PEC error in reception flag.
+ *            I2C_IT_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure flag.
+ *            I2C_IT_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_IT_BERR - Bus error flag.
+ *            I2C_IT_TXE - Data register empty flag (Transmitter).
+ *            I2C_IT_RXNE - Data register not empty (Receiver) flag.
+ *            I2C_IT_STOPF - Stop detection flag (Slave mode).
+ *            I2C_IT_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_IT_BTF - Byte transfer finished flag.
+ *            I2C_IT_ADDR - Address sent flag (Master mode) "ADSL"  Address matched
+ *        flag (Slave mode)"ENDAD".
+ *            I2C_IT_SB - Start bit flag (Master mode).
+ *
+ * @return  none
+ */
+ITStatus I2C_GetITStatus( I2C_TypeDef *I2Cx, uint32_t I2C_IT )
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = ( uint32_t )( ( ( I2C_IT & ITEN_Mask ) >> 16 ) & ( I2Cx->CTLR2 ) ) ;
+    I2C_IT &= FLAG_Mask;
+
+    if( ( ( I2Cx->STAR1 & I2C_IT ) != ( uint32_t )RESET ) && enablestatus )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearITPendingBit
+ *
+ * @brief   Clears the I2Cx interrupt pending bits.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the interrupt pending bit to clear.
+ *            I2C_IT_SMBALERT - SMBus Alert interrupt.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error interrupt.
+ *            I2C_IT_PECERR - PEC error in reception  interrupt.
+ *            I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure interrupt.
+ *            I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
+ *            I2C_IT_BERR - Bus error interrupt.
+ *
+ * @return  none
+ */
+void I2C_ClearITPendingBit( I2C_TypeDef *I2Cx, uint32_t I2C_IT )
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_IT & FLAG_Mask;
+    I2Cx->STAR1 = ( uint16_t )~flagpos;
+}
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_iwdg.c

@@ -0,0 +1,125 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32f10x_iwdg.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the IWDG firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_iwdg.h"
+
+/* CTLR register bit mask */
+#define CTLR_KEY_Reload    ((uint16_t)0xAAAA)
+#define CTLR_KEY_Enable    ((uint16_t)0xCCCC)
+
+/*********************************************************************
+ * @fn      IWDG_WriteAccessCmd
+ *
+ * @brief   Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
+ *
+ * @param   WDG_WriteAccess - new state of write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
+ *        and IWDG_RLDR registers.
+ *
+ * @return  none
+ */
+void IWDG_WriteAccessCmd( uint16_t IWDG_WriteAccess )
+{
+    IWDG->CTLR = IWDG_WriteAccess;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetPrescaler
+ *
+ * @brief   Sets IWDG Prescaler value.
+ *
+ * @param   IWDG_Prescaler - specifies the IWDG Prescaler value.
+ *             IWDG_Prescaler_4 - IWDG prescaler set to 4.
+ *             IWDG_Prescaler_8 - IWDG prescaler set to 8.
+ *             IWDG_Prescaler_16 - IWDG prescaler set to 16.
+ *             IWDG_Prescaler_32 - IWDG prescaler set to 32.
+ *             IWDG_Prescaler_64 - IWDG prescaler set to 64.
+ *             IWDG_Prescaler_128 - IWDG prescaler set to 128.
+ *             IWDG_Prescaler_256 - IWDG prescaler set to 256.
+ *
+ * @return  none
+ */
+void IWDG_SetPrescaler( uint8_t IWDG_Prescaler )
+{
+    IWDG->PSCR = IWDG_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetReload
+ *
+ * @brief   Sets IWDG Reload value.
+ *
+ * @param   Reload - specifies the IWDG Reload value.
+ *            This parameter must be a number between 0 and 0x0FFF.
+ *
+ * @return  none
+ */
+void IWDG_SetReload( uint16_t Reload )
+{
+    IWDG->RLDR = Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_ReloadCounter
+ *
+ * @brief   Reloads IWDG counter with value defined in the reload register.
+ *
+ * @return  none
+ */
+void IWDG_ReloadCounter( void )
+{
+    IWDG->CTLR = CTLR_KEY_Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_Enable
+ *
+ * @brief   Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
+ *
+ * @return  none
+ */
+void IWDG_Enable( void )
+{
+    IWDG->CTLR = CTLR_KEY_Enable;
+}
+
+/*********************************************************************
+ * @fn      IWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the specified IWDG flag is set or not.
+ *
+ * @param   IWDG_FLAG - specifies the flag to check.
+ *            IWDG_FLAG_PVU - Prescaler Value Update on going.
+ *            IWDG_FLAG_RVU - Reload Value Update on going.
+ *
+ * @return  none
+ */
+FlagStatus IWDG_GetFlagStatus( uint16_t IWDG_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+
+    if( ( IWDG->STATR & IWDG_FLAG ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_misc.c

@@ -0,0 +1,148 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_misc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the miscellaneous firmware functions (add-on
+ *                      to CMSIS functions).
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32f10x_misc.h"
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+
+/*********************************************************************
+ * @fn      NVIC_PriorityGroupConfig
+ *
+ * @brief   Configures the priority grouping - pre-emption priority and subpriority.
+ *
+ * @param   NVIC_PriorityGroup - specifies the priority grouping bits length.
+ *            NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
+ *                                   4 bits for subpriority
+ *            NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
+ *                                   3 bits for subpriority
+ *            NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
+ *                                   2 bits for subpriority
+ *            NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
+ *                                   1 bits for subpriority
+ *            NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
+ *                                   0 bits for subpriority
+ *
+ * @return  none
+ */
+void NVIC_PriorityGroupConfig( uint32_t NVIC_PriorityGroup )
+{
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/*********************************************************************
+ * @fn      NVIC_Init
+ *
+ * @brief   Initializes the NVIC peripheral according to the specified parameters in
+ *        the NVIC_InitStruct.
+ *
+ * @param   NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
+ *        configuration information for the specified NVIC peripheral.
+ *
+ * @return  none
+ */
+void NVIC_Init( NVIC_InitTypeDef *NVIC_InitStruct )
+{
+    uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+    if( NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE )
+    {
+        /* Compute the Corresponding IRQ Priority */
+        tmppriority = ( 0x700 - ( ( SCB->AIRCR ) & ( uint32_t )0x700 ) ) >> 0x08;
+        tmppre = ( 0x4 - tmppriority );
+        tmpsub = tmpsub >> tmppriority;
+
+        tmppriority = ( uint32_t )NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+        tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+        tmppriority = tmppriority << 0x04;
+
+        NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+        /* Enable the Selected IRQ Channels */
+        NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+            ( uint32_t )0x01 << ( NVIC_InitStruct->NVIC_IRQChannel & ( uint8_t )0x1F );
+    }
+    else
+    {
+        /* Disable the Selected IRQ Channels */
+        NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+            ( uint32_t )0x01 << ( NVIC_InitStruct->NVIC_IRQChannel & ( uint8_t )0x1F );
+    }
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetVectorTable
+ *
+ * @brief   Sets the vector table location and Offset.
+ *
+ * @param   NVIC_VectTab - specifies if the vector table is in RAM or FLASH memory.The
+ *        value can be NVIC_VectTab_RAM or NVIC_VectTab_FLASH.
+ *        Offset - Vector Table base offset field. This value must be a multiple of 0x200.
+ *
+ * @return  none
+ */
+void NVIC_SetVectorTable( uint32_t NVIC_VectTab, uint32_t Offset )
+{
+    SCB->VTOR = NVIC_VectTab | ( Offset & ( uint32_t )0x1FFFFF80 );
+}
+
+/*********************************************************************
+ * @fn      NVIC_SystemLPConfig
+ *
+ * @brief   Selects the condition for the system to enter low power mode.
+ *
+ * @param   LowPowerMode - Specifies the new mode for the system to enter low power mode.
+ *                   NVIC_LP_SEVONPEND
+ *                   NVIC_LP_SLEEPDEEP
+ *                   NVIC_LP_SLEEPONEXIT
+ *          NewState -  new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ *          
+ * @return  none
+ */
+void NVIC_SystemLPConfig( uint8_t LowPowerMode, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        SCB->SCR |= LowPowerMode;
+    }
+    else
+    {
+        SCB->SCR &= ( uint32_t )( ~( uint32_t )LowPowerMode );
+    }
+}
+
+
+/*********************************************************************
+ * @fn      SysTick_CLKSourceConfig
+ *
+ * @brief   Configures the SysTick clock source.
+ *
+ * @param   SysTick_CLKSource: Specifies the new mode for the system to enter low power mode.
+ *           ysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+ *           SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+ *          
+ * @return  none
+ */
+void SysTick_CLKSourceConfig( uint32_t SysTick_CLKSource )
+{
+    if( SysTick_CLKSource == SysTick_CLKSource_HCLK )
+    {
+        SysTick->CTRL |= SysTick_CLKSource_HCLK;
+    }
+    else
+    {
+        SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+    }
+}
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_pwr.c

@@ -0,0 +1,218 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_pwr.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the PWR firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ********************************************************************************/
+#include "ch32f10x_pwr.h"
+#include "ch32f10x_rcc.h"
+
+/* PWR registers bit address in the alias region */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* CTLR Register */
+/* Alias word address of DBP bit */
+#define CTLR_OFFSET              (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CTLR_DBP_BB              (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CTLR_PVDE_BB             (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* CSR Register */
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* PWR registers bit mask */
+/* CTLR register bit mask */
+#define CTLR_DS_MASK             ((uint32_t)0xFFFFFFFC)
+#define CTLR_PLS_MASK            ((uint32_t)0xFFFFFF1F)
+
+/*********************************************************************
+ * @fn      PWR_DeInit
+ *
+ * @brief   Deinitializes the PWR peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none
+ */
+void PWR_DeInit( void )
+{
+    RCC_APB1PeriphResetCmd( RCC_APB1Periph_PWR, ENABLE );
+    RCC_APB1PeriphResetCmd( RCC_APB1Periph_PWR, DISABLE );
+}
+
+
+/*********************************************************************
+ * @fn      PWR_BackupAccessCmd
+ *
+ * @brief   Enables or disables access to the RTC and backup registers.
+ *
+ * @param   NewState - new state of the access to the RTC and backup registers,
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void PWR_BackupAccessCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) CTLR_DBP_BB = ( uint32_t )NewState;
+}
+
+
+/*********************************************************************
+ * @fn      PWR_PVDCmd
+ *
+ * @brief   Enables or disables the Power Voltage Detector(PVD).
+ *
+ * @param   NewState - new state of the PVD(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_PVDCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) CTLR_PVDE_BB = ( uint32_t )NewState;
+}
+
+
+/*********************************************************************
+ * @fn      PWR_PVDLevelConfig
+ *
+ * @brief   Configures the voltage threshold detected by the Power Voltage
+ *        Detector(PVD).
+ *
+ * @param   PWR_PVDLevel - specifies the PVD detection level
+ *            PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
+ *            PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
+ *            PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
+ *            PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
+ *            PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
+ *            PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
+ *            PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
+ *            PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
+ *
+ * @return  none
+ */
+void PWR_PVDLevelConfig( uint32_t PWR_PVDLevel )
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_PLS_MASK;
+    tmpreg |= PWR_PVDLevel;
+    PWR->CTLR = tmpreg;
+}
+
+
+/*********************************************************************
+ * @fn      PWR_WakeUpPinCmd
+ *
+ * @brief   Enables or disables the WakeUp Pin functionality.
+ *
+ * @param   NewState - new state of the WakeUp Pin functionality
+ *        (ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_WakeUpPinCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) CSR_EWUP_BB = ( uint32_t )NewState;
+}
+
+
+/*********************************************************************
+ * @fn      PWR_EnterSTOPMode
+ *
+ * @brief   Enters STOP mode.
+ *
+ * @param   PWR_Regulator - specifies the regulator state in STOP mode.
+ *            PWR_Regulator_ON - STOP mode with regulator ON
+ *            PWR_Regulator_LowPower - STOP mode with regulator in low power mode
+ *          PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
+ *            PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
+ *            PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
+ *
+ * @return  none
+ */
+void PWR_EnterSTOPMode( uint32_t PWR_Regulator, uint8_t PWR_STOPEntry )
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_DS_MASK;
+    tmpreg |= PWR_Regulator;
+    PWR->CTLR = tmpreg;
+    SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+    if( PWR_STOPEntry == PWR_STOPEntry_WFI )
+    {
+        __WFI();
+    }
+    else
+    {
+        __WFE();
+    }
+
+    SCB->SCR &= ( uint32_t )~( ( uint32_t )SCB_SCR_SLEEPDEEP );
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode
+ *
+ * @brief   Enters STANDBY mode.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode( void )
+{
+    PWR->CTLR |= PWR_CTLR_CWUF;
+    PWR->CTLR |= PWR_CTLR_PDDS;
+    SCB->SCR |= SCB_SCR_SLEEPDEEP;
+#if defined ( __CC_ARM   )
+    __force_stores();
+#endif
+    __WFI();
+}
+
+
+/********************************************************************************
+* Function Name  : PWR_GetFlagStatus
+* Description    : Checks whether the specified PWR flag is set or not.
+* Input          : PWR_FLAG: specifies the flag to check.
+*                     PWR_FLAG_WU: Wake Up flag
+*                     PWR_FLAG_SB: StandBy flag
+*                     PWR_FLAG_PVDO: PVD Output
+* Return         : The new state of PWR_FLAG (SET or RESET).
+*********************************************************************************/
+FlagStatus PWR_GetFlagStatus( uint32_t PWR_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+
+    if( ( PWR->CSR & PWR_FLAG ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+
+/********************************************************************************
+* Function Name  : PWR_ClearFlag
+* Description    : Clears the PWR's pending flags.
+* Input          : PWR_FLAG: specifies the flag to clear.
+*                     PWR_FLAG_WU: Wake Up flag
+*                     PWR_FLAG_SB: StandBy flag
+* Return         : None
+*********************************************************************************/
+void PWR_ClearFlag( uint32_t PWR_FLAG )
+{
+    PWR->CTLR |=  PWR_FLAG << 2;
+}
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_rcc.c

@@ -0,0 +1,931 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_rcc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the RCC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_rcc.h"
+
+/* RCC registers bit address in the alias region */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+
+/* CTLR Register */
+
+/* Alias word address of HSION bit */
+#define CTLR_OFFSET               (RCC_OFFSET + 0x00)
+#define HSION_BitNumber           0x00
+#define CTLR_HSION_BB             (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber           0x18
+#define CTLR_PLLON_BB             (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber           0x13
+#define CTLR_CSSON_BB             (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* CFGR0 Register */
+
+/* Alias word address of USBPRE bit */
+#define CFGR0_OFFSET              (RCC_OFFSET + 0x04)
+#define USBPRE_BitNumber          0x16
+#define CFGR0_USBPRE_BB           (PERIPH_BB_BASE + (CFGR0_OFFSET * 32) + (USBPRE_BitNumber * 4))
+
+/* BDCTLR Register */
+
+/* Alias word address of RTCEN bit */
+#define BDCTLR_OFFSET             (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber           0x0F
+#define BDCTLR_RTCEN_BB           (PERIPH_BB_BASE + (BDCTLR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber           0x10
+#define BDCTLR_BDRST_BB           (PERIPH_BB_BASE + (BDCTLR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* RSTSCKR Register */
+
+/* Alias word address of LSION bit */
+#define RSTSCKR_OFFSET            (RCC_OFFSET + 0x24)
+#define LSION_BitNumber           0x00
+#define RSTSCKR_LSION_BB          (PERIPH_BB_BASE + (RSTSCKR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* RCC registers bit mask */
+
+/* CTLR register bit mask */
+#define CTLR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
+#define CTLR_HSEBYP_Set             ((uint32_t)0x00040000)
+#define CTLR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
+#define CTLR_HSEON_Set              ((uint32_t)0x00010000)
+#define CTLR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
+
+#define CFGR0_PLL_Mask              ((uint32_t)0xFFC0FFFF)
+#define CFGR0_PLLMull_Mask          ((uint32_t)0x003C0000)
+#define CFGR0_PLLSRC_Mask           ((uint32_t)0x00010000)
+#define CFGR0_PLLXTPRE_Mask         ((uint32_t)0x00020000)
+#define CFGR0_SWS_Mask              ((uint32_t)0x0000000C)
+#define CFGR0_SW_Mask               ((uint32_t)0xFFFFFFFC)
+#define CFGR0_HPRE_Reset_Mask       ((uint32_t)0xFFFFFF0F)
+#define CFGR0_HPRE_Set_Mask         ((uint32_t)0x000000F0)
+#define CFGR0_PPRE1_Reset_Mask      ((uint32_t)0xFFFFF8FF)
+#define CFGR0_PPRE1_Set_Mask        ((uint32_t)0x00000700)
+#define CFGR0_PPRE2_Reset_Mask      ((uint32_t)0xFFFFC7FF)
+#define CFGR0_PPRE2_Set_Mask        ((uint32_t)0x00003800)
+#define CFGR0_ADCPRE_Reset_Mask     ((uint32_t)0xFFFF3FFF)
+#define CFGR0_ADCPRE_Set_Mask       ((uint32_t)0x0000C000)
+
+/* RSTSCKR register bit mask */
+#define RSTSCKR_RMVF_Set            ((uint32_t)0x01000000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                   ((uint8_t)0x1F)
+
+/* INTR register byte 2 (Bits[15:8]) base address */
+#define INTR_BYTE2_ADDRESS          ((uint32_t)0x40021009)
+
+/* INTR register byte 3 (Bits[23:16]) base address */
+#define INTR_BYTE3_ADDRESS          ((uint32_t)0x4002100A)
+
+/* CFGR0 register byte 4 (Bits[31:24]) base address */
+#define CFGR0_BYTE4_ADDRESS         ((uint32_t)0x40021007)
+
+/* BDCTLR register base address */
+#define BDCTLR_ADDRESS              (PERIPH_BASE + BDCTLR_OFFSET)
+
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/*********************************************************************
+ * @fn      RCC_DeInit
+ *
+ * @brief   Resets the RCC clock configuration to the default reset state.
+ *
+ * @return  none
+ */
+void RCC_DeInit( void )
+{
+    RCC->CTLR |= ( uint32_t )0x00000001;
+    RCC->CFGR0 &= ( uint32_t )0xF8FF0000;
+    RCC->CTLR &= ( uint32_t )0xFEF6FFFF;
+    RCC->CTLR &= ( uint32_t )0xFFFBFFFF;
+    RCC->CFGR0 &= ( uint32_t )0xFF80FFFF;
+    RCC->INTR = 0x009F0000;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSEConfig
+ *
+ * @brief   Configures the External High Speed oscillator (HSE).
+ *
+ * @param   RCC_HSE -
+ *            RCC_HSE_OFF - HSE oscillator OFF.
+ *            RCC_HSE_ON - HSE oscillator ON.
+ *            RCC_HSE_Bypass - HSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_HSEConfig( uint32_t RCC_HSE )
+{
+    RCC->CTLR &= CTLR_HSEON_Reset;
+    RCC->CTLR &= CTLR_HSEBYP_Reset;
+
+    switch( RCC_HSE )
+    {
+        case RCC_HSE_ON:
+            RCC->CTLR |= CTLR_HSEON_Set;
+            break;
+
+        case RCC_HSE_Bypass:
+            RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_WaitForHSEStartUp
+ *
+ * @brief   Waits for HSE start-up.
+ *
+ * @return  SUCCESS - HSE oscillator is stable and ready to use.
+ *                  ERROR - HSE oscillator not yet ready.
+ */
+ErrorStatus RCC_WaitForHSEStartUp( void )
+{
+    __IO uint32_t StartUpCounter = 0;
+
+    ErrorStatus status = ERROR;
+    FlagStatus HSEStatus = RESET;
+
+    do
+    {
+        HSEStatus = RCC_GetFlagStatus( RCC_FLAG_HSERDY );
+        StartUpCounter++;
+    }
+    while( ( StartUpCounter != HSE_STARTUP_TIMEOUT ) && ( HSEStatus == RESET ) );
+
+    if( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) != RESET )
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    return ( status );
+}
+
+/*********************************************************************
+ * @fn      RCC_AdjustHSICalibrationValue
+ *
+ * @brief   Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ *
+ * @param   HSICalibrationValue - specifies the calibration trimming value.
+ *                    This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void RCC_AdjustHSICalibrationValue( uint8_t HSICalibrationValue )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CTLR;
+    tmpreg &= CTLR_HSITRIM_Mask;
+    tmpreg |= ( uint32_t )HSICalibrationValue << 3;
+    RCC->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSICmd
+ *
+ * @brief   Enables or disables the Internal High Speed oscillator (HSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_HSICmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) CTLR_HSION_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLConfig
+ *
+ * @brief   Configures the PLL clock source and multiplication factor.
+ *
+ * @param   RCC_PLLSource - specifies the PLL entry clock source.
+ *          RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2
+ *        selected as PLL clock entry.
+ *          RCC_PLLSource_HSE_Div1 - HSE oscillator clock selected as PLL
+ *        clock entry.
+ *          RCC_PLLSource_HSE_Div2 - HSE oscillator clock divided by 2
+ *        selected as PLL clock entry.
+ *          RCC_PLLMul - specifies the PLL multiplication factor.
+ *          This parameter can be RCC_PLLMul_x where x:[2,16].
+ *
+ * @return  none
+ */
+void RCC_PLLConfig( uint32_t RCC_PLLSource, uint32_t RCC_PLLMul )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PLL_Mask;
+    tmpreg |= RCC_PLLSource | RCC_PLLMul;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLCmd
+ *
+ * @brief   Enables or disables the PLL.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLLCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) CTLR_PLLON_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      RCC_SYSCLKConfig
+ *
+ * @brief   Configures the system clock (SYSCLK).
+ *
+ * @param   RCC_SYSCLKSource - specifies the clock source used as system clock.
+ *            RCC_SYSCLKSource_HSI - HSI selected as system clock.
+ *            RCC_SYSCLKSource_HSE - HSE selected as system clock.
+ *            RCC_SYSCLKSource_PLLCLK - PLL selected as system clock.
+ *
+ * @return  none
+ */
+void RCC_SYSCLKConfig( uint32_t RCC_SYSCLKSource )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_SW_Mask;
+    tmpreg |= RCC_SYSCLKSource;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetSYSCLKSource
+ *
+ * @brief   Returns the clock source used as system clock.
+ *
+ * @return  0x00 - HSI used as system clock.
+ *          0x04 - HSE used as system clock.
+ *          0x08 - PLL used as system clock.
+ */
+uint8_t RCC_GetSYSCLKSource( void )
+{
+    return ( ( uint8_t )( RCC->CFGR0 & CFGR0_SWS_Mask ) );
+}
+
+/*********************************************************************
+ * @fn      RCC_HCLKConfig
+ *
+ * @brief   Configures the AHB clock (HCLK).
+ *
+ * @param   RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
+ *        the system clock (SYSCLK).
+ *            RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
+ *            RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
+ *            RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
+ *            RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
+ *            RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
+ *            RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
+ *            RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
+ *            RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
+ *            RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512.
+ *
+ * @return  none
+ */
+void RCC_HCLKConfig( uint32_t RCC_SYSCLK )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_HPRE_Reset_Mask;
+    tmpreg |= RCC_SYSCLK;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK1Config
+ *
+ * @brief   Configures the Low Speed APB clock (PCLK1).
+ *
+ * @param   RCC_HCLK - defines the APB1 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK1Config( uint32_t RCC_HCLK )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PPRE1_Reset_Mask;
+    tmpreg |= RCC_HCLK;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK2Config
+ *
+ * @brief   Configures the High Speed APB clock (PCLK2).
+ *
+ * @param   RCC_HCLK - defines the APB2 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK2Config( uint32_t RCC_HCLK )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PPRE2_Reset_Mask;
+    tmpreg |= RCC_HCLK << 3;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_ITConfig
+ *
+ * @brief   Enables or disables the specified RCC interrupts.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt sources to be enabled or disabled.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ITConfig( uint8_t RCC_IT, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        *( __IO uint8_t * ) INTR_BYTE2_ADDRESS |= RCC_IT;
+    }
+    else
+    {
+        *( __IO uint8_t * ) INTR_BYTE2_ADDRESS &= ( uint8_t )~RCC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_USBCLKConfig
+ *
+ * @brief   Configures the USB clock (USBCLK).
+ *
+ * @param   RCC_USBCLKSource: specifies the USB clock source. This clock is
+ *        derived from the PLL output.
+ *          RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ *        clock source.
+ *          RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source.
+ *
+ * @return  none
+ */
+void RCC_USBCLKConfig( uint32_t RCC_USBCLKSource )
+{
+    *( __IO uint32_t * ) CFGR0_USBPRE_BB = RCC_USBCLKSource;
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKConfig
+ *
+ * @brief   Configures the ADC clock (ADCCLK).
+ *
+ * @param   RCC_PCLK2 - defines the ADC clock divider. This clock is derived from
+ *        the APB2 clock (PCLK2).
+ *          RCC_PCLK2_Div2 - ADC clock = PCLK2/2.
+ *          RCC_PCLK2_Div4 - ADC clock = PCLK2/4.
+ *          RCC_PCLK2_Div6 - ADC clock = PCLK2/6.
+ *          RCC_PCLK2_Div8 - ADC clock = PCLK2/8.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKConfig( uint32_t RCC_PCLK2 )
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_ADCPRE_Reset_Mask;
+    tmpreg |= RCC_PCLK2;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_LSEConfig
+ *
+ * @brief   Configures the External Low Speed oscillator (LSE).
+ *
+ * @param   RCC_LSE - specifies the new state of the LSE.
+ *            RCC_LSE_OFF - LSE oscillator OFF.
+ *            RCC_LSE_ON - LSE oscillator ON.
+ *            RCC_LSE_Bypass - LSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_LSEConfig( uint8_t RCC_LSE )
+{
+    *( __IO uint8_t * ) BDCTLR_ADDRESS = RCC_LSE_OFF;
+    *( __IO uint8_t * ) BDCTLR_ADDRESS = RCC_LSE_OFF;
+
+    switch( RCC_LSE )
+    {
+        case RCC_LSE_ON:
+            *( __IO uint8_t * ) BDCTLR_ADDRESS = RCC_LSE_ON;
+            break;
+
+        case RCC_LSE_Bypass:
+            *( __IO uint8_t * ) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_LSICmd
+ *
+ * @brief   Enables or disables the Internal Low Speed oscillator (LSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_LSICmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) RSTSCKR_LSION_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKConfig
+ *
+ * @brief   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ *
+ * @param   RCC_RTCCLKSource - specifies the RTC clock source.
+ *            RCC_RTCCLKSource_LSE - LSE selected as RTC clock.
+ *            RCC_RTCCLKSource_LSI - LSI selected as RTC clock.
+ *            RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKConfig( uint32_t RCC_RTCCLKSource )
+{
+    RCC->BDCTLR |= RCC_RTCCLKSource;
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKCmd
+ *
+ * @brief   This function must be used only after the RTC clock was selected
+ *        using the RCC_RTCCLKConfig function.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) BDCTLR_RTCEN_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetClocksFreq
+ *
+ * @brief   The result of this function could be not correct when using
+ *        fractional value for HSE crystal.
+ *
+ * @param   RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
+ *        the clocks frequencies.
+ *
+ * @return  none
+ */
+void RCC_GetClocksFreq( RCC_ClocksTypeDef *RCC_Clocks )
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+    tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
+
+    switch( tmp )
+    {
+        case 0x00:
+            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+            break;
+
+        case 0x04:
+            RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+            break;
+
+        case 0x08:
+            pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
+            pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
+            pllmull = ( pllmull >> 18 ) + 2;
+
+            if( pllsource == 0x00 )
+            {
+                if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE )
+                {
+                    RCC_Clocks->SYSCLK_Frequency = ( HSI_VALUE ) * pllmull;
+                }
+                else
+                {
+                    RCC_Clocks->SYSCLK_Frequency = ( HSI_VALUE >> 1 ) * pllmull;
+                }
+            }
+            else
+            {
+                if( ( RCC->CFGR0 & CFGR0_PLLXTPRE_Mask ) != ( uint32_t )RESET )
+                {
+                    RCC_Clocks->SYSCLK_Frequency = ( HSE_VALUE >> 1 ) * pllmull;
+                }
+                else
+                {
+                    RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+                }
+            }
+            break;
+
+        default:
+            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+            break;
+    }
+
+    tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
+    tmp = tmp >> 4;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
+    tmp = tmp >> 8;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
+    tmp = tmp >> 11;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
+    tmp = tmp >> 14;
+    presc = ADCPrescTable[tmp];
+    RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/*********************************************************************
+ * @fn      RCC_AHBPeriphClockCmd
+ *
+ * @brief   Enables or disables the AHB peripheral clock.
+ *
+ * @param   RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
+ *            RCC_AHBPeriph_DMA1.
+ *            RCC_AHBPeriph_DMA2.
+ *            RCC_AHBPeriph_SRAM.
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_AHBPeriphClockCmd( uint32_t RCC_AHBPeriph, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        RCC->AHBPCENR |= RCC_AHBPeriph;
+    }
+    else
+    {
+        RCC->AHBPCENR &= ~RCC_AHBPeriph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphClockCmd
+ *
+ * @brief   Enables or disables the High Speed APB (APB2) peripheral clock.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphClockCmd( uint32_t RCC_APB2Periph, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        RCC->APB2PCENR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PCENR &= ~RCC_APB2Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphClockCmd
+ *
+ * @brief   Enables or disables the Low Speed APB (APB1) peripheral clock.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphClockCmd( uint32_t RCC_APB1Periph, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        RCC->APB1PCENR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PCENR &= ~RCC_APB1Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphResetCmd
+ *
+ * @brief   Forces or releases High Speed APB (APB2) peripheral reset.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to reset.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_USART1.
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphResetCmd( uint32_t RCC_APB2Periph, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        RCC->APB2PRSTR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PRSTR &= ~RCC_APB2Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphResetCmd
+ *
+ * @brief   Forces or releases Low Speed APB (APB1) peripheral reset.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to reset.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphResetCmd( uint32_t RCC_APB1Periph, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        RCC->APB1PRSTR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PRSTR &= ~RCC_APB1Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_BackupResetCmd
+ *
+ * @brief   Forces or releases the Backup domain reset.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_BackupResetCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) BDCTLR_BDRST_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClockSecuritySystemCmd
+ *
+ * @brief   Enables or disables the Clock Security System.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ClockSecuritySystemCmd( FunctionalState NewState )
+{
+    *( __IO uint32_t * ) CTLR_CSSON_BB = ( uint32_t )NewState;
+}
+
+/*********************************************************************
+ * @fn      RCC_MCOConfig
+ *
+ * @brief   Selects the clock source to output on MCO pin.
+ *
+ * @param   RCC_MCO - specifies the clock source to output.
+ *            RCC_MCO_NoClock - No clock selected.
+ *            RCC_MCO_SYSCLK - System clock selected.
+ *            RCC_MCO_HSI - HSI oscillator clock selected.
+ *            RCC_MCO_HSE - HSE oscillator clock selected.
+ *            RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected.
+ *
+ * @return  none
+ */
+void RCC_MCOConfig( uint8_t RCC_MCO )
+{
+    *( __IO uint8_t * ) CFGR0_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RCC flag is set or not.
+ *
+ * @param   RCC_FLAG - specifies the flag to check.
+ *            RCC_FLAG_HSIRDY - HSI oscillator clock ready.
+ *            RCC_FLAG_HSERDY - HSE oscillator clock ready.
+ *            RCC_FLAG_PLLRDY - PLL clock ready.
+ *            RCC_FLAG_LSERDY - LSE oscillator clock ready.
+ *            RCC_FLAG_LSIRDY - LSI oscillator clock ready.
+ *            RCC_FLAG_PINRST - Pin reset.
+ *            RCC_FLAG_PORRST - POR/PDR reset.
+ *            RCC_FLAG_SFTRST - Software reset.
+ *            RCC_FLAG_IWDGRST - Independent Watchdog reset.
+ *            RCC_FLAG_WWDGRST - Window Watchdog reset.
+ *            RCC_FLAG_LPWRRST - Low Power reset.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus RCC_GetFlagStatus( uint8_t RCC_FLAG )
+{
+    uint32_t tmp = 0;
+    uint32_t statusreg = 0;
+
+    FlagStatus bitstatus = RESET;
+    tmp = RCC_FLAG >> 5;
+
+    if( tmp == 1 )
+    {
+        statusreg = RCC->CTLR;
+    }
+    else if( tmp == 2 )
+    {
+        statusreg = RCC->BDCTLR;
+    }
+    else
+    {
+        statusreg = RCC->RSTSCKR;
+    }
+
+    tmp = RCC_FLAG & FLAG_Mask;
+
+    if( ( statusreg & ( ( uint32_t )1 << tmp ) ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearFlag
+ *
+ * @brief   Clears the RCC reset flags.
+ *
+ * @return  none
+ */
+void RCC_ClearFlag( void )
+{
+    RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetITStatus
+ *
+ * @brief   Checks whether the specified RCC interrupt has occurred or not.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt source to check.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus RCC_GetITStatus( uint8_t RCC_IT )
+{
+    ITStatus bitstatus = RESET;
+
+    if( ( RCC->INTR & RCC_IT ) != ( uint32_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearITPendingBit
+ *
+ * @brief   Clears the RCC's interrupt pending bits.
+ *
+ * @param   RCC_IT - specifies the interrupt pending bit to clear.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  none
+ */
+void RCC_ClearITPendingBit( uint8_t RCC_IT )
+{
+    *( __IO uint8_t * ) INTR_BYTE3_ADDRESS = RCC_IT;
+}
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_rtc.c

@@ -0,0 +1,285 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_rtc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the RTC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ********************************************************************************/
+
+#include "ch32f10x_rtc.h"
+
+/* RTC_Private_Defines */
+#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /* RTC LSB Mask */
+#define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /* RTC Prescaler MSB Mask */
+
+
+/*********************************************************************
+ * @fn      RTC_ITConfig
+ *
+ * @brief   Enables or disables the specified RTC interrupts.
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
+ *            RTC_IT_OW - Overflow interrupt
+ *            RTC_IT_ALR - Alarm interrupt
+ *            RTC_IT_SEC - Second interrupt
+ *
+ * @return  NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
+ */
+void RTC_ITConfig( uint16_t RTC_IT, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        RTC->CTLRH |= RTC_IT;
+    }
+    else
+    {
+        RTC->CTLRH &= ( uint16_t )~RTC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_EnterConfigMode
+ *
+ * @brief   Enters the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_EnterConfigMode( void )
+{
+    RTC->CTLRL |= RTC_CTLRL_CNF;
+}
+
+
+/*********************************************************************
+ * @fn      RTC_ExitConfigMode
+ *
+ * @brief   Exits from the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_ExitConfigMode( void )
+{
+    RTC->CTLRL &= ( uint16_t )~( ( uint16_t )RTC_CTLRL_CNF );
+}
+
+
+/*********************************************************************
+ * @fn      RTC_GetCounter
+ *
+ * @brief   Gets the RTC counter value
+ *
+ * @return  RTC counter value
+ */
+uint32_t RTC_GetCounter( void )
+{
+    uint16_t high1 = 0, high2 = 0, low = 0;
+
+    high1 = RTC->CNTH;
+    low   = RTC->CNTL;
+    high2 = RTC->CNTH;
+
+    if( high1 != high2 )
+    {
+        return ( ( ( uint32_t ) high2 << 16 ) | RTC->CNTL );
+    }
+    else
+    {
+        return ( ( ( uint32_t ) high1 << 16 ) | low );
+    }
+}
+
+
+/*********************************************************************
+ * @fn      RTC_SetCounter
+ *
+ * @brief   Sets the RTC counter value.
+ *
+ * @param   CounterValue - RTC counter new value.
+ *
+ * @return  RTC counter value
+ */
+void RTC_SetCounter( uint32_t CounterValue )
+{
+    RTC_EnterConfigMode();
+    RTC->CNTH = CounterValue >> 16;
+    RTC->CNTL = ( CounterValue & RTC_LSB_MASK );
+    RTC_ExitConfigMode();
+}
+
+
+/*********************************************************************
+ * @fn      RTC_SetPrescaler
+ *
+ * @brief   Sets the RTC prescaler value
+ *
+ * @param   PrescalerValue - RTC prescaler new value
+ *
+ * @return  none
+ */
+void RTC_SetPrescaler( uint32_t PrescalerValue )
+{
+    RTC_EnterConfigMode();
+    RTC->PSCRH = ( PrescalerValue & PRLH_MSB_MASK ) >> 16;
+    RTC->PSCRL = ( PrescalerValue & RTC_LSB_MASK );
+    RTC_ExitConfigMode();
+}
+
+
+/*********************************************************************
+ * @fn      RTC_SetAlarm
+ *
+ * @brief   Sets the RTC alarm value
+ *
+ * @param   AlarmValue - RTC alarm new value
+ *
+ * @return  none
+ */
+void RTC_SetAlarm( uint32_t AlarmValue )
+{
+    RTC_EnterConfigMode();
+    RTC->ALRMH = AlarmValue >> 16;
+    RTC->ALRML = ( AlarmValue & RTC_LSB_MASK );
+    RTC_ExitConfigMode();
+}
+
+
+/*********************************************************************
+ * @fn      RTC_GetDivider
+ *
+ * @brief   Gets the RTC divider value
+ *
+ * @return  RTC Divider value
+ */
+uint32_t RTC_GetDivider( void )
+{
+    uint32_t tmp = 0x00;
+    tmp = ( ( uint32_t )RTC->DIVH & ( uint32_t )0x000F ) << 16;
+    tmp |= RTC->DIVL;
+    return tmp;
+}
+
+/*********************************************************************
+ * @fn      RTC_WaitForLastTask
+ *
+ * @brief   Waits until last write operation on RTC registers has finished
+ *
+ * @return  none
+ */
+void RTC_WaitForLastTask( void )
+{
+    while( ( RTC->CTLRL & RTC_FLAG_RTOFF ) == ( uint16_t )RESET )
+    {
+    }
+}
+
+
+/*********************************************************************
+ * @fn      RTC_WaitForSynchro
+ *
+ * @brief   Waits until the RTC registers are synchronized with RTC APB clock
+ *
+ * @return  none
+ */
+void RTC_WaitForSynchro( void )
+{
+    RTC->CTLRL &= ( uint16_t )~RTC_FLAG_RSF;
+    while( ( RTC->CTLRL & RTC_FLAG_RSF ) == ( uint16_t )RESET )
+    {
+    }
+}
+
+
+/*********************************************************************
+ * @fn      RTC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RTC flag is set or not
+ *
+ * @param   RTC_FLAG- specifies the flag to check
+ *            RTC_FLAG_RTOFF - RTC Operation OFF flag
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  The new state of RTC_FLAG (SET or RESET)
+ */
+FlagStatus RTC_GetFlagStatus( uint16_t RTC_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+    if( ( RTC->CTLRL & RTC_FLAG ) != ( uint16_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearFlag
+ *
+ * @brief   Clears the RTC's pending flags
+ *
+ * @param   RTC_FLAG - specifies the flag to clear
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  none
+ */
+void RTC_ClearFlag( uint16_t RTC_FLAG )
+{
+    RTC->CTLRL &= ( uint16_t )~RTC_FLAG;
+}
+
+
+/*********************************************************************
+ * @fn      RTC_GetITStatus
+ *
+ * @brief   Checks whether the specified RTC interrupt has occurred or not
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to check
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  The new state of the RTC_IT (SET or RESET)
+ */
+ITStatus RTC_GetITStatus( uint16_t RTC_IT )
+{
+    ITStatus bitstatus = RESET;
+
+    bitstatus = ( ITStatus )( RTC->CTLRL & RTC_IT );
+    if( ( ( RTC->CTLRH & RTC_IT ) != ( uint16_t )RESET ) && ( bitstatus != ( uint16_t )RESET ) )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearITPendingBit
+ *
+ * @brief   Clears the RTC's interrupt pending bits
+ *
+ * @param   RTC_IT - specifies the interrupt pending bit to clear
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  none
+ */
+void RTC_ClearITPendingBit( uint16_t RTC_IT )
+{
+    RTC->CTLRL &= ( uint16_t )~RTC_IT;
+}
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_spi.c

@@ -0,0 +1,654 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_spi.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the SPI firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32f10x_spi.h"
+#include "ch32f10x_rcc.h"
+
+/* SPI SPE mask */
+#define CTLR1_SPE_Set          ((uint16_t)0x0040)
+#define CTLR1_SPE_Reset        ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set       ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset     ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CTLR1_CRCNext_Set      ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTLR1_CRCEN_Set        ((uint16_t)0x2000)
+#define CTLR1_CRCEN_Reset      ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTLR2_SSOE_Set         ((uint16_t)0x0004)
+#define CTLR2_SSOE_Reset       ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTLR1_CLEAR_Mask       ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask     ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select        ((uint16_t)0xF7FF)
+#define I2S_Mode_Select        ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC         ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC         ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK           ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK           ((uint32_t)(0x000000F0))
+
+/*********************************************************************
+ * @fn      SPI_I2S_DeInit
+ *
+ * @brief   Deinitializes the SPIx peripheral registers to their default
+ *        reset values (Affects also the I2Ss).
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_I2S_DeInit( SPI_TypeDef *SPIx )
+{
+    if( SPIx == SPI1 )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_SPI1, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_SPI1, DISABLE );
+    }
+    else if( SPIx == SPI2 )
+    {
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_SPI2, ENABLE );
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_SPI2, DISABLE );
+    }
+    else
+    {
+        if( SPIx == SPI3 )
+        {
+            RCC_APB1PeriphResetCmd( RCC_APB1Periph_SPI3, ENABLE );
+            RCC_APB1PeriphResetCmd( RCC_APB1Periph_SPI3, DISABLE );
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the SPI_InitStruct.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_Init( SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct )
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = SPIx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= ( uint16_t )( ( uint32_t )SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                            SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+                            SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+                            SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit );
+
+    SPIx->CTLR1 = tmpreg;
+    SPIx->I2SCFGR &= SPI_Mode_Select;
+    SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/*********************************************************************
+ * @fn      I2S_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the I2S_InitStruct.
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *        (configured in I2S mode).
+ *          I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral
+ *        configured in I2S mode.
+ * @return  none
+ */
+void I2S_Init( SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct )
+{
+    uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+    uint32_t tmp = 0;
+    RCC_ClocksTypeDef RCC_Clocks;
+    uint32_t sourceclock = 0;
+
+    SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+    SPIx->I2SPR = 0x0002;
+    tmpreg = SPIx->I2SCFGR;
+
+    if( I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default )
+    {
+        i2sodd = ( uint16_t )0;
+        i2sdiv = ( uint16_t )2;
+    }
+    else
+    {
+        if( I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b )
+        {
+            packetlength = 1;
+        }
+        else
+        {
+            packetlength = 2;
+        }
+
+        if( ( ( uint32_t )SPIx ) == SPI2_BASE )
+        {
+            tmp = I2S2_CLOCK_SRC;
+        }
+        else
+        {
+            tmp = I2S3_CLOCK_SRC;
+        }
+
+        RCC_GetClocksFreq( &RCC_Clocks );
+
+        sourceclock = RCC_Clocks.SYSCLK_Frequency;
+
+        if( I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable )
+        {
+            tmp = ( uint16_t )( ( ( ( ( sourceclock / 256 ) * 10 ) / I2S_InitStruct->I2S_AudioFreq ) ) + 5 );
+        }
+        else
+        {
+            tmp = ( uint16_t )( ( ( ( ( sourceclock / ( 32 * packetlength ) ) * 10 ) / I2S_InitStruct->I2S_AudioFreq ) ) + 5 );
+        }
+
+        tmp = tmp / 10;
+        i2sodd = ( uint16_t )( tmp & ( uint16_t )0x0001 );
+        i2sdiv = ( uint16_t )( ( tmp - i2sodd ) / 2 );
+        i2sodd = ( uint16_t )( i2sodd << 8 );
+    }
+
+    if( ( i2sdiv < 2 ) || ( i2sdiv > 0xFF ) )
+    {
+        i2sdiv = 2;
+        i2sodd = 0;
+    }
+
+    SPIx->I2SPR = ( uint16_t )( i2sdiv | ( uint16_t )( i2sodd | ( uint16_t )I2S_InitStruct->I2S_MCLKOutput ) );
+    tmpreg |= ( uint16_t )( I2S_Mode_Select | ( uint16_t )( I2S_InitStruct->I2S_Mode | \
+                            ( uint16_t )( I2S_InitStruct->I2S_Standard | ( uint16_t )( I2S_InitStruct->I2S_DataFormat | \
+                                          ( uint16_t )I2S_InitStruct->I2S_CPOL ) ) ) );
+    SPIx->I2SCFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_StructInit
+ *
+ * @brief   Fills each SPI_InitStruct member with its default value.
+ *
+ * @param   SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void SPI_StructInit( SPI_InitTypeDef *SPI_InitStruct )
+{
+    SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+    SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+    SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+    SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+    SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+    SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/*********************************************************************
+ * @fn      I2S_StructInit
+ *
+ * @brief   Fills each I2S_InitStruct member with its default value.
+ *
+ * @param   I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2S_StructInit( I2S_InitTypeDef *I2S_InitStruct )
+{
+    I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+    I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+    I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+    I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+    I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+    I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/*********************************************************************
+ * @fn      SPI_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_Cmd( SPI_TypeDef *SPIx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        SPIx->CTLR1 |= CTLR1_SPE_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_SPE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2S_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral (in I2S mode).
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2S_Cmd( SPI_TypeDef *SPIx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+    }
+    else
+    {
+        SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ITConfig
+ *
+ * @brief   Enables or disables the specified SPI/I2S interrupts.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
+ *        enabled or disabled.
+ *            SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
+ *            SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
+ *            SPI_I2S_IT_ERR - Error interrupt mask.
+ *          NewState: ENABLE or DISABLE.
+ * @return  none
+ */
+void SPI_I2S_ITConfig( SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState )
+{
+    uint16_t itpos = 0, itmask = 0 ;
+
+    itpos = SPI_I2S_IT >> 4;
+    itmask = ( uint16_t )1 << ( uint16_t )itpos;
+
+    if( NewState != DISABLE )
+    {
+        SPIx->CTLR2 |= itmask;
+    }
+    else
+    {
+        SPIx->CTLR2 &= ( uint16_t )~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_DMACmd
+ *
+ * @brief   Enables or disables the SPIx/I2Sx DMA interface.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
+ *        be enabled or disabled.
+ *            SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
+ *            SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_I2S_DMACmd( SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        SPIx->CTLR2 |= SPI_I2S_DMAReq;
+    }
+    else
+    {
+        SPIx->CTLR2 &= ( uint16_t )~SPI_I2S_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_SendData
+ *
+ * @brief   Transmits a Data through the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  none
+ */
+void SPI_I2S_SendData( SPI_TypeDef *SPIx, uint16_t Data )
+{
+    SPIx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  SPIx->DATAR - The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData( SPI_TypeDef *SPIx )
+{
+    return SPIx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      SPI_NSSInternalSoftwareConfig
+ *
+ * @brief   Configures internally by software the NSS pin for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_NSSInternalSoft -
+ *            SPI_NSSInternalSoft_Set - Set NSS pin internally.
+ *            SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
+ *
+ * @return  none
+ */
+void SPI_NSSInternalSoftwareConfig( SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft )
+{
+    if( SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset )
+    {
+        SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_SSOutputCmd
+ *
+ * @brief   Enables or disables the SS output for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx SS output.
+ *
+ * @return  none
+ */
+void SPI_SSOutputCmd( SPI_TypeDef *SPIx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        SPIx->CTLR2 |= CTLR2_SSOE_Set;
+    }
+    else
+    {
+        SPIx->CTLR2 &= CTLR2_SSOE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_DataSizeConfig
+ *
+ * @brief   Configures the data size for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_DataSize - specifies the SPI data size.
+ *            SPI_DataSize_16b - Set data frame format to 16bit.
+ *            SPI_DataSize_8b - Set data frame format to 8bit.
+ *
+ * @return  none
+ */
+void SPI_DataSizeConfig( SPI_TypeDef *SPIx, uint16_t SPI_DataSize )
+{
+    SPIx->CTLR1 &= ( uint16_t )~SPI_DataSize_16b;
+    SPIx->CTLR1 |= SPI_DataSize;
+}
+
+/*********************************************************************
+ * @fn      SPI_TransmitCRC
+ *
+ * @brief   Transmit the SPIx CRC value.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_TransmitCRC( SPI_TypeDef *SPIx )
+{
+    SPIx->CTLR1 |= CTLR1_CRCNext_Set;
+}
+
+/*********************************************************************
+ * @fn      SPI_CalculateCRC
+ *
+ * @brief   Enables or disables the CRC value calculation of the transferred bytes.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx CRC value calculation.
+ *
+ * @return  none
+ */
+void SPI_CalculateCRC( SPI_TypeDef *SPIx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        SPIx->CTLR1 |= CTLR1_CRCEN_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRC
+ *
+ * @brief   Returns the transmit or the receive CRC register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_CRC - specifies the CRC register to be read.
+ *            SPI_CRC_Tx - Selects Tx CRC register.
+ *            SPI_CRC_Rx - Selects Rx CRC register.
+ *
+ * @return  crcreg: The selected CRC register value.
+ */
+uint16_t SPI_GetCRC( SPI_TypeDef *SPIx, uint8_t SPI_CRC )
+{
+    uint16_t crcreg = 0;
+
+    if( SPI_CRC != SPI_CRC_Rx )
+    {
+        crcreg = SPIx->TCRCR;
+    }
+    else
+    {
+        crcreg = SPIx->RCRCR;
+    }
+
+    return crcreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRCPolynomial
+ *
+ * @brief   Returns the CRC Polynomial register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  SPIx->CRCR - The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial( SPI_TypeDef *SPIx )
+{
+    return SPIx->CRCR;
+}
+
+/*********************************************************************
+ * @fn      SPI_BiDirectionalLineConfig
+ *
+ * @brief   Selects the data transfer direction in bi-directional mode
+ *      for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_Direction - specifies the data transfer direction in
+ *        bi-directional mode.
+ *            SPI_Direction_Tx - Selects Tx transmission direction.
+ *            SPI_Direction_Rx - Selects Rx receive direction.
+ *
+ * @return  none
+ */
+void SPI_BiDirectionalLineConfig( SPI_TypeDef *SPIx, uint16_t SPI_Direction )
+{
+    if( SPI_Direction == SPI_Direction_Tx )
+    {
+        SPIx->CTLR1 |= SPI_Direction_Tx;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_Direction_Rx;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetFlagStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S flag is set or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
+ *            SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
+ *            SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
+ *            SPI_I2S_FLAG_BSY - Busy flag.
+ *            SPI_I2S_FLAG_OVR - Overrun flag.
+ *            SPI_FLAG_MODF - Mode Fault flag.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *            I2S_FLAG_UDR - Underrun Error flag.
+ *            I2S_FLAG_CHSIDE - Channel Side flag.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus SPI_I2S_GetFlagStatus( SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+
+    if( ( SPIx->STATR & SPI_I2S_FLAG ) != ( uint16_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearFlag
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) flag.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI flag to clear.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+void SPI_I2S_ClearFlag( SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG )
+{
+    SPIx->STATR = ( uint16_t )~SPI_I2S_FLAG;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetITStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S interrupt has occurred or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
+ *            SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
+ *            SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
+ *            SPI_I2S_IT_OVR - Overrun interrupt.
+ *            SPI_IT_MODF - Mode Fault interrupt.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *            I2S_IT_UDR - Underrun Error interrupt.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+ITStatus SPI_I2S_GetITStatus( SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT )
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+    itpos = 0x01 << ( SPI_I2S_IT & 0x0F );
+    itmask = SPI_I2S_IT >> 4;
+    itmask = 0x01 << itmask;
+    enablestatus = ( SPIx->CTLR2 & itmask ) ;
+
+    if( ( ( SPIx->STATR & itpos ) != ( uint16_t )RESET ) && enablestatus )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearITPendingBit
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *          SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *
+ * @return  none
+ */
+void SPI_I2S_ClearITPendingBit( SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT )
+{
+    uint16_t itpos = 0;
+
+    itpos = 0x01 << ( SPI_I2S_IT & 0x0F );
+    SPIx->STATR = ( uint16_t )~itpos;
+}
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_usart.c

@@ -0,0 +1,825 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_usart.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the USART firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_usart.h"
+#include "ch32f10x_rcc.h"
+
+/* USART_Private_Defines */
+#define CTLR1_UE_Set                ((uint16_t)0x2000)  /* USART Enable Mask */
+#define CTLR1_UE_Reset              ((uint16_t)0xDFFF)  /* USART Disable Mask */
+
+#define CTLR1_WAKE_Mask             ((uint16_t)0xF7FF)  /* USART WakeUp Method Mask */
+
+#define CTLR1_RWU_Set               ((uint16_t)0x0002)  /* USART mute mode Enable Mask */
+#define CTLR1_RWU_Reset             ((uint16_t)0xFFFD)  /* USART mute mode Enable Mask */
+#define CTLR1_SBK_Set               ((uint16_t)0x0001)  /* USART Break Character send Mask */
+#define CTLR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /* USART CR1 Mask */
+#define CTLR2_Address_Mask          ((uint16_t)0xFFF0)  /* USART address Mask */
+
+#define CTLR2_LINEN_Set             ((uint16_t)0x4000)  /* USART LIN Enable Mask */
+#define CTLR2_LINEN_Reset           ((uint16_t)0xBFFF)  /* USART LIN Disable Mask */
+
+#define CTLR2_LBDL_Mask             ((uint16_t)0xFFDF)  /* USART LIN Break detection Mask */
+#define CTLR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /* USART CR2 STOP Bits Mask */
+#define CTLR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /* USART CR2 Clock Mask */
+
+#define CTLR3_SCEN_Set              ((uint16_t)0x0020)  /* USART SC Enable Mask */
+#define CTLR3_SCEN_Reset            ((uint16_t)0xFFDF)  /* USART SC Disable Mask */
+
+#define CTLR3_NACK_Set              ((uint16_t)0x0010)  /* USART SC NACK Enable Mask */
+#define CTLR3_NACK_Reset            ((uint16_t)0xFFEF)  /* USART SC NACK Disable Mask */
+
+#define CTLR3_HDSEL_Set             ((uint16_t)0x0008)  /* USART Half-Duplex Enable Mask */
+#define CTLR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /* USART Half-Duplex Disable Mask */
+
+#define CTLR3_IRLP_Mask             ((uint16_t)0xFFFB)  /* USART IrDA LowPower mode Mask */
+#define CTLR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /* USART CR3 Mask */
+
+#define CTLR3_IREN_Set              ((uint16_t)0x0002)  /* USART IrDA Enable Mask */
+#define CTLR3_IREN_Reset            ((uint16_t)0xFFFD)  /* USART IrDA Disable Mask */
+#define GPR_LSB_Mask                ((uint16_t)0x00FF)  /* Guard Time Register LSB Mask */
+#define GPR_MSB_Mask                ((uint16_t)0xFF00)  /* Guard Time Register MSB Mask */
+#define IT_Mask                     ((uint16_t)0x001F)  /* USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CTLR1_OVER8_Set             ((uint16_t)0x8000)  /* USART OVER8 mode Enable Mask */
+#define CTLR1_OVER8_Reset           ((uint16_t)0x7FFF)  /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CTLR3_ONEBITE_Set           ((uint16_t)0x0800)  /* USART ONEBITE mode Enable Mask */
+#define CTLR3_ONEBITE_Reset         ((uint16_t)0xF7FF)  /* USART ONEBITE mode Disable Mask */
+
+
+/*********************************************************************
+ * @fn      USART_DeInit
+ *
+ * @brief   Deinitializes the USARTx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *
+ * @return  none
+ */
+void USART_DeInit( USART_TypeDef *USARTx )
+{
+    if( USARTx == USART1 )
+    {
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_USART1, ENABLE );
+        RCC_APB2PeriphResetCmd( RCC_APB2Periph_USART1, DISABLE );
+    }
+    else if( USARTx == USART2 )
+    {
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_USART2, ENABLE );
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_USART2, DISABLE );
+    }
+    else if( USARTx == USART3 )
+    {
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_USART3, ENABLE );
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_USART3, DISABLE );
+    }
+    else if( USARTx == UART4 )
+    {
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_UART4, ENABLE );
+        RCC_APB1PeriphResetCmd( RCC_APB1Periph_UART4, DISABLE );
+    }
+    else
+    {
+        if( USARTx == UART5 )
+        {
+            RCC_APB1PeriphResetCmd( RCC_APB1Periph_UART5, ENABLE );
+            RCC_APB1PeriphResetCmd( RCC_APB1Periph_UART5, DISABLE );
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_Init
+ *
+ * @brief   Initializes the USARTx peripheral according to the specified
+ *        parameters in the USART_InitStruct.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *          USART_InitStruct - pointer to a USART_InitTypeDef structure
+ *        that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_Init( USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct )
+{
+    uint32_t tmpreg = 0x00, apbclock = 0x00;
+    uint32_t integerdivider = 0x00;
+    uint32_t fractionaldivider = 0x00;
+    uint32_t usartxbase = 0;
+    RCC_ClocksTypeDef RCC_ClocksStatus;
+
+    if( USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None )
+    {
+    }
+
+    usartxbase = ( uint32_t )USARTx;
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_STOP_CLEAR_Mask;
+    tmpreg |= ( uint32_t )USART_InitStruct->USART_StopBits;
+
+    USARTx->CTLR2 = ( uint16_t )tmpreg;
+    tmpreg = USARTx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= ( uint32_t )USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+              USART_InitStruct->USART_Mode;
+    USARTx->CTLR1 = ( uint16_t )tmpreg;
+
+    tmpreg = USARTx->CTLR3;
+    tmpreg &= CTLR3_CLEAR_Mask;
+    tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+    USARTx->CTLR3 = ( uint16_t )tmpreg;
+
+    RCC_GetClocksFreq( &RCC_ClocksStatus );
+
+    if( usartxbase == USART1_BASE )
+    {
+        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+    }
+    else
+    {
+        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+    }
+
+    if( ( USARTx->CTLR1 & CTLR1_OVER8_Set ) != 0 )
+    {
+        integerdivider = ( ( 25 * apbclock ) / ( 2 * ( USART_InitStruct->USART_BaudRate ) ) );
+    }
+    else
+    {
+        integerdivider = ( ( 25 * apbclock ) / ( 4 * ( USART_InitStruct->USART_BaudRate ) ) );
+    }
+    tmpreg = ( integerdivider / 100 ) << 4;
+
+    fractionaldivider = integerdivider - ( 100 * ( tmpreg >> 4 ) );
+
+    if( ( USARTx->CTLR1 & CTLR1_OVER8_Set ) != 0 )
+    {
+        tmpreg |= ( ( ( ( fractionaldivider * 8 ) + 50 ) / 100 ) ) & ( ( uint8_t )0x07 );
+    }
+    else
+    {
+        tmpreg |= ( ( ( ( fractionaldivider * 16 ) + 50 ) / 100 ) ) & ( ( uint8_t )0x0F );
+    }
+
+    USARTx->BRR = ( uint16_t )tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_StructInit
+ *
+ * @brief   Fills each USART_InitStruct member with its default value.
+ *
+ * @param   USART_InitStruct: pointer to a USART_InitTypeDef structure
+ *       which will be initialized.
+ *
+ * @return  none
+ */
+void USART_StructInit( USART_InitTypeDef *USART_InitStruct )
+{
+    USART_InitStruct->USART_BaudRate = 9600;
+    USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+    USART_InitStruct->USART_StopBits = USART_StopBits_1;
+    USART_InitStruct->USART_Parity = USART_Parity_No ;
+    USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockInit
+ *
+ * @brief   Initializes the USARTx peripheral Clock according to the
+ *        specified parameters in the USART_ClockInitStruct .
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_ClockInit( USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct )
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
+    tmpreg |= ( uint32_t )USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+              USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+    USARTx->CTLR2 = ( uint16_t )tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockStructInit
+ *
+ * @brief   Fills each USART_ClockStructInit member with its default value.
+ *
+ * @param   USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void USART_ClockStructInit( USART_ClockInitTypeDef *USART_ClockInitStruct )
+{
+    USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+    USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+    USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+    USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/*********************************************************************
+ * @fn      USART_Cmd
+ *
+ * @brief   Enables or disables the specified USART peripheral.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_Cmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR1 |= CTLR1_UE_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_UE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_ITConfig
+ *
+ * @brief   Enables or disables the specified USART interrupts.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt sources to be enabled or disabled.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Transmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *            USART_IT_ERR - Error interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ITConfig( USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState )
+{
+    uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+    uint32_t usartxbase = 0x00;
+
+    if( USART_IT == USART_IT_CTS )
+    {
+    }
+
+    usartxbase = ( uint32_t )USARTx;
+    usartreg = ( ( ( uint8_t )USART_IT ) >> 0x05 );
+    itpos = USART_IT & IT_Mask;
+    itmask = ( ( ( uint32_t )0x01 ) << itpos );
+
+    if( usartreg == 0x01 )
+    {
+        usartxbase += 0x0C;
+    }
+    else if( usartreg == 0x02 )
+    {
+        usartxbase += 0x10;
+    }
+    else
+    {
+        usartxbase += 0x14;
+    }
+
+    if( NewState != DISABLE )
+    {
+        *( __IO uint32_t * )usartxbase  |= itmask;
+    }
+    else
+    {
+        *( __IO uint32_t * )usartxbase &= ~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_DMACmd
+ *
+ * @brief   Enables or disables the USART DMA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_DMAReq - specifies the DMA request.
+ *            USART_DMAReq_Tx - USART DMA transmit request.
+ *            USART_DMAReq_Rx - USART DMA receive request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_DMACmd( USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR3 |= USART_DMAReq;
+    }
+    else
+    {
+        USARTx->CTLR3 &= ( uint16_t )~USART_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SetAddress
+ *
+ * @brief   Sets the address of the USART node.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Address - Indicates the address of the USART node.
+ *
+ * @return  none
+ */
+void USART_SetAddress( USART_TypeDef *USARTx, uint8_t USART_Address )
+{
+    USARTx->CTLR2 &= CTLR2_Address_Mask;
+    USARTx->CTLR2 |= USART_Address;
+}
+
+/*********************************************************************
+ * @fn      USART_WakeUpConfig
+ *
+ * @brief   Selects the USART WakeUp method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_WakeUp - specifies the USART wakeup method.
+ *            USART_WakeUp_IdleLine - WakeUp by an idle line detection.
+ *            USART_WakeUp_AddressMark - WakeUp by an address mark.
+ *
+ * @return  none
+ */
+void USART_WakeUpConfig( USART_TypeDef *USARTx, uint16_t USART_WakeUp )
+{
+    USARTx->CTLR1 &= CTLR1_WAKE_Mask;
+    USARTx->CTLR1 |= USART_WakeUp;
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiverWakeUpCmd
+ *
+ * @brief   Determines if the USART is in mute mode or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ReceiverWakeUpCmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR1 |= CTLR1_RWU_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_RWU_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_LINBreakDetectLengthConfig
+ *
+ * @brief   Sets the USART LIN Break detection length.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_LINBreakDetectLength - specifies the LIN break detection length.
+ *            USART_LINBreakDetectLength_10b - 10-bit break detection.
+ *            USART_LINBreakDetectLength_11b - 11-bit break detection.
+ *
+ * @return  none
+ */
+void USART_LINBreakDetectLengthConfig( USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength )
+{
+    USARTx->CTLR2 &= CTLR2_LBDL_Mask;
+    USARTx->CTLR2 |= USART_LINBreakDetectLength;
+}
+
+/*********************************************************************
+ * @fn      USART_LINCmd
+ *
+ * @brief   Enables or disables the USART LIN mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_LINCmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR2 |= CTLR2_LINEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR2 &= CTLR2_LINEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SendData
+ *
+ * @brief   Transmits single data through the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          Data - the data to transmit.
+ *
+ * @return  none
+ */
+void USART_SendData( USART_TypeDef *USARTx, uint16_t Data )
+{
+    USARTx->DATAR = ( Data & ( uint16_t )0x01FF );
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  The received data.
+ */
+uint16_t USART_ReceiveData( USART_TypeDef *USARTx )
+{
+    return ( uint16_t )( USARTx->DATAR & ( uint16_t )0x01FF );
+}
+
+/*********************************************************************
+ * @fn      USART_SendBreak
+ *
+ * @brief   Transmits break characters.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  none
+ */
+void USART_SendBreak( USART_TypeDef *USARTx )
+{
+    USARTx->CTLR1 |= CTLR1_SBK_Set;
+}
+
+/*********************************************************************
+ * @fn      USART_SetGuardTime
+ *
+ * @brief   Sets the specified USART guard time.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_GuardTime - specifies the guard time.
+ *
+ * @return  none
+ */
+void USART_SetGuardTime( USART_TypeDef *USARTx, uint8_t USART_GuardTime )
+{
+    USARTx->GPR &= GPR_LSB_Mask;
+    USARTx->GPR |= ( uint16_t )( ( uint16_t )USART_GuardTime << 0x08 );
+}
+
+/*********************************************************************
+ * @fn      USART_SetPrescaler
+ *
+ * @brief   Sets the system clock prescaler.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Prescaler - specifies the prescaler clock.
+ *
+ * @return  none
+ */
+void USART_SetPrescaler( USART_TypeDef *USARTx, uint8_t USART_Prescaler )
+{
+    USARTx->GPR &= GPR_MSB_Mask;
+    USARTx->GPR |= USART_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardCmd
+ *
+ * @brief   Enables or disables the USART Smart Card mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardCmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR3 |= CTLR3_SCEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_SCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardNACKCmd
+ *
+ * @brief   Enables or disables NACK transmission.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardNACKCmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR3 |= CTLR3_NACK_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_NACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_HalfDuplexCmd
+ *
+ * @brief   Enables or disables the USART Half Duplex communication.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *                  NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_HalfDuplexCmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR3 |= CTLR3_HDSEL_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OverSampling8Cmd
+ *
+ * @brief   Enables or disables the USART's 8x oversampling mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OverSampling8Cmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR1 |= CTLR1_OVER8_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_OVER8_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OneBitMethodCmd
+ *
+ * @brief   Enables or disables the USART's one bit sampling method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OneBitMethodCmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_IrDAConfig
+ *
+ * @brief   Configures the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IrDAMode - specifies the IrDA mode.
+ *            USART_IrDAMode_LowPower.
+ *            USART_IrDAMode_Normal.
+ *
+ * @return  none
+ */
+void USART_IrDAConfig( USART_TypeDef *USARTx, uint16_t USART_IrDAMode )
+{
+    USARTx->CTLR3 &= CTLR3_IRLP_Mask;
+    USARTx->CTLR3 |= USART_IrDAMode;
+}
+
+/*********************************************************************
+ * @fn      USART_IrDACmd
+ *
+ * @brief   Enables or disables the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_IrDACmd( USART_TypeDef *USARTx, FunctionalState NewState )
+{
+    if( NewState != DISABLE )
+    {
+        USARTx->CTLR3 |= CTLR3_IREN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_IREN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_GetFlagStatus
+ *
+ * @brief   Checks whether the specified USART flag is set or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to check.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TXE - Transmit data register empty flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *            USART_FLAG_IDLE - Idle Line detection flag.
+ *            USART_FLAG_ORE - OverRun Error flag.
+ *            USART_FLAG_NE - Noise Error flag.
+ *            USART_FLAG_FE - Framing Error flag.
+ *            USART_FLAG_PE - Parity Error flag.
+ *
+ * @return  bitstatus: SET or RESET
+ */
+FlagStatus USART_GetFlagStatus( USART_TypeDef *USARTx, uint16_t USART_FLAG )
+{
+    FlagStatus bitstatus = RESET;
+
+    if( USART_FLAG == USART_FLAG_CTS )
+    {
+    }
+
+    if( ( USARTx->STATR & USART_FLAG ) != ( uint16_t )RESET )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearFlag
+ *
+ * @brief   Clears the USARTx's pending flags.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to clear.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *
+ * @return  none
+ */
+void USART_ClearFlag( USART_TypeDef *USARTx, uint16_t USART_FLAG )
+{
+    if( ( USART_FLAG & USART_FLAG_CTS ) == USART_FLAG_CTS )
+    {
+    }
+
+    USARTx->STATR = ( uint16_t )~USART_FLAG;
+}
+
+/*********************************************************************
+ * @fn      USART_GetITStatus
+ *
+ * @brief   Checks whether the specified USART interrupt has occurred or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt source to check.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Tansmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
+ *            USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
+ *            USART_IT_NE - Noise Error interrupt.
+ *            USART_IT_FE - Framing Error interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *
+ * @return  bitstatus: SET or RESET.
+ */
+ITStatus USART_GetITStatus( USART_TypeDef *USARTx, uint16_t USART_IT )
+{
+    uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+    ITStatus bitstatus = RESET;
+
+    if( USART_IT == USART_IT_CTS )
+    {
+    }
+
+    usartreg = ( ( ( uint8_t )USART_IT ) >> 0x05 );
+    itmask = USART_IT & IT_Mask;
+    itmask = ( uint32_t )0x01 << itmask;
+
+    if( usartreg == 0x01 )
+    {
+        itmask &= USARTx->CTLR1;
+    }
+    else if( usartreg == 0x02 )
+    {
+        itmask &= USARTx->CTLR2;
+    }
+    else
+    {
+        itmask &= USARTx->CTLR3;
+    }
+
+    bitpos = USART_IT >> 0x08;
+    bitpos = ( uint32_t )0x01 << bitpos;
+    bitpos &= USARTx->STATR;
+
+    if( ( itmask != ( uint16_t )RESET ) && ( bitpos != ( uint16_t )RESET ) )
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearITPendingBit
+ *
+ * @brief   Clears the USARTx's interrupt pending bits.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the interrupt pending bit to clear.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *
+ * @return  none
+ */
+void USART_ClearITPendingBit( USART_TypeDef *USARTx, uint16_t USART_IT )
+{
+    uint16_t bitpos = 0x00, itmask = 0x00;
+
+    if( USART_IT == USART_IT_CTS )
+    {
+
+    }
+
+    bitpos = USART_IT >> 0x08;
+    itmask = ( ( uint16_t )0x01 << ( uint16_t )bitpos );
+    USARTx->STATR = ( uint16_t )~itmask;
+}
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_usb.c

@@ -0,0 +1,114 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_usb.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the USB firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_usb.h"
+#include "ch32f10x_rcc.h"
+#include "debug.h"
+/******************************** USB DEVICE **********************************/
+
+/* Endpoint address */
+PUINT8  pEP0_RAM_Addr;
+PUINT8  pEP1_RAM_Addr;
+PUINT8  pEP2_RAM_Addr;
+PUINT8  pEP3_RAM_Addr;
+
+/*********************************************************************
+ * @fn      USB_DeviceInit
+ *
+ * @brief   Initializes USB device.
+ *
+ * @return  none
+ */
+void USB_DeviceInit( void )
+{
+    R8_USB_CTRL = 0x00;
+
+    R8_UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN;
+    R8_UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN;
+
+    R16_UEP0_DMA = ( UINT16 )( UINT32 )pEP0_RAM_Addr;
+    R16_UEP1_DMA = ( UINT16 )( UINT32 )pEP1_RAM_Addr;
+    R16_UEP2_DMA = ( UINT16 )( UINT32 )pEP2_RAM_Addr;
+    R16_UEP3_DMA = ( UINT16 )( UINT32 )pEP3_RAM_Addr;
+
+    R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+
+    R8_USB_INT_FG = 0xFF;
+    R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER;
+
+    R8_USB_DEV_AD = 0x00;
+    R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN;
+    R8_UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN;
+}
+
+/*********************************************************************
+ * @fn      DevEP1_IN_Deal
+ *
+ * @brief   Device endpoint1 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP1_IN_Deal( UINT8 l )
+{
+    R8_UEP1_T_LEN = l;
+    R8_UEP1_CTRL = ( R8_UEP1_CTRL & ~MASK_UEP_T_RES ) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP2_IN_Deal
+ *
+ * @brief   Device endpoint2 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP2_IN_Deal( UINT8 l )
+{
+    R8_UEP2_T_LEN = l;
+    R8_UEP2_CTRL = ( R8_UEP2_CTRL & ~MASK_UEP_T_RES ) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP3_IN_Deal
+ *
+ * @brief   Device endpoint3 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP3_IN_Deal( UINT8 l )
+{
+    R8_UEP3_T_LEN = l;
+    R8_UEP3_CTRL = ( R8_UEP3_CTRL & ~MASK_UEP_T_RES ) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP4_IN_Deal
+ *
+ * @brief   Device endpoint4 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP4_IN_Deal( UINT8 l )
+{
+    R8_UEP4_T_LEN = l;
+    R8_UEP4_CTRL = ( R8_UEP4_CTRL & ~MASK_UEP_T_RES ) | UEP_T_RES_ACK;
+}
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_usb_host.c

@@ -0,0 +1,879 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_usb_host.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the USB firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32f10x_usb_host.h"
+#include "debug.h"
+
+
+/******************************** HOST DEVICE **********************************/
+UINT8  UsbDevEndp0Size;
+UINT8  FoundNewDev;
+_RootHubDev   ThisUsbDev;
+
+PUINT8  pHOST_RX_RAM_Addr;
+PUINT8  pHOST_TX_RAM_Addr;
+extern UINT8 Com_Buffer[128];
+
+__align( 4 ) const UINT8  SetupGetDevDescr[] = { USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_DEVICE, 0x00, 0x00, sizeof( USB_DEV_DESCR ), 0x00 };
+
+__align( 4 ) const UINT8  SetupGetCfgDescr[] = { USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_CONFIG, 0x00, 0x00, 0x04, 0x00 };
+
+__align( 4 ) const UINT8  SetupSetUsbAddr[] = { USB_REQ_TYP_OUT, USB_SET_ADDRESS, USB_DEVICE_ADDR, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+__align( 4 ) const UINT8  SetupSetUsbConfig[] = { USB_REQ_TYP_OUT, USB_SET_CONFIGURATION, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+__align( 4 ) const UINT8  SetupSetUsbInterface[] = { USB_REQ_RECIP_INTERF, USB_SET_INTERFACE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+__align( 4 ) const UINT8  SetupClrEndpStall[] = { USB_REQ_TYP_OUT | USB_REQ_RECIP_ENDP, USB_CLEAR_FEATURE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+
+/*********************************************************************
+ * @fn      DisableRootHubPort( )
+ *
+ * @brief  Disable root hub
+ *
+ * @return  none
+ */
+void DisableRootHubPort( void )
+{
+#ifdef	FOR_ROOT_UDISK_ONLY
+    CH103DiskStatus = DISK_DISCONNECT;
+
+#endif
+
+#ifndef	DISK_BASE_BUF_LEN
+    ThisUsbDev.DeviceStatus = ROOT_DEV_DISCONNECT;
+    ThisUsbDev.DeviceAddress = 0x00;
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      AnalyzeRootHub
+ *
+ * @brief  Analyze root hub state.
+ *
+ * @return  Error
+ */
+UINT8 AnalyzeRootHub( void )
+{
+    UINT8	s;
+
+    s = ERR_SUCCESS;
+
+    if( R8_USB_MIS_ST & RB_UMS_DEV_ATTACH )
+    {
+
+#ifdef DISK_BASE_BUF_LEN
+        if( CH103DiskStatus == DISK_DISCONNECT
+
+#else
+        if( ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT
+
+#endif
+            || ( R8_UHOST_CTRL & RB_UH_PORT_EN ) == 0x00 )
+        {
+            DisableRootHubPort( );
+
+#ifdef DISK_BASE_BUF_LEN
+            CH103DiskStatus = DISK_CONNECT;
+
+#else
+            ThisUsbDev.DeviceSpeed = R8_USB_MIS_ST & RB_UMS_DM_LEVEL ? 0 : 1;
+            ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED;
+
+#endif
+            s = ERR_USB_CONNECT;
+        }
+    }
+
+#ifdef DISK_BASE_BUF_LEN
+    else if( CH103DiskStatus >= DISK_CONNECT )
+    {
+
+#else
+    else if( ThisUsbDev.DeviceStatus >= ROOT_DEV_CONNECTED )
+    {
+
+#endif
+        DisableRootHubPort( );
+        if( s == ERR_SUCCESS )
+        {
+            s = ERR_USB_DISCON;
+        }
+    }
+
+    return( s );
+}
+
+/*********************************************************************
+ * @fn      SetHostUsbAddr
+ *
+ * @brief  Set USB host address
+ *
+ * @param   addr -  host address
+ *
+ * @return  none
+ */
+void SetHostUsbAddr( UINT8 addr )
+{
+    R8_USB_DEV_AD = ( R8_USB_DEV_AD & RB_UDA_GP_BIT ) | ( addr & MASK_USB_ADDR );
+}
+
+#ifndef	FOR_ROOT_UDISK_ONLY
+/*********************************************************************
+ * @fn      SetUsbSpeed
+ *
+ * @brief  Set USB speed.
+ *
+ * @param   FullSpeed - USB speed.
+ *
+ * @return  none
+ */
+void SetUsbSpeed( UINT8 FullSpeed )
+{
+    if( FullSpeed )
+    {
+        R8_USB_CTRL &= ~ RB_UC_LOW_SPEED;
+        R8_UH_SETUP &= ~ RB_UH_PRE_PID_EN;
+    }
+    else
+    {
+        R8_USB_CTRL |= RB_UC_LOW_SPEED;
+    }
+}
+#endif
+
+/*********************************************************************
+ * @fn      ResetRootHubPort( )
+ *
+ * @brief   Reset root hub
+ *
+ * @return  none
+ */
+void ResetRootHubPort( void )
+{
+    UsbDevEndp0Size = DEFAULT_ENDP0_SIZE;
+    SetHostUsbAddr( 0x00 );
+    R8_UHOST_CTRL &= ~RB_UH_PORT_EN;
+    SetUsbSpeed( 1 );
+    R8_UHOST_CTRL = ( R8_UHOST_CTRL & ~RB_UH_LOW_SPEED ) | RB_UH_BUS_RESET;
+    Delay_Ms( 15 );
+    R8_UHOST_CTRL = R8_UHOST_CTRL & ~ RB_UH_BUS_RESET;
+    Delay_Us( 250 );
+    R8_USB_INT_FG = RB_UIF_DETECT;
+}
+
+/*********************************************************************
+ * @fn      EnableRootHubPort( )
+ *
+ * @brief   Enable root hub.
+ *
+ * @return  ERROR
+ */
+UINT8 EnableRootHubPort( void )
+{
+#ifdef DISK_BASE_BUF_LEN
+    if( CH103DiskStatus < DISK_CONNECT )
+    {
+        CH103DiskStatus = DISK_CONNECT;
+    }
+
+#else
+    if( ThisUsbDev.DeviceStatus < ROOT_DEV_CONNECTED )
+    {
+        ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED;
+    }
+
+#endif
+    if( R8_USB_MIS_ST & RB_UMS_DEV_ATTACH )
+    {
+#ifndef DISK_BASE_BUF_LEN
+        if( ( R8_UHOST_CTRL & RB_UH_PORT_EN ) == 0x00 )
+        {
+            ThisUsbDev.DeviceSpeed = ( R8_USB_MIS_ST & RB_UMS_DM_LEVEL ) ? 0 : 1;
+            if( ThisUsbDev.DeviceSpeed == 0 )
+            {
+                R8_UHOST_CTRL |= RB_UH_LOW_SPEED;
+            }
+        }
+
+#endif
+        R8_UHOST_CTRL |= RB_UH_PORT_EN;
+        return( ERR_SUCCESS );
+    }
+
+    return( ERR_USB_DISCON );
+}
+
+/*********************************************************************
+ * @fn      WaitUSB_Interrupt
+ *
+ * @brief   Wait USB Interrput.
+ *
+ * @return  ERROR
+ */
+UINT8 WaitUSB_Interrupt( void )
+{
+    UINT16  i;
+
+    for( i = WAIT_USB_TOUT_200US; i != 0 && ( R8_USB_INT_FG & RB_UIF_TRANSFER ) == 0; i -- ) {;}
+    return( ( R8_USB_INT_FG & RB_UIF_TRANSFER )  ? ERR_SUCCESS : ERR_USB_UNKNOWN );
+}
+
+/*********************************************************************
+ * @fn      USBHostTransact
+ *
+ * @brief   USB host transport transaction
+ * @param   endp_pid: endpoint and PID
+ *          tog: Synchronization flag
+ *          timeout: timeout times
+ *
+ * @return  EEROR:
+ *                         ERR_USB_UNKNOWN
+ *          ERR_USB_DISCON
+ *          ERR_USB_CONNECT
+ *          ERR_SUCCESS
+ */
+UINT8 USBHostTransact( UINT8 endp_pid, UINT8 tog, UINT32 timeout )
+{
+    UINT8	TransRetry;
+    UINT8	s, r;
+    UINT16	i;
+
+    R8_UH_RX_CTRL = R8_UH_TX_CTRL = tog;
+    TransRetry = 0;
+
+    do
+    {
+        R8_UH_EP_PID = endp_pid;
+        R8_USB_INT_FG = RB_UIF_TRANSFER;
+        for( i = WAIT_USB_TOUT_200US; i != 0 && ( R8_USB_INT_FG & RB_UIF_TRANSFER ) == 0; i -- );
+        R8_UH_EP_PID = 0x00;
+        if( ( R8_USB_INT_FG & RB_UIF_TRANSFER ) == 0 )
+        {
+            return( ERR_USB_UNKNOWN );
+        }
+
+        if( R8_USB_INT_FG & RB_UIF_DETECT )
+        {
+            R8_USB_INT_FG = RB_UIF_DETECT;
+            s = AnalyzeRootHub( );
+
+            if( s == ERR_USB_CONNECT )
+            {
+                FoundNewDev = 1;
+            }
+
+#ifdef DISK_BASE_BUF_LEN
+
+            if( CH103DiskStatus == DISK_DISCONNECT )
+            {
+                return( ERR_USB_DISCON );
+            }
+            if( CH103DiskStatus == DISK_CONNECT )
+            {
+                return( ERR_USB_CONNECT );
+            }
+
+#else
+            if( ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT )
+            {
+                return( ERR_USB_DISCON );
+            }
+            if( ThisUsbDev.DeviceStatus == ROOT_DEV_CONNECTED )
+            {
+                return( ERR_USB_CONNECT );
+            }
+
+#endif
+            Delay_Us( 200 );
+        }
+
+        if( R8_USB_INT_FG & RB_UIF_TRANSFER )
+        {
+            if( R8_USB_INT_ST & RB_UIS_TOG_OK )
+            {
+                return( ERR_SUCCESS );
+            }
+            r = R8_USB_INT_ST & MASK_UIS_H_RES;
+            if( r == USB_PID_STALL )
+            {
+                return( r | ERR_USB_TRANSFER );
+            }
+
+            if( r == USB_PID_NAK )
+            {
+                if( timeout == 0 )
+                {
+                    return( r | ERR_USB_TRANSFER );
+                }
+                if( timeout < 0xFFFF )
+                {
+                    timeout --;
+                }
+                -- TransRetry;
+            }
+            else switch( endp_pid >> 4 )
+                {
+                    case USB_PID_SETUP:
+
+                    case USB_PID_OUT:
+                        if( r )
+                        {
+                            return( r | ERR_USB_TRANSFER );
+                        }
+                        break;
+
+                    case USB_PID_IN:
+                        if( r == USB_PID_DATA0 && r == USB_PID_DATA1 )
+                        {
+                        }
+                        else if( r )
+                        {
+                            return( r | ERR_USB_TRANSFER );
+                        }
+                        break;
+
+                    default:
+                        return( ERR_USB_UNKNOWN );
+                }
+        }
+        else
+        {
+            R8_USB_INT_FG = 0xFF;
+        }
+        Delay_Us( 15 );
+    }
+    while( ++ TransRetry < 3 );
+
+    return( ERR_USB_TRANSFER );
+}
+
+/*********************************************************************
+ * @fn      HostCtrlTransfer
+ *
+ * @brief  Host control transport.
+ *
+ * @param   DataBuf : Receive or send data buffer.
+ *          RetLen  : Data length.
+ *
+ * @return  ERR_USB_BUF_OVER IN
+ *          ERR_SUCCESS
+ */
+UINT8 HostCtrlTransfer( PUINT8 DataBuf, PUINT8 RetLen )
+{
+    UINT16  RemLen  = 0;
+    UINT8   s, RxLen, RxCnt, TxCnt;
+    PUINT8  pBuf;
+    PUINT8   pLen;
+
+    pBuf = DataBuf;
+    pLen = RetLen;
+    Delay_Us( 200 );
+    if( pLen )
+    {
+        *pLen = 0;
+    }
+
+    R8_UH_TX_LEN = sizeof( USB_SETUP_REQ );
+    s = USBHostTransact( USB_PID_SETUP << 4 | 0x00, 0x00, 200000 / 20 );
+    if( s != ERR_SUCCESS )
+    {
+        return( s );
+    }
+    R8_UH_RX_CTRL = R8_UH_TX_CTRL = RB_UH_R_TOG | RB_UH_R_AUTO_TOG | RB_UH_T_TOG | RB_UH_T_AUTO_TOG;
+    R8_UH_TX_LEN = 0x01;
+    RemLen = pSetupReq -> wLength;
+
+    if( RemLen && pBuf )
+    {
+        if( pSetupReq -> bRequestType & USB_REQ_TYP_IN )
+        {
+            while( RemLen )
+            {
+                Delay_Us( 200 );
+                s = USBHostTransact( USB_PID_IN << 4 | 0x00, R8_UH_RX_CTRL, 200000 / 20 );
+                if( s != ERR_SUCCESS )
+                {
+                    return( s );
+                }
+                RxLen = R8_USB_RX_LEN < RemLen ? R8_USB_RX_LEN : RemLen;
+                RemLen -= RxLen;
+                if( pLen )
+                {
+                    *pLen += RxLen;
+                }
+
+                for( RxCnt = 0; RxCnt != RxLen; RxCnt ++ )
+                {
+                    *pBuf = pHOST_RX_RAM_Addr[ RxCnt ];
+                    pBuf ++;
+                }
+
+                if( R8_USB_RX_LEN == 0 || ( R8_USB_RX_LEN & ( UsbDevEndp0Size - 1 ) ) )
+                {
+                    break;
+                }
+            }
+            R8_UH_TX_LEN = 0x00;
+        }
+        else
+        {
+            while( RemLen )
+            {
+                Delay_Us( 200 );
+                R8_UH_TX_LEN = RemLen >= UsbDevEndp0Size ? UsbDevEndp0Size : RemLen;
+
+                for( TxCnt = 0; TxCnt != R8_UH_TX_LEN; TxCnt ++ )
+                {
+                    pHOST_TX_RAM_Addr[ TxCnt ] = *pBuf;
+                    pBuf ++;
+                }
+
+                s = USBHostTransact( USB_PID_OUT << 4 | 0x00, R8_UH_TX_CTRL, 200000 / 20 );
+                if( s != ERR_SUCCESS )
+                {
+                    return( s );
+                }
+                RemLen -= R8_UH_TX_LEN;
+                if( pLen )
+                {
+                    *pLen += R8_UH_TX_LEN;
+                }
+            }
+        }
+    }
+
+    Delay_Us( 200 );
+    s = USBHostTransact( ( R8_UH_TX_LEN ? USB_PID_IN << 4 | 0x00 : USB_PID_OUT << 4 | 0x00 ), RB_UH_R_TOG | RB_UH_T_TOG, 200000 / 20 );
+    if( s != ERR_SUCCESS )
+    {
+        return( s );
+    }
+    if( R8_UH_TX_LEN == 0 )
+    {
+        return( ERR_SUCCESS );
+    }
+    if( R8_USB_RX_LEN == 0 )
+    {
+        return( ERR_SUCCESS );
+    }
+
+    return( ERR_USB_BUF_OVER );
+}
+
+/*********************************************************************
+ * @fn      CopySetupReqPkg
+ *
+ * @brief  Copy setup request package.
+ *
+ * @param   pReqPkt: setup request package address.
+ *
+ * @return  none
+ */
+void CopySetupReqPkg( const UINT8 *pReqPkt )
+{
+    UINT8 i;
+
+    for( i = 0; i != sizeof( USB_SETUP_REQ ); i ++ ){
+        ( ( PUINT8 )pSetupReq )[ i ] = *pReqPkt;
+        pReqPkt++;
+    }
+}
+
+/*********************************************************************
+ * @fn      CtrlGetDeviceDescr
+ *
+ * @brief  Get device descrptor.
+ *
+ * @param   DataBuf: Data buffer.
+ *
+ * @return  ERR_USB_BUF_OVER
+ *          ERR_SUCCESS
+ */
+UINT8 CtrlGetDeviceDescr( PUINT8 DataBuf )
+{
+    UINT8   s;
+    UINT8  len;
+
+    UsbDevEndp0Size = DEFAULT_ENDP0_SIZE;
+    CopySetupReqPkg( SetupGetDevDescr );
+    s = HostCtrlTransfer( DataBuf, &len );
+
+    if( s != ERR_SUCCESS )
+    {
+        return( s );
+    }
+    UsbDevEndp0Size = ( ( PUSB_DEV_DESCR )DataBuf ) -> bMaxPacketSize0;
+    if( len < ( ( PUSB_SETUP_REQ )SetupGetDevDescr )->wLength )
+    {
+        return( ERR_USB_BUF_OVER );
+    }
+
+    return( ERR_SUCCESS );
+}
+
+/*********************************************************************
+ * @fn      CtrlGetConfigDescr
+ *
+ * @brief  Get configration descrptor.
+ *
+ * @param   DataBuf: Data buffer.
+ *
+ * @return  ERR_USB_BUF_OVER
+ *          ERR_SUCCESS
+ */
+UINT8 CtrlGetConfigDescr( PUINT8 DataBuf )
+{
+    UINT8   s;
+    UINT8  len;
+
+    CopySetupReqPkg( SetupGetCfgDescr );
+    s = HostCtrlTransfer( DataBuf, &len );
+    if( s != ERR_SUCCESS )
+    {
+        return( s );
+    }
+    if( len < ( ( PUSB_SETUP_REQ )SetupGetCfgDescr ) -> wLength )
+    {
+        return( ERR_USB_BUF_OVER );
+    }
+
+    len = ( ( PUSB_CFG_DESCR )DataBuf ) -> wTotalLength;
+    CopySetupReqPkg( SetupGetCfgDescr );
+    pSetupReq ->wLength = len;
+    s = HostCtrlTransfer( DataBuf, &len );
+    if( s != ERR_SUCCESS )
+    {
+        return( s );
+    }
+
+    return( ERR_SUCCESS );
+}
+
+/*********************************************************************
+ * @fn      CtrlSetUsbAddress
+ *
+ * @brief   Set USB device address.
+ *
+ * @param   addr: Device address.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlSetUsbAddress( UINT8 addr )
+{
+    UINT8   s;
+
+    CopySetupReqPkg( SetupSetUsbAddr );
+    pSetupReq -> wValue = addr;
+    s = HostCtrlTransfer( NULL, NULL );
+    if( s != ERR_SUCCESS )
+    {
+        return( s );
+    }
+    SetHostUsbAddr( addr );
+    Delay_Ms( 10 );
+
+    return( ERR_SUCCESS );
+}
+
+/*********************************************************************
+ * @fn      CtrlSetUsbConfig
+ *
+ * @brief   Set usb configration.
+ *
+ * @param   cfg: Configration Value.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlSetUsbConfig( UINT8 cfg )
+{
+    CopySetupReqPkg( SetupSetUsbConfig );
+    pSetupReq -> wValue = cfg;
+    return( HostCtrlTransfer( NULL, NULL ) );
+}
+
+/*********************************************************************
+ * @fn      CtrlClearEndpStall
+ *
+ * @brief   Clear endpoint STALL.
+ *
+ * @param   endp: Endpoint address.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlClearEndpStall( UINT8 endp )
+{
+    CopySetupReqPkg( SetupClrEndpStall );
+    pSetupReq -> wIndex = endp;
+    return( HostCtrlTransfer( NULL, NULL ) );
+}
+
+/*********************************************************************
+ * @fn      CtrlSetUsbIntercace
+ *
+ * @brief   Set USB Interface configration.
+ *
+ * @param   cfg: Configration value.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlSetUsbIntercace( UINT8 cfg )
+{
+    CopySetupReqPkg( SetupSetUsbInterface );
+    pSetupReq -> wValue = cfg;
+    return( HostCtrlTransfer( NULL, NULL ) );
+}
+
+/*********************************************************************
+ * @fn      USB_HostInit
+ *
+ * @brief   Initializes USB host mode.
+ *
+ * @return  ERR_SUCCESS
+ */
+void  USB_HostInit( void )
+{
+    R8_USB_CTRL = RB_UC_HOST_MODE;
+    R8_UHOST_CTRL = 0;
+    R8_USB_DEV_AD = 0x00;
+    R8_UH_EP_MOD = RB_UH_EP_TX_EN | RB_UH_EP_RX_EN;
+    R16_UH_RX_DMA = ( UINT16 )( UINT32 )pHOST_RX_RAM_Addr;
+    R16_UH_TX_DMA = ( UINT16 )( UINT32 )pHOST_TX_RAM_Addr;
+
+    R8_UH_RX_CTRL = 0x00;
+    R8_UH_TX_CTRL = 0x00;
+    R8_USB_CTRL =  RB_UC_HOST_MODE | RB_UC_INT_BUSY | RB_UC_DMA_EN;
+    R8_UH_SETUP = RB_UH_SOF_EN;
+    R8_USB_INT_FG = 0xFF;
+    DisableRootHubPort( );
+    R8_USB_INT_EN = RB_UIE_TRANSFER | RB_UIE_DETECT;
+
+    FoundNewDev = 0;
+}
+
+/*********************************************************************
+ * @fn      InitRootDevice
+ *
+ * @brief   Initializes USB root hub.
+ *
+ * @param   DataBuf: Data buffer.
+ *
+ * @return  ERROR
+ */
+UINT8 InitRootDevice( PUINT8 DataBuf )
+{
+    UINT8  i, s;
+    UINT8  cfg, dv_cls, if_cls;
+
+    ResetRootHubPort( );
+
+    for( i = 0, s = 0; i < 100; i ++ )
+    {
+        Delay_Ms( 1 );
+        if( EnableRootHubPort( ) == ERR_SUCCESS )
+        {
+            i = 0;
+            s ++;
+            if( s > 100 )
+            {
+                break;
+            }
+        }
+    }
+
+    if( i )
+    {
+        DisableRootHubPort( );
+        return( ERR_USB_DISCON );
+    }
+
+    SetUsbSpeed( ThisUsbDev.DeviceSpeed );
+
+    s = CtrlGetDeviceDescr( DataBuf );
+
+    if( s == ERR_SUCCESS )
+    {
+
+        ThisUsbDev.DeviceVID = ( ( PUSB_DEV_DESCR )DataBuf )->idVendor;
+        ThisUsbDev.DevicePID = ( ( PUSB_DEV_DESCR )DataBuf )->idProduct;
+        dv_cls = ( ( PUSB_DEV_DESCR )DataBuf ) -> bDeviceClass;
+
+        s = CtrlSetUsbAddress( ( ( PUSB_SETUP_REQ )SetupSetUsbAddr )->wValue );
+
+        if( s == ERR_SUCCESS )
+        {
+            ThisUsbDev.DeviceAddress = ( ( PUSB_SETUP_REQ )SetupSetUsbAddr )->wValue;
+
+            s = CtrlGetConfigDescr( DataBuf );
+
+            if( s == ERR_SUCCESS )
+            {
+                cfg = ( ( PUSB_CFG_DESCR )DataBuf )->bConfigurationValue;
+                if_cls = ( ( PUSB_CFG_DESCR_LONG )DataBuf )->itf_descr.bInterfaceClass;
+
+                if( ( dv_cls == 0x00 ) && ( if_cls == USB_DEV_CLASS_STORAGE ) )
+                {
+
+#ifdef	FOR_ROOT_UDISK_ONLY
+                    CH103DiskStatus = DISK_USB_ADDR;
+                    return( ERR_SUCCESS );
+                }
+                else
+                {
+                    return( ERR_USB_UNSUPPORT );
+                }
+
+#else
+                    s = CtrlSetUsbConfig( cfg );
+
+                    if( s == ERR_SUCCESS )
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        ThisUsbDev.DeviceType = USB_DEV_CLASS_STORAGE;
+                        SetUsbSpeed( 1 );
+                        return( ERR_SUCCESS );
+                    }
+                }
+                else if( ( dv_cls == 0x00 ) && ( if_cls == USB_DEV_CLASS_PRINTER ) && ( ( PUSB_CFG_DESCR_LONG )DataBuf )->itf_descr.bInterfaceSubClass == 0x01 )
+                {
+                    s = CtrlSetUsbConfig( cfg );
+                    if( s == ERR_SUCCESS )
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        ThisUsbDev.DeviceType = USB_DEV_CLASS_PRINTER;
+                        SetUsbSpeed( 1 );
+                        return( ERR_SUCCESS );
+                    }
+                }
+                else if( ( dv_cls == 0x00 ) && ( if_cls == USB_DEV_CLASS_HID ) && ( ( PUSB_CFG_DESCR_LONG )DataBuf )->itf_descr.bInterfaceSubClass <= 0x01 )
+                {
+                    if_cls = ( ( PUSB_CFG_DESCR_LONG )DataBuf ) -> itf_descr.bInterfaceProtocol;
+                    s = CtrlSetUsbConfig( cfg );
+                    if( s == ERR_SUCCESS )
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        if( if_cls == 1 )
+                        {
+                            ThisUsbDev.DeviceType = DEV_TYPE_KEYBOARD;
+                            SetUsbSpeed( 1 );
+                            return( ERR_SUCCESS );
+                        }
+                        else if( if_cls == 2 )
+                        {
+                            ThisUsbDev.DeviceType = DEV_TYPE_MOUSE;
+                            SetUsbSpeed( 1 );
+                            return( ERR_SUCCESS );
+                        }
+                        s = ERR_USB_UNSUPPORT;
+                    }
+                }
+                else
+                {
+                    s = CtrlSetUsbConfig( cfg );
+                    if( s == ERR_SUCCESS )
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        ThisUsbDev.DeviceType = DEV_TYPE_UNKNOW;
+                        SetUsbSpeed( 1 );
+                        return( ERR_SUCCESS );
+                    }
+                }
+
+#endif
+            }
+        }
+    }
+
+#ifdef	FOR_ROOT_UDISK_ONLY
+    CH103DiskStatus = DISK_CONNECT;
+
+#else
+    ThisUsbDev.DeviceStatus = ROOT_DEV_FAILED;
+
+#endif
+
+    SetUsbSpeed( 1 );
+
+    return( s );
+}
+/*********************************************************************
+ * @fn      HubGetPortStatus
+ *
+ * @brief   查询HUB端口状态,返回在Com_Buffer中
+ *
+ * @param   UINT8 HubPortIndex
+ *
+ * @return  ERR_SUCCESS 成功
+ *          ERR_USB_BUF_OVER 长度错误
+ */
+UINT8   HubGetPortStatus( UINT8 HubPortIndex )
+{
+    UINT8   s;
+    UINT8  len;
+
+    pSetupReq -> bRequestType = HUB_GET_PORT_STATUS;
+    pSetupReq -> bRequest = HUB_GET_STATUS;
+    pSetupReq -> wValue = 0x0000;
+    pSetupReq -> wIndex = 0x0000 | HubPortIndex;
+    pSetupReq -> wLength = 0x0004;
+    s = HostCtrlTransfer( Com_Buffer, &len );                           // 执行控制传输
+    if( s != ERR_SUCCESS )
+    {
+        return( s );
+    }
+    if( len < 4 )
+    {
+        return( ERR_USB_BUF_OVER );                                             // 描述符长度错误
+    }
+    return( ERR_SUCCESS );
+}
+
+/*********************************************************************
+ * @fn      HubSetPortFeature
+ *
+ * @brief   设置HUB端口特性
+ *
+ * @param   UINT8 HubPortIndex
+ *          UINT8 FeatureSelt
+ *
+ * @return  ERR_SUCCESS 成功
+ */
+UINT8   HubSetPortFeature( UINT8 HubPortIndex, UINT8 FeatureSelt )
+{
+    pSetupReq -> bRequestType = HUB_SET_PORT_FEATURE;
+    pSetupReq -> bRequest = HUB_SET_FEATURE;
+    pSetupReq -> wValue = 0x0000 | FeatureSelt;
+    pSetupReq -> wIndex = 0x0000 | HubPortIndex;
+    pSetupReq -> wLength = 0x0000;
+    return( HostCtrlTransfer( NULL, NULL ) );                                 // 执行控制传输
+}
+
+/*********************************************************************
+ * @fn      HubClearPortFeature
+ *
+ * @brief   清除HUB端口特性
+ *
+ * @param   UINT8 HubPortIndex
+ *          UINT8 FeatureSelt
+ *
+ * @return  ERR_SUCCESS 成功
+ */
+UINT8   HubClearPortFeature( UINT8 HubPortIndex, UINT8 FeatureSelt )
+{
+    pSetupReq -> bRequestType = HUB_CLEAR_PORT_FEATURE;
+    pSetupReq -> bRequest = HUB_CLEAR_FEATURE;
+    pSetupReq -> wValue = 0x0000 | FeatureSelt;
+    pSetupReq -> wIndex = 0x0000 | HubPortIndex;
+    pSetupReq -> wLength = 0x0000;
+    return( HostCtrlTransfer( NULL, NULL ) );                                // 执行控制传输
+}
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/StdPeriphDriver/src/ch32f10x_wwdg.c

@@ -0,0 +1,150 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f10x_wwdg.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file provides all the WWDG firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ **********************************************************************************/
+#include "ch32f10x_wwdg.h"
+#include "ch32f10x_rcc.h"
+
+
+/* WWDG registers bit address in the alias region */
+#define WWDG_OFFSET        (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFGR_OFFSET        (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber      0x09
+#define CFGR_EWI_BB        (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* CTLR register bit mask */
+#define CTLR_WDGA_Set      ((uint32_t)0x00000080)
+
+/* CFGR register bit mask */
+#define CFGR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
+#define CFGR_W_Mask        ((uint32_t)0xFFFFFF80)
+#define BIT_Mask           ((uint8_t)0x7F)
+
+
+/*********************************************************************
+ * @fn      WWDG_DeInit
+ *
+ * @brief   Deinitializes the WWDG peripheral registers to their default reset values
+ *
+ * @return  none
+ */
+void WWDG_DeInit( void )
+{
+    RCC_APB1PeriphResetCmd( RCC_APB1Periph_WWDG, ENABLE );
+    RCC_APB1PeriphResetCmd( RCC_APB1Periph_WWDG, DISABLE );
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetPrescaler
+ *
+ * @brief   Sets the WWDG Prescaler
+ *
+ * @param   WWDG_Prescaler - specifies the WWDG Prescaler
+ *            WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
+ *            WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
+ *            WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
+ *            WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
+ *
+ * @return  none
+ */
+void WWDG_SetPrescaler( uint32_t WWDG_Prescaler )
+{
+    uint32_t tmpreg = 0;
+    tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
+    tmpreg |= WWDG_Prescaler;
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetWindowValue
+ *
+ * @brief   Sets the WWDG window value
+ *
+ * @param   WindowValue - specifies the window value to be compared to the
+ *        downcounter,which must be lower than 0x80
+ *
+ * @return  none
+ */
+void WWDG_SetWindowValue( uint8_t WindowValue )
+{
+    __IO uint32_t tmpreg = 0;
+
+    tmpreg = WWDG->CFGR & CFGR_W_Mask;
+
+    tmpreg |= WindowValue & ( uint32_t ) BIT_Mask;
+
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_EnableIT
+ *
+ * @brief   Enables the WWDG Early Wakeup interrupt(EWI)
+ *
+ * @return  none
+ */
+void WWDG_EnableIT( void )
+{
+    *( __IO uint32_t * ) CFGR_EWI_BB = ( uint32_t )ENABLE;
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetCounter
+ *
+ * @brief   Sets the WWDG counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ *
+ * @return  none
+ */
+void WWDG_SetCounter( uint8_t Counter )
+{
+    WWDG->CTLR = Counter & BIT_Mask;
+}
+
+
+/*********************************************************************
+ * @fn      WWDG_Enable
+ *
+ * @brief   Enables WWDG and load the counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ * @return  none
+ */
+void WWDG_Enable( uint8_t Counter )
+{
+    WWDG->CTLR = CTLR_WDGA_Set | Counter;
+}
+
+/*********************************************************************
+ * @fn      WWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the Early Wakeup interrupt flag is set or not
+ *
+ * @return  The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus( void )
+{
+    return ( FlagStatus )( WWDG->STATR );
+}
+
+/*********************************************************************
+ * @fn      WWDG_ClearFlag
+ *
+ * @brief   Clears Early Wakeup interrupt flag
+ *
+ * @return  none
+ */
+void WWDG_ClearFlag( void )
+{
+    WWDG->STATR = ( uint32_t )RESET;
+}

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/hw_config.c

@@ -0,0 +1,154 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : hw_config.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : USB configuration file.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_istr.h"
+#include "hw_config.h"
+#include "usb_pwr.h"  
+#include "string.h"	
+#include "stdarg.h"		 
+#include "stdio.h"	
+
+/*********************************************************************
+ * @fn      USBWakeUp_IRQHandler
+ *
+ * @brief   This function handles USB wake up exception.
+ *
+ * @return  none
+ */
+void USBWakeUp_IRQHandler(void) 
+{
+	EXTI_ClearITPendingBit(EXTI_Line18);
+} 
+
+/*********************************************************************
+ * @fn      USBWakeUp_IRQHandler
+ *
+ * @brief   This function handles USB exception.
+ *
+ * @return  none
+ */
+void USB_LP_CAN1_RX0_IRQHandler(void) 
+{
+	USB_Istr();
+} 
+
+/*********************************************************************
+ * @fn      Set_USBConfig
+ *
+ * @brief   Set_USBConfig.
+ *
+ * @return  none
+ */
+void Set_USBConfig( )
+{
+	
+	RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);	
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);	 		 
+}
+
+/*********************************************************************
+ * @fn      Enter_LowPowerMode
+ *
+ * @brief   Enter low power mode.
+ *
+ * @return  none
+ */
+void Enter_LowPowerMode(void)
+{  
+ 	printf("usb enter low power mode\r\n");
+	bDeviceState=SUSPENDED;
+} 
+
+/*********************************************************************
+ * @fn      Leave_LowPowerMode
+ *
+ * @brief   Leave low power mode.
+ *
+ * @return  none
+ */
+void Leave_LowPowerMode(void)
+{
+	DEVICE_INFO *pInfo=&Device_Info;
+	printf("leave low power mode\r\n"); 
+	if (pInfo->Current_Configuration!=0)bDeviceState=CONFIGURED; 
+	else bDeviceState = ATTACHED; 
+} 
+
+/*********************************************************************
+ * @fn      USB_Interrupts_Config
+ *
+ * @brief   Configrate USB interrupt.
+ *
+ * @return  none
+ */
+void USB_Interrupts_Config(void)
+{ 
+	NVIC_InitTypeDef NVIC_InitStructure;
+	EXTI_InitTypeDef EXTI_InitStructure;
+
+	EXTI_ClearITPendingBit(EXTI_Line18);
+	EXTI_InitStructure.EXTI_Line = EXTI_Line18; 
+	EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+	EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;	
+	EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+	EXTI_Init(&EXTI_InitStructure); 	 
+
+	NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;	
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+	NVIC_Init(&NVIC_InitStructure);
+	
+	NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;  
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+	NVIC_Init(&NVIC_InitStructure);   
+}	
+
+/*********************************************************************
+ * @fn      USB_Port_Set
+ *
+ * @brief   Set USB IO port.
+ *
+ * @param   NewState - DISABLE or ENABLE.
+ *          Pin_In_IPU - Enables or Disables intenal pull-up resistance.
+ *
+ * @return  none
+ */
+void USB_Port_Set(FunctionalState NewState, FunctionalState Pin_In_IPU)
+{
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+	if(NewState) {
+		_SetCNTR(_GetCNTR()&(~(1<<1)));
+		GPIOA->CFGHR&=0XFFF00FFF;
+		GPIOA->OUTDR&=~(3<<11);	//PA11/12=0
+		GPIOA->CFGHR|=0X00088000;	// IPD
+	}
+	else
+	{	  
+		_SetCNTR(_GetCNTR()|(1<<1));  
+		GPIOA->CFGHR&=0XFFF00FFF;
+		GPIOA->OUTDR&=~(3<<11);	//PA11/12=0
+		GPIOA->CFGHR|=0X00033000;	// LOW
+	}
+	
+	if(Pin_In_IPU) (EXTEN->EXTEN_CTR) |= EXTEN_USBD_PU_EN; 
+	else (EXTEN->EXTEN_CTR) &= ~EXTEN_USBD_PU_EN;
+}  
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/hw_config.h

@@ -0,0 +1,36 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : hw_config.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Configuration file for USB.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __HW_CONFIG_H
+#define __HW_CONFIG_H
+
+#include "usb_type.h" 
+ 
+#ifdef	DEBUG
+#define printf_usb(X...) printf(X)
+#else
+#define printf_usb(X...)
+#endif 
+
+
+void Set_USBConfig(void);
+void Enter_LowPowerMode(void);
+void Leave_LowPowerMode(void);
+void USB_Interrupts_Config(void);
+void USB_Port_Set(FunctionalState NewState, FunctionalState Pin_In_IPU);
+
+#endif /* __HW_CONFIG_H */ 
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_conf.h

@@ -0,0 +1,75 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB configration firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_CONF_H
+#define __USB_CONF_H
+
+
+#define EP_NUM                          (4)
+
+/* Buffer Description Table */
+/* buffer table base address */
+/* buffer table base address */
+#define BTABLE_ADDRESS      (0x00)
+
+/* EP0  */
+/* rx/tx buffer base address */
+#define ENDP0_RXADDR        (0x40)
+#define ENDP0_TXADDR        (0x80)
+
+/* EP1  */
+/* tx buffer base address */
+#define ENDP1_TXADDR        (0xC0)
+#define ENDP2_TXADDR        (0x100)
+#define ENDP2_RXADDR        (0x110)
+#define ENDP3_RXADDR        (0x111)
+
+/* ISTR events */
+/* IMR_MSK */
+/* mask defining which events has to be handled */
+/* by the device application software */
+#define IMR_MSK (CNTR_CTRM  | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM  | CNTR_SOFM \
+                 | CNTR_ESOFM | CNTR_RESETM )
+
+/*#define CTR_CALLBACK*/
+/*#define DOVR_CALLBACK*/
+/*#define ERR_CALLBACK*/
+/*#define WKUP_CALLBACK*/
+/*#define SUSP_CALLBACK*/
+/*#define RESET_CALLBACK*/
+#define SOF_CALLBACK
+/*#define ESOF_CALLBACK*/
+
+
+/* CTR service routines */
+/* associated to defined endpoints */
+#define  EP1_IN_Callback   NOP_Process
+/*#define  EP2_IN_Callback   NOP_Process*/
+#define  EP3_IN_Callback   NOP_Process
+#define  EP4_IN_Callback   NOP_Process
+#define  EP5_IN_Callback   NOP_Process
+#define  EP6_IN_Callback   NOP_Process
+#define  EP7_IN_Callback   NOP_Process
+
+#define  EP1_OUT_Callback   NOP_Process
+/*#define  EP2_OUT_Callback   NOP_Process*/
+#define  EP3_OUT_Callback   NOP_Process
+#define  EP4_OUT_Callback   NOP_Process
+#define  EP5_OUT_Callback   NOP_Process
+#define  EP6_OUT_Callback   NOP_Process
+#define  EP7_OUT_Callback   NOP_Process
+
+#endif /* __USB_CONF_H */
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_desc.c

@@ -0,0 +1,71 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_desc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Descriptors for Virtual Com Port Demo.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+#include "usb_desc.h"
+
+/* USB Device Descriptors */
+const uint8_t  USBD_DeviceDescriptor[] = { 
+	0x12, 0x01, 0x10, 0x01,0xFF, 0x80, 0x55, 0x08,							 
+	0x48, 0x43, 0x37, 0x55,  					
+	0x00, 0x01, 0x01, 0x02, 0x03, 0x01,
+};
+
+/* USB Configration Descriptors */
+const uint8_t  USBD_ConfigDescriptor[] = { 
+	0x09, 0x02, 0x4A, 0x00, 0x01, 0x01, 0x00, 0x80, 0x32,
+	0x09, 0x04, 0x00, 0x00, 0x07, 0xFF, 0x80, 0x55, 0x00,
+	0x07, 0x05, 0x84, 0x02, 0x40, 0x00, 0x00,
+	0x07, 0x05, 0x04, 0x02, 0x40, 0x00, 0x00,
+	0x07, 0x05, 0x83, 0x02, 0x40, 0x00, 0x00,
+	0x07, 0x05, 0x03, 0x02, 0x40, 0x00, 0x00,
+	0x07, 0x05, 0x82, 0x02, 0x40, 0x00, 0x00,
+	0x07, 0x05, 0x02, 0x02, 0x40, 0x00, 0x00,
+	0x07, 0x05, 0x81, 0x02, 0x40, 0x00, 0x00,
+	0x07, 0x05, 0x01, 0x02, 0x40, 0x00, 0x00,
+};
+
+/* USB String Descriptors */
+const uint8_t USBD_StringLangID[USBD_SIZE_STRING_LANGID] = {
+	USBD_SIZE_STRING_LANGID,
+	USB_STRING_DESCRIPTOR_TYPE,
+	0x09,
+	0x04 
+};
+
+/* USB Device String Vendor */
+const uint8_t USBD_StringVendor[USBD_SIZE_STRING_VENDOR] = {
+	USBD_SIZE_STRING_VENDOR,    
+	USB_STRING_DESCRIPTOR_TYPE,           
+	'W', 0, 'C', 0, 'H', 0, 'I', 0, 'C', 0, 'r', 0, 'o', 0, 'e', 0,
+	'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+	'c', 0, 's', 0
+};
+
+/* USB Device String Product */
+const uint8_t USBD_StringProduct[USBD_SIZE_STRING_PRODUCT] = {
+	USBD_SIZE_STRING_PRODUCT,         
+	USB_STRING_DESCRIPTOR_TYPE,        
+	'W', 0, 'C', 0, 'H', 0, '3', 0, '2', 0, ' ', 0, 'V', 0, 'i', 0,
+	'r', 0, 't', 0, 'u', 0, 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0,
+	'M', 0, ' ', 0, 'P', 0, 'o', 0, 'r', 0, 't', 0, ' ', 0, ' ', 0
+};
+
+/* USB Device String Serial */
+uint8_t USBD_StringSerial[USBD_SIZE_STRING_SERIAL] = {
+	USBD_SIZE_STRING_SERIAL,          
+	USB_STRING_DESCRIPTOR_TYPE,                   
+	'W', 0, 'C', 0, 'H', 0, '3', 0, '2', 0
+};
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_desc.h

@@ -0,0 +1,52 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_desc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB description firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_DESC_H
+#define __USB_DESC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+	 
+#include "ch32f10x.h"
+	 
+	 
+#define USB_DEVICE_DESCRIPTOR_TYPE              0x01
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE       0x02
+#define USB_STRING_DESCRIPTOR_TYPE              0x03
+#define USB_INTERFACE_DESCRIPTOR_TYPE           0x04
+#define USB_ENDPOINT_DESCRIPTOR_TYPE            0x05
+
+#define USBD_DATA_SIZE               64
+#define USBD_INT_SIZE                8
+       
+#define USBD_SIZE_DEVICE_DESC        18
+#define USBD_SIZE_CONFIG_DESC        74
+#define USBD_SIZE_STRING_LANGID      4
+#define USBD_SIZE_STRING_VENDOR      38
+#define USBD_SIZE_STRING_PRODUCT     50
+#define USBD_SIZE_STRING_SERIAL      26
+
+#define STANDARD_ENDPOINT_DESC_SIZE             0x09
+
+
+extern const uint8_t USBD_DeviceDescriptor[USBD_SIZE_DEVICE_DESC];
+extern const uint8_t USBD_ConfigDescriptor[USBD_SIZE_CONFIG_DESC];
+                    
+extern const uint8_t USBD_StringLangID [USBD_SIZE_STRING_LANGID];
+extern const uint8_t USBD_StringVendor [USBD_SIZE_STRING_VENDOR];
+extern const uint8_t USBD_StringProduct[USBD_SIZE_STRING_PRODUCT];
+extern uint8_t USBD_StringSerial [USBD_SIZE_STRING_SERIAL];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_DESC_H */

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_endp.c

@@ -0,0 +1,85 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_endp.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Endpoint routines
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_mem.h"
+#include "hw_config.h"
+#include "usb_istr.h"
+#include "usb_pwr.h"
+
+/* Interval between sending IN packets in frame number (1 frame = 1ms) */
+#define IN_FRAME_INTERVAL             5
+
+/* Private variables */
+uint8_t USB_Rx_Buffer[USBD_DATA_SIZE];
+u16 USB_Rx_Cnt=0; 
+
+/*********************************************************************
+ * @fn      EP2_IN_Callback
+ *
+ * @brief   Endpoint 2 IN.
+ *
+ * @return  none
+ */
+void EP2_IN_Callback (void)
+{ 
+	UserToPMABufferCopy(USB_Rx_Buffer, ENDP2_TXADDR, USB_Rx_Cnt);
+	SetEPTxCount(ENDP2, USB_Rx_Cnt);
+	SetEPTxValid(ENDP2);   
+}
+
+/*********************************************************************
+ * @fn      EP2_OUT_Callback
+ *
+ * @brief   Endpoint 2 IN.
+ *
+ * @return  none
+ */
+void EP2_OUT_Callback(void)
+{
+	uint8_t i; 
+	
+	USB_Rx_Cnt = USB_SIL_Read(EP2_OUT, USB_Rx_Buffer);	
+	
+  for(i=0;i<USB_Rx_Cnt;i++)
+	{
+    USB_Rx_Buffer[i] = ~USB_Rx_Buffer[i];
+	}
+	
+  EP2_IN_Callback(); 
+	SetEPRxValid(ENDP2);													
+}
+
+/*********************************************************************
+ * @fn      SOF_Callback
+ *
+ * @brief   SOF call back.
+ *
+ * @return  none
+ */
+void SOF_Callback(void)
+{
+	static uint32_t FrameCount = 0;
+
+	if(bDeviceState == CONFIGURED)
+	{
+		if (FrameCount++ == IN_FRAME_INTERVAL)
+		{		
+			FrameCount = 0;
+			//Handle_USBAsynchXfer();
+		}
+	}  
+}
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_istr.c

@@ -0,0 +1,189 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_istr.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : ISTR events interrupt service routines
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_pwr.h"
+#include "usb_istr.h"
+
+/* Private variables */
+__IO uint16_t wIstr;  
+__IO uint8_t bIntPackSOF = 0;  
+__IO uint32_t esof_counter =0;
+__IO uint32_t wCNTR=0;
+
+/* function pointers to non-control endpoints service routines */
+void (*pEpInt_IN[7])(void) ={
+	EP1_IN_Callback,
+	EP2_IN_Callback,
+	EP3_IN_Callback,
+	EP4_IN_Callback,
+	EP5_IN_Callback,
+	EP6_IN_Callback,
+	EP7_IN_Callback,
+};
+
+void (*pEpInt_OUT[7])(void) ={
+	EP1_OUT_Callback,
+	EP2_OUT_Callback,
+	EP3_OUT_Callback,
+	EP4_OUT_Callback,
+	EP5_OUT_Callback,
+	EP6_OUT_Callback,
+	EP7_OUT_Callback,
+};
+
+/*********************************************************************
+ * @fn      USB_Istr
+ *
+ * @brief   ISTR events interrupt service routine
+ *
+ * @return  none
+ */
+void USB_Istr(void)
+{
+    uint32_t i=0;
+ __IO uint32_t EP[8];
+  
+  wIstr = _GetISTR();
+#if (IMR_MSK & ISTR_SOF)
+  if (wIstr & ISTR_SOF & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_SOF);
+    bIntPackSOF++;
+
+#ifdef SOF_CALLBACK
+    SOF_Callback();
+		
+#endif
+  }
+#endif
+ 
+  
+#if (IMR_MSK & ISTR_CTR)
+  if (wIstr & ISTR_CTR & wInterrupt_Mask)
+  {
+    CTR_LP();
+#ifdef CTR_CALLBACK
+    CTR_Callback();
+#endif
+  }
+#endif
+ 
+#if (IMR_MSK & ISTR_RESET)
+  if (wIstr & ISTR_RESET & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_RESET);
+    Device_Property.Reset();
+    // SetDeviceAddress(0);
+#ifdef RESET_CALLBACK
+    RESET_Callback();
+#endif
+  }
+#endif
+
+#if (IMR_MSK & ISTR_DOVR)
+  if (wIstr & ISTR_DOVR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_DOVR);
+#ifdef DOVR_CALLBACK
+    DOVR_Callback();
+#endif
+  }
+#endif
+
+#if (IMR_MSK & ISTR_ERR)
+  if (wIstr & ISTR_ERR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_ERR);
+#ifdef ERR_CALLBACK
+    ERR_Callback();
+#endif
+  }
+#endif
+
+#if (IMR_MSK & ISTR_WKUP)
+  if (wIstr & ISTR_WKUP & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_WKUP);
+    Resume(RESUME_EXTERNAL);
+#ifdef WKUP_CALLBACK
+    WKUP_Callback();
+#endif
+  }
+#endif
+#if (IMR_MSK & ISTR_SUSP)
+  if (wIstr & ISTR_SUSP & wInterrupt_Mask)
+  {
+    if (fSuspendEnabled)
+    {
+      Suspend();
+    }
+    else
+    {
+      Resume(RESUME_LATER);
+    }
+    _SetISTR((uint16_t)CLR_SUSP);
+#ifdef SUSP_CALLBACK
+    SUSP_Callback();
+#endif
+  }
+#endif
+
+#if (IMR_MSK & ISTR_ESOF)
+  if (wIstr & ISTR_ESOF & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_ESOF);
+    
+    if ((_GetFNR()&FNR_RXDP)!=0)
+    {
+      esof_counter ++;
+      
+      if ((esof_counter >3)&&((_GetCNTR()&CNTR_FSUSP)==0))
+      {           
+
+        wCNTR = _GetCNTR(); 
+      
+        for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+      
+        wCNTR|=CNTR_FRES;
+        _SetCNTR(wCNTR);
+ 
+        wCNTR&=~CNTR_FRES;
+        _SetCNTR(wCNTR);
+      
+        while((_GetISTR()&ISTR_RESET) == 0);
+  
+        _SetISTR((uint16_t)CLR_RESET);
+   
+        for (i=0;i<8;i++)
+        _SetENDPOINT(i, EP[i]);
+      
+        esof_counter = 0;
+      }
+    }
+    else
+    {
+        esof_counter = 0;
+    }
+    
+    Resume(RESUME_ESOF); 
+
+#ifdef ESOF_CALLBACK
+    ESOF_Callback();
+#endif
+  }
+#endif
+} /* USB_Istr */
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_istr.h

@@ -0,0 +1,75 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_istr.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file includes the peripherals header files in the 
+ *                      user application.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_ISTR_H
+#define __USB_ISTR_H
+
+#include "usb_conf.h"
+
+
+void USB_Istr(void);
+void EP1_IN_Callback(void);
+void EP2_IN_Callback(void);
+void EP3_IN_Callback(void);
+void EP4_IN_Callback(void);
+void EP5_IN_Callback(void);
+void EP6_IN_Callback(void);
+void EP7_IN_Callback(void);
+
+void EP1_OUT_Callback(void);
+void EP2_OUT_Callback(void);
+void EP3_OUT_Callback(void);
+void EP4_OUT_Callback(void);
+void EP5_OUT_Callback(void);
+void EP6_OUT_Callback(void);
+void EP7_OUT_Callback(void);
+
+#ifdef CTR_CALLBACK
+void CTR_Callback(void);
+#endif
+
+#ifdef DOVR_CALLBACK
+void DOVR_Callback(void);
+#endif
+
+#ifdef ERR_CALLBACK
+void ERR_Callback(void);
+#endif
+
+#ifdef WKUP_CALLBACK
+void WKUP_Callback(void);
+#endif
+
+#ifdef SUSP_CALLBACK
+void SUSP_Callback(void);
+#endif
+
+#ifdef RESET_CALLBACK
+void RESET_Callback(void);
+#endif
+
+#ifdef SOF_CALLBACK
+void SOF_Callback(void);
+#endif
+
+#ifdef ESOF_CALLBACK
+void ESOF_Callback(void);
+#endif
+
+
+#endif /*__USB_ISTR_H*/
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_prop.c

@@ -0,0 +1,338 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_prop.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : All processing related to Virtual Com Port Demo
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+uint8_t Request = 0;
+
+DEVICE Device_Table =
+{
+	EP_NUM,
+	1
+};
+
+DEVICE_PROP Device_Property =
+{
+	USBD_init,
+	USBD_Reset,
+	USBD_Status_In,
+	USBD_Status_Out,
+	USBD_Data_Setup,
+	USBD_NoData_Setup,
+	USBD_Get_Interface_Setting,
+	USBD_GetDeviceDescriptor,
+	USBD_GetConfigDescriptor,
+	USBD_GetStringDescriptor,
+	0,
+	0x08                                 
+};
+
+USER_STANDARD_REQUESTS User_Standard_Requests =
+{
+	USBD_GetConfiguration,
+	USBD_SetConfiguration,
+	USBD_GetInterface,
+	USBD_SetInterface,
+	USBD_GetStatus, 
+	USBD_ClearFeature,
+	USBD_SetEndPointFeature,
+	USBD_SetDeviceFeature,
+	USBD_SetDeviceAddress
+};
+
+ONE_DESCRIPTOR Device_Descriptor =
+{
+	(uint8_t*)USBD_DeviceDescriptor,
+	USBD_SIZE_DEVICE_DESC
+};
+
+ONE_DESCRIPTOR Config_Descriptor =
+{
+	(uint8_t*)USBD_ConfigDescriptor,
+	USBD_SIZE_CONFIG_DESC
+};
+
+ONE_DESCRIPTOR String_Descriptor[4] =
+{
+	{(uint8_t*)USBD_StringLangID, USBD_SIZE_STRING_LANGID},
+	{(uint8_t*)USBD_StringVendor, USBD_SIZE_STRING_VENDOR},
+	{(uint8_t*)USBD_StringProduct,USBD_SIZE_STRING_PRODUCT},
+	{(uint8_t*)USBD_StringSerial, USBD_SIZE_STRING_SERIAL}
+};
+
+
+/*********************************************************************
+ * @fn      USBD_SetConfiguration.
+ *
+ * @brief   Update the device state to configured.
+ *
+ * @return  none
+ */
+void USBD_SetConfiguration(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  if (pInfo->Current_Configuration != 0)
+  {
+    bDeviceState = CONFIGURED;
+  }
+}
+
+/*********************************************************************
+ * @fn      USBD_SetDeviceAddress.
+ *
+ * @brief   Update the device state to addressed.
+ *
+ * @return  none
+ */
+void USBD_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+
+/*********************************************************************
+ * @fn      USBD_Status_In.
+ *
+ * @brief   USBD Status In Routine.
+ *
+ * @return  none
+ */
+void USBD_Status_In(void)
+{
+ 
+}
+
+/*********************************************************************
+ * @fn      USBD_Status_Out
+ *
+ * @brief   USBD Status OUT Routine.
+ *
+ * @return  none
+ */
+void USBD_Status_Out(void)
+{
+    
+}
+
+/*********************************************************************
+ * @fn      USB_init.
+ *
+ * @brief   init routine.
+ *
+ * @return  none
+ */
+void USBD_init(void)
+{
+  uint8_t	i;
+    
+  pInformation->Current_Configuration = 0;
+  PowerOn();
+  for (i=0;i<8;i++) _SetENDPOINT(i,_GetENDPOINT(i) & 0x7F7F & EPREG_MASK);//all clear
+  _SetISTR((uint16_t)0x00FF);//all clear
+  USB_SIL_Init();
+  bDeviceState = UNCONNECTED;
+}
+
+/*********************************************************************
+ * @fn      USBD_Reset
+ *
+ * @brief   Virtual_Com_Port Mouse reset routine
+ *
+ * @return  none
+ */
+void USBD_Reset(void)
+{
+  pInformation->Current_Configuration = 0;
+  pInformation->Current_Feature = USBD_ConfigDescriptor[7];
+  pInformation->Current_Interface = 0;
+
+  SetBTABLE(BTABLE_ADDRESS);
+
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+  _ClearDTOG_RX(ENDP0);
+  _ClearDTOG_TX(ENDP0);
+
+  SetEPType(ENDP1, EP_BULK);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  SetEPRxStatus(ENDP1, EP_RX_DIS);
+  _ClearDTOG_RX(ENDP1);
+  _ClearDTOG_TX(ENDP1);
+
+  SetEPType(ENDP2, EP_BULK);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPRxAddr(ENDP2, ENDP2_RXADDR);   
+  SetEPRxCount(ENDP2, USBD_DATA_SIZE);
+  SetEPRxStatus(ENDP2, EP_RX_VALID);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+  _ClearDTOG_RX(ENDP2);
+  _ClearDTOG_TX(ENDP2);
+
+  SetEPType(ENDP3, EP_INTERRUPT);
+  SetEPRxAddr(ENDP3, ENDP3_RXADDR);
+  SetEPRxCount(ENDP3, USBD_DATA_SIZE);
+  SetEPRxStatus(ENDP3, EP_RX_VALID);
+  SetEPTxStatus(ENDP3, EP_TX_DIS);
+  _ClearDTOG_RX(ENDP3);
+  _ClearDTOG_TX(ENDP3);
+   
+  SetDeviceAddress(0);
+  
+  bDeviceState = ATTACHED;
+}
+
+/*********************************************************************
+ * @fn      USBD_GetDeviceDescriptor.
+ *
+ * @brief   Gets the device descriptor.
+ *
+ * @param   Length.
+ *
+ * @return  The address of the device descriptor.
+ */
+uint8_t *USBD_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor);
+}
+
+/*********************************************************************
+ * @fn      USBD_GetConfigDescriptor.
+ *
+ * @brief   get the configuration descriptor.
+ *
+ * @param   Length.
+ *
+ * @return  The address of the device descriptor.
+ */
+uint8_t *USBD_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Config_Descriptor);
+}
+
+/*********************************************************************
+ * @fn      USBD_GetStringDescriptor
+ *
+ * @brief   Gets the string descriptors according to the needed index
+ *
+ * @param   Length.
+ *
+ * @return  The address of the device descriptor.
+ */
+uint8_t *USBD_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+	
+  if (wValue0 > 4)
+  {
+    return NULL;
+  }
+  else
+  {
+    return Standard_GetDescriptorData(Length, &String_Descriptor[wValue0]);
+  }
+}
+
+/*********************************************************************
+ * @fn      USBD_Get_Interface_Setting.
+ *
+ * @brief   test the interface and the alternate setting according to the
+ *          supported one.
+ *
+ * @param   Interface - interface number.
+ *          AlternateSetting - Alternate Setting number.
+ *
+ * @return  The address of the device descriptor.
+ */
+RESULT USBD_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else if (Interface > 1)
+  {
+    return USB_UNSUPPORT;
+  }
+	
+  return USB_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      USBD_Data_Setup
+ *
+ * @brief   handle the data class specific requests
+ *
+ * @param   Request Nb.
+ *
+ * @return  USB_UNSUPPORT or USB_SUCCESS.
+ */
+RESULT USBD_Data_Setup(uint8_t RequestNo)
+{
+  
+  return USB_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      USBD_NoData_Setup.
+ *
+ * @brief   handle the no data class specific requests.
+ *
+ * @param   Request Nb.
+ *
+ * @return  USB_UNSUPPORT or USB_SUCCESS.
+ */
+RESULT USBD_NoData_Setup(uint8_t RequestNo)
+{                                          
+  return USB_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      Virtual_Com_Port_GetLineCoding.
+ *
+ * @brief   send the linecoding structure to the PC host.
+ *
+ * @param   Length.
+ *
+ * @return  Linecoding structure base address.
+ */
+uint8_t *Virtual_Com_Port_GetLineCoding(uint16_t Length)
+{
+  return 0;
+}
+
+/*********************************************************************
+ * @fn      Virtual_Com_Port_SetLineCoding.
+ *
+ * @brief   Set the linecoding structure fields.
+ *
+ * @param   Length.
+ *
+ * @return  Linecoding structure base address.
+ */
+uint8_t *Virtual_Com_Port_SetLineCoding(uint16_t Length)
+{
+  return 0;
+}
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_prop.h

@@ -0,0 +1,67 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_prop.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : All processing related to Virtual COM Port Demo (Endpoint 0) 
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __usb_prop_H
+#define __usb_prop_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+#define USBD_GetConfiguration          NOP_Process
+//#define USBD_SetConfiguration          NOP_Process
+#define USBD_GetInterface              NOP_Process
+#define USBD_SetInterface              NOP_Process
+#define USBD_GetStatus                 NOP_Process
+#define USBD_ClearFeature              NOP_Process
+#define USBD_SetEndPointFeature        NOP_Process
+#define USBD_SetDeviceFeature          NOP_Process
+//#define USBD_SetDeviceAddress          NOP_Process
+
+#define SEND_ENCAPSULATED_COMMAND   0x00
+#define GET_ENCAPSULATED_RESPONSE   0x01
+#define SET_COMM_FEATURE            0x02
+#define GET_COMM_FEATURE            0x03
+#define CLEAR_COMM_FEATURE          0x04
+#define SET_LINE_CODING             0x20
+#define GET_LINE_CODING             0x21
+#define SET_CONTROL_LINE_STATE      0x22
+#define SEND_BREAK                  0x23
+
+
+void USBD_init(void);
+void USBD_Reset(void);
+void USBD_SetConfiguration(void);
+void USBD_SetDeviceAddress (void);
+void USBD_Status_In (void);
+void USBD_Status_Out (void);
+RESULT USBD_Data_Setup(uint8_t);
+RESULT USBD_NoData_Setup(uint8_t);
+RESULT USBD_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting);
+uint8_t *USBD_GetDeviceDescriptor(uint16_t );
+uint8_t *USBD_GetConfigDescriptor(uint16_t);
+uint8_t *USBD_GetStringDescriptor(uint16_t);
+        
+uint8_t *USBD_GetLineCoding(uint16_t Length);
+uint8_t *USBD_SetLineCoding(uint16_t Length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __usb_prop_H */
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_pwr.c

@@ -0,0 +1,214 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_pwr.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Connection/disconnection & power management
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+__IO uint32_t bDeviceState = UNCONNECTED; 
+__IO bool fSuspendEnabled = TRUE;  
+__IO uint32_t EP[8];
+
+struct
+{
+  __IO RESUME_STATE eState;
+  __IO uint8_t bESOFcnt;
+}
+ResumeS;
+
+__IO uint32_t remotewakeupon=0;
+
+/*********************************************************************
+ * @fn      PowerOn
+ *
+ * @brief   Enable power on.
+ *
+ * @return  USB_SUCCESS.
+ */
+RESULT PowerOn(void)
+{
+  uint16_t wRegVal;
+
+  wRegVal = CNTR_FRES;
+  _SetCNTR(wRegVal);
+  wInterrupt_Mask = 0;
+  _SetCNTR(wInterrupt_Mask);
+  _SetISTR(0);
+  wInterrupt_Mask = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM;
+  _SetCNTR(wInterrupt_Mask);
+  
+  return USB_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      PowerOff
+ *
+ * @brief   handles switch-off conditions
+ *
+ * @return  USB_SUCCESS.
+ */
+RESULT PowerOff()
+{
+  _SetCNTR(CNTR_FRES); 
+  _SetISTR(0); 
+  _SetCNTR(CNTR_FRES + CNTR_PDWN);
+
+  return USB_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      Suspend
+ *
+ * @brief   sets suspend mode operating conditions
+ *
+ * @return  USB_SUCCESS.
+ */
+void Suspend(void)
+{
+	uint32_t i =0;
+	uint16_t wCNTR; 
+  __IO uint32_t savePWR_CR=0;
+
+	wCNTR = _GetCNTR();  
+  for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+	
+	wCNTR|=CNTR_RESETM;
+	_SetCNTR(wCNTR);
+	
+	wCNTR|=CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	wCNTR&=~CNTR_FRES;
+	_SetCNTR(wCNTR);
+
+	while((_GetISTR()&ISTR_RESET) == 0);
+	
+	_SetISTR((uint16_t)CLR_RESET);
+	
+	for (i=0;i<8;i++)
+	_SetENDPOINT(i, EP[i]);
+	
+	wCNTR |= CNTR_FSUSP;
+	_SetCNTR(wCNTR);
+	
+	wCNTR = _GetCNTR();
+	wCNTR |= CNTR_LPMODE;
+	_SetCNTR(wCNTR);
+
+	Enter_LowPowerMode();
+}
+
+/*********************************************************************
+ * @fn      Resume_Init
+ *
+ * @brief   Handles wake-up restoring normal operations
+ *
+ * @return  USB_SUCCESS.
+ */
+void Resume_Init(void)
+{
+  uint16_t wCNTR;
+  
+  wCNTR = _GetCNTR();
+  wCNTR &= (~CNTR_LPMODE);
+  _SetCNTR(wCNTR);      
+  Leave_LowPowerMode();
+  _SetCNTR(IMR_MSK);
+}
+
+/*********************************************************************
+ * @fn      Resume
+ *
+ * @brief   This is the state machine handling resume operations and
+ *          timing sequence. The control is based on the Resume structure
+ *          variables and on the ESOF interrupt calling this subroutine
+ *          without changing machine state.
+ *
+ * @param   a state machine value (RESUME_STATE)
+ *         RESUME_ESOF doesn't change ResumeS.eState allowing
+ *         decrementing of the ESOF counter in different states.
+ *
+ * @return  none
+ */
+void Resume(RESUME_STATE eResumeSetVal)
+{
+  uint16_t wCNTR;
+
+  if (eResumeSetVal != RESUME_ESOF)
+	{
+   ResumeS.eState = eResumeSetVal;
+	}
+	
+  switch (ResumeS.eState)
+  {
+    case RESUME_EXTERNAL:
+      if (remotewakeupon ==0)
+      {
+        Resume_Init();
+        ResumeS.eState = RESUME_OFF;
+      }
+      else 
+      {
+        ResumeS.eState = RESUME_ON;
+      }
+      break;
+			
+    case RESUME_INTERNAL:
+      Resume_Init();
+      ResumeS.eState = RESUME_START;
+      remotewakeupon = 1;
+      break;
+		
+    case RESUME_LATER:
+      ResumeS.bESOFcnt = 2;
+      ResumeS.eState = RESUME_WAIT;
+      break;
+		
+    case RESUME_WAIT:
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+        ResumeS.eState = RESUME_START;
+      break;
+			
+    case RESUME_START:
+      wCNTR = _GetCNTR();
+      wCNTR |= CNTR_RESUME;
+      _SetCNTR(wCNTR);
+      ResumeS.eState = RESUME_ON;
+      ResumeS.bESOFcnt = 10;
+      break;
+		
+    case RESUME_ON:    
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+      {
+        wCNTR = _GetCNTR();
+        wCNTR &= (~CNTR_RESUME);
+        _SetCNTR(wCNTR);
+        ResumeS.eState = RESUME_OFF;
+        remotewakeupon = 0;
+      }
+      break;
+			
+    case RESUME_OFF:
+			
+    case RESUME_ESOF:
+			
+    default:
+      ResumeS.eState = RESUME_OFF;
+      break;
+  }
+}
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/CONFIG/usb_pwr.h

@@ -0,0 +1,60 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_pwr.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Connection/disconnection & power management header 
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_PWR_H
+#define __USB_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+	 
+#include "ch32f10x.h"
+typedef enum _RESUME_STATE
+{
+  RESUME_EXTERNAL,
+  RESUME_INTERNAL,
+  RESUME_LATER,
+  RESUME_WAIT,
+  RESUME_START,
+  RESUME_ON,
+  RESUME_OFF,
+  RESUME_ESOF
+} RESUME_STATE;
+
+typedef enum _DEVICE_STATE
+{
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+} DEVICE_STATE;
+
+
+void Suspend(void);
+void Resume_Init(void);
+void Resume(RESUME_STATE eResumeSetVal);
+RESULT PowerOn(void);
+RESULT PowerOff(void);
+
+extern  __IO uint32_t bDeviceState; /* USB device status */
+extern __IO bool fSuspendEnabled;  /* true when suspend is possible */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*__USB_PWR_H*/
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_core.h

@@ -0,0 +1,189 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_core.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB cor firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_CORE_H
+#define __USB_CORE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+	 
+typedef enum _CONTROL_STATE
+{
+  WAIT_SETUP,       /* 0 */
+  SETTING_UP,       /* 1 */
+  IN_DATA,          /* 2 */
+  OUT_DATA,         /* 3 */
+  LAST_IN_DATA,     /* 4 */
+  LAST_OUT_DATA,    /* 5 */
+  WAIT_STATUS_IN,   /* 7 */
+  WAIT_STATUS_OUT,  /* 8 */
+  STALLED,          /* 9 */
+  PAUSE             /* 10 */
+} CONTROL_STATE;    /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+  uint8_t *Descriptor;
+  uint16_t Descriptor_Size;
+}
+ONE_DESCRIPTOR, *PONE_DESCRIPTOR;
+
+typedef enum _RESULT
+{
+  USB_SUCCESS = 0,    /* Process successfully */
+  USB_ERROR,
+  USB_UNSUPPORT,
+  USB_NOT_READY       /* The process has not been finished, endpoint will be
+                         NAK to further request */
+} RESULT;
+
+
+/* Definitions for endpoint level */
+typedef struct _ENDPOINT_INFO
+{
+  uint16_t  Usb_wLength;
+  uint16_t  Usb_wOffset;
+  uint16_t  PacketSize;
+  uint8_t   *(*CopyData)(uint16_t Length);
+}ENDPOINT_INFO;
+
+/* Definitions for device level */
+typedef struct _DEVICE
+{
+  uint8_t Total_Endpoint;     /* Number of endpoints that are used */
+  uint8_t Total_Configuration;/* Number of configuration available */
+}
+DEVICE;
+
+typedef union
+{
+  uint16_t w;
+  struct BW
+  {
+    uint8_t bb1;
+    uint8_t bb0;
+  }
+  bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+  uint8_t USBbmRequestType;       /* bmRequestType */
+  uint8_t USBbRequest;            /* bRequest */
+  uint16_t_uint8_t USBwValues;         /* wValue */
+  uint16_t_uint8_t USBwIndexs;         /* wIndex */
+  uint16_t_uint8_t USBwLengths;        /* wLength */
+
+  uint8_t ControlState;           /* of type CONTROL_STATE */
+  uint8_t Current_Feature;
+  uint8_t Current_Configuration;   /* Selected configuration */
+  uint8_t Current_Interface;       /* Selected interface of current configuration */
+  uint8_t Current_AlternateSetting;/* Selected Alternate Setting of current
+                                     interface*/
+
+  ENDPOINT_INFO Ctrl_Info;
+}DEVICE_INFO;
+
+typedef struct _DEVICE_PROP
+{
+  void (*Init)(void);        /* Initialize the device */
+  void (*Reset)(void);       /* Reset routine of this device */
+  void (*Process_Status_IN)(void);
+  void (*Process_Status_OUT)(void);
+
+  RESULT (*Class_Data_Setup)(uint8_t RequestNo);
+
+  RESULT (*Class_NoData_Setup)(uint8_t RequestNo);
+
+  RESULT  (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+  uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+  uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+  uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+  void* RxEP_buffer;
+   
+  uint8_t MaxPacketSize;
+
+}DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+  void (*User_GetConfiguration)(void);       /* Get Configuration */
+  void (*User_SetConfiguration)(void);       /* Set Configuration */
+  void (*User_GetInterface)(void);           /* Get Interface */
+  void (*User_SetInterface)(void);           /* Set Interface */
+  void (*User_GetStatus)(void);              /* Get Status */
+  void (*User_ClearFeature)(void);           /* Clear Feature */
+  void (*User_SetEndPointFeature)(void);     /* Set Endpoint Feature */
+  void (*User_SetDeviceFeature)(void);       /* Set Device Feature */
+  void (*User_SetDeviceAddress)(void);       /* Set Device Address */
+}
+USER_STANDARD_REQUESTS;
+
+
+#define Type_Recipient (pInformation->USBbmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue USBwValues.w
+#define USBwValue0 USBwValues.bw.bb0
+#define USBwValue1 USBwValues.bw.bb1
+#define USBwIndex USBwIndexs.w
+#define USBwIndex0 USBwIndexs.bw.bb0
+#define USBwIndex1 USBwIndexs.bw.bb1
+#define USBwLength USBwLengths.w
+#define USBwLength0 USBwLengths.bw.bb0
+#define USBwLength1 USBwLengths.bw.bb1
+
+
+uint8_t Setup0_Process(void);
+uint8_t Post0_Process(void);
+uint8_t Out0_Process(void);
+uint8_t In0_Process(void);
+
+RESULT Standard_SetEndPointFeature(void);
+RESULT Standard_SetDeviceFeature(void);
+
+uint8_t *Standard_GetConfiguration(uint16_t Length);
+RESULT Standard_SetConfiguration(void);
+uint8_t *Standard_GetInterface(uint16_t Length);
+RESULT Standard_SetInterface(void);
+uint8_t *Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t *Standard_GetStatus(uint16_t Length);
+RESULT Standard_ClearFeature(void);
+void SetDeviceAddress(uint8_t);
+void NOP_Process(void);
+
+extern DEVICE_PROP Device_Property;
+extern  USER_STANDARD_REQUESTS User_Standard_Requests;
+extern  DEVICE  Device_Table;
+extern DEVICE_INFO Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_CORE_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_def.h

@@ -0,0 +1,80 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_def.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB definition firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_DEF_H
+#define __USB_DEF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+typedef enum _RECIPIENT_TYPE
+{
+  DEVICE_RECIPIENT,     
+  INTERFACE_RECIPIENT,  
+  ENDPOINT_RECIPIENT,   
+  OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+typedef enum _STANDARD_REQUESTS
+{
+  GET_STATUS = 0,
+  CLEAR_FEATURE,
+  RESERVED1,
+  SET_FEATURE,
+  RESERVED2,
+  SET_ADDRESS,
+  GET_DESCRIPTOR,
+  SET_DESCRIPTOR,
+  GET_CONFIGURATION,
+  SET_CONFIGURATION,
+  GET_INTERFACE,
+  SET_INTERFACE,
+  TOTAL_sREQUEST,  
+  SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+  DEVICE_DESCRIPTOR = 1,
+  CONFIG_DESCRIPTOR,
+  STRING_DESCRIPTOR,
+  INTERFACE_DESCRIPTOR,
+  ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLEAR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+  ENDPOINT_STALL,
+  DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Definition of "USBbmRequestType" */
+#define REQUEST_TYPE      0x60  
+#define STANDARD_REQUEST  0x00  
+#define CLASS_REQUEST     0x20 
+#define VENDOR_REQUEST    0x40  
+#define RECIPIENT         0x1F  
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_DEF_H */
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_init.h

@@ -0,0 +1,40 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_init.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB Initialization firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_INIT_H
+#define __USB_INIT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+	 
+#include "ch32f10x.h"
+
+	 
+void USB_Init(void);
+extern uint8_t	EPindex;
+extern DEVICE_INFO*	pInformation;
+extern DEVICE_PROP*	pProperty;
+extern USER_STANDARD_REQUESTS *pUser_Standard_Requests;
+extern uint16_t	SaveState ;
+extern uint16_t wInterrupt_Mask;
+
+#ifdef __cplusplus
+}
+
+#endif
+
+
+#endif /* __USB_INIT_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_int.h

@@ -0,0 +1,23 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_int.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB Endpoint firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_INT_H
+#define __USB_INT_H
+
+void CTR_LP(void);
+void CTR_HP(void);
+
+#endif /* __USB_INT_H */
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_lib.h

@@ -0,0 +1,28 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_lib.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Library configuration file for USB.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_LIB_H
+#define __USB_LIB_H
+
+#include "hw_config.h"
+#include "usb_type.h"
+#include "usb_regs.h"
+#include "usb_def.h"
+#include "usb_core.h"
+#include "usb_init.h"
+#include "usb_sil.h"
+#include "usb_mem.h"
+#include "usb_int.h"
+#include "ch32f10x_usb.h"
+
+#endif /* __USB_LIB_H */
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_mem.h

@@ -0,0 +1,34 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_mem.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB Initialization firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_MEM_H
+#define __USB_MEM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*__USB_MEM_H*/
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_regs.h

@@ -0,0 +1,641 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_regs.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB cell registers firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_REGS_H
+#define __USB_REGS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+	 
+typedef enum _EP_DBUF_DIR
+{
+  EP_DBUF_ERR,
+  EP_DBUF_OUT,
+  EP_DBUF_IN
+}EP_DBUF_DIR;
+
+/* endpoint buffer number */
+enum EP_BUF_NUM
+{
+  EP_NOBUF,
+  EP_BUF0,
+  EP_BUF1
+};
+
+#define RegBase  (0x40005C00L)  
+#define PMAAddr  (0x40006000L)  
+
+/******************************************************************************/
+/*                         General registers                                  */
+/******************************************************************************/
+
+/* Control register */
+#define CNTLR    ((__IO unsigned *)(RegBase + 0x40))
+/* Interrupt status register */
+#define ISTR    ((__IO unsigned *)(RegBase + 0x44))
+/* Frame number register */
+#define FNR     ((__IO unsigned *)(RegBase + 0x48))
+/* Device address register */
+#define DADDR   ((__IO unsigned *)(RegBase + 0x4C))
+/* Buffer Table address register */
+#define BTABLE  ((__IO unsigned *)(RegBase + 0x50))
+/******************************************************************************/
+/*                         Endpoint registers                                 */
+/******************************************************************************/
+#define EP0REG  ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */
+
+/* Endpoint Addresses (w/direction) */
+#define EP0_OUT     ((uint8_t)0x00)  
+#define EP0_IN      ((uint8_t)0x80) 
+#define EP1_OUT     ((uint8_t)0x01)  
+#define EP1_IN      ((uint8_t)0x81)  
+#define EP2_OUT     ((uint8_t)0x02)  
+#define EP2_IN      ((uint8_t)0x82)  
+#define EP3_OUT     ((uint8_t)0x03)  
+#define EP3_IN      ((uint8_t)0x83) 
+#define EP4_OUT     ((uint8_t)0x04)  
+#define EP4_IN      ((uint8_t)0x84)
+#define EP5_OUT     ((uint8_t)0x05)  
+#define EP5_IN      ((uint8_t)0x85)
+#define EP6_OUT     ((uint8_t)0x06)  
+#define EP6_IN      ((uint8_t)0x86)
+#define EP7_OUT     ((uint8_t)0x07)  
+#define EP7_IN      ((uint8_t)0x87)
+
+/* endpoints enumeration */
+#define ENDP0       ((uint8_t)0)
+#define ENDP1       ((uint8_t)1)
+#define ENDP2       ((uint8_t)2)
+#define ENDP3       ((uint8_t)3)
+#define ENDP4       ((uint8_t)4)
+#define ENDP5       ((uint8_t)5)
+#define ENDP6       ((uint8_t)6)
+#define ENDP7       ((uint8_t)7)
+
+/******************************************************************************/
+/*                       ISTR interrupt events                                */
+/******************************************************************************/
+#define ISTR_CTR    (0x8000) /* Correct TRansfer (clear-only bit) */
+#define ISTR_DOVR   (0x4000) /* DMA OVeR/underrun (clear-only bit) */
+#define ISTR_ERR    (0x2000) /* ERRor (clear-only bit) */
+#define ISTR_WKUP   (0x1000) /* WaKe UP (clear-only bit) */
+#define ISTR_SUSP   (0x0800) /* SUSPend (clear-only bit) */
+#define ISTR_RESET  (0x0400) /* RESET (clear-only bit) */
+#define ISTR_SOF    (0x0200) /* Start Of Frame (clear-only bit) */
+#define ISTR_ESOF   (0x0100) /* Expected Start Of Frame (clear-only bit) */
+
+
+#define ISTR_DIR    (0x0010)  /* DIRection of transaction (read-only bit)  */
+#define ISTR_EP_ID  (0x000F)  /* EndPoint IDentifier (read-only bit)  */
+
+#define CLR_CTR    (~ISTR_CTR)   /* clear Correct TRansfer bit */
+#define CLR_DOVR   (~ISTR_DOVR)  /* clear DMA OVeR/underrun bit*/
+#define CLR_ERR    (~ISTR_ERR)   /* clear ERRor bit */
+#define CLR_WKUP   (~ISTR_WKUP)  /* clear WaKe UP bit     */
+#define CLR_SUSP   (~ISTR_SUSP)  /* clear SUSPend bit     */
+#define CLR_RESET  (~ISTR_RESET) /* clear RESET bit      */
+#define CLR_SOF    (~ISTR_SOF)   /* clear Start Of Frame bit   */
+#define CLR_ESOF   (~ISTR_ESOF)  /* clear Expected Start Of Frame bit */
+
+/******************************************************************************/
+/*             CNTR control register bits definitions                         */
+/******************************************************************************/
+#define CNTR_CTRM   (0x8000) /* Correct TRansfer Mask */
+#define CNTR_DOVRM  (0x4000) /* DMA OVeR/underrun Mask */
+#define CNTR_ERRM   (0x2000) /* ERRor Mask */
+#define CNTR_WKUPM  (0x1000) /* WaKe UP Mask */
+#define CNTR_SUSPM  (0x0800) /* SUSPend Mask */
+#define CNTR_RESETM (0x0400) /* RESET Mask   */
+#define CNTR_SOFM   (0x0200) /* Start Of Frame Mask */
+#define CNTR_ESOFM  (0x0100) /* Expected Start Of Frame Mask */
+
+
+#define CNTR_RESUME (0x0010) /* RESUME request */
+#define CNTR_FSUSP  (0x0008) /* Force SUSPend */
+#define CNTR_LPMODE (0x0004) /* Low-power MODE */
+#define CNTR_PDWN   (0x0002) /* Power DoWN */
+#define CNTR_FRES   (0x0001) /* Force USB RESet */
+
+/******************************************************************************/
+/*                FNR Frame Number Register bit definitions                   */
+/******************************************************************************/
+#define FNR_RXDP    (0x8000) /* status of D+ data line */
+#define FNR_RXDM    (0x4000) /* status of D- data line */
+#define FNR_LCK     (0x2000) /* LoCKed */
+#define FNR_LSOF    (0x1800) /* Lost SOF */
+#define FNR_FN      (0x07FF) /* Frame Number */
+/******************************************************************************/
+/*               DADDR Device ADDRess bit definitions                         */
+/******************************************************************************/
+#define DADDR_EF    (0x80)
+#define DADDR_ADD   (0x7F)
+/******************************************************************************/
+/*                            Endpoint register                               */
+/******************************************************************************/
+/* bit positions */
+#define EP_CTR_RX      (0x8000) /* EndPoint Correct TRansfer RX */
+#define EP_DTOG_RX     (0x4000) /* EndPoint Data TOGGLE RX */
+#define EPRX_STAT      (0x3000) /* EndPoint RX STATus bit field */
+#define EP_SETUP       (0x0800) /* EndPoint SETUP */
+#define EP_T_FIELD     (0x0600) /* EndPoint TYPE */
+#define EP_KIND        (0x0100) /* EndPoint KIND */
+#define EP_CTR_TX      (0x0080) /* EndPoint Correct TRansfer TX */
+#define EP_DTOG_TX     (0x0040) /* EndPoint Data TOGGLE TX */
+#define EPTX_STAT      (0x0030) /* EndPoint TX STATus bit field */
+#define EPADDR_FIELD   (0x000F) /* EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define EPREG_MASK     (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD)
+
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_TYPE_MASK   (0x0600) /* EndPoint TYPE Mask */
+#define EP_BULK        (0x0000) /* EndPoint BULK */
+#define EP_CONTROL     (0x0200) /* EndPoint CONTROL */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT */
+#define EP_T_MASK      (~EP_T_FIELD & EPREG_MASK)
+
+
+/* EP_KIND EndPoint KIND */
+#define EPKIND_MASK    (~EP_KIND & EPREG_MASK)
+
+/* STAT_TX[1:0] STATus for TX transfer */
+#define EP_TX_DIS      (0x0000) /* EndPoint TX DISabled */
+#define EP_TX_STALL    (0x0010) /* EndPoint TX STALLed */
+#define EP_TX_NAK      (0x0020) /* EndPoint TX NAKed */
+#define EP_TX_VALID    (0x0030) /* EndPoint TX VALID */
+#define EPTX_DTOG1     (0x0010) /* EndPoint TX Data TOGgle bit1 */
+#define EPTX_DTOG2     (0x0020) /* EndPoint TX Data TOGgle bit2 */
+#define EPTX_DTOGMASK  (EPTX_STAT|EPREG_MASK)
+
+/* STAT_RX[1:0] STATus for RX transfer */
+#define EP_RX_DIS      (0x0000) /* EndPoint RX DISabled */
+#define EP_RX_STALL    (0x1000) /* EndPoint RX STALLed */
+#define EP_RX_NAK      (0x2000) /* EndPoint RX NAKed */
+#define EP_RX_VALID    (0x3000) /* EndPoint RX VALID */
+#define EPRX_DTOG1     (0x1000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DTOG2     (0x2000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DTOGMASK  (EPRX_STAT|EPREG_MASK)
+
+/* SetCNTR */
+#define _SetCNTR(wRegValue)  (*CNTLR   = (uint16_t)wRegValue)
+
+/* SetISTR */
+#define _SetISTR(wRegValue)  (*ISTR   = (uint16_t)wRegValue)
+
+/* SetDADDR */
+#define _SetDADDR(wRegValue) (*DADDR  = (uint16_t)wRegValue)
+
+/* SetBTABLE */
+#define _SetBTABLE(wRegValue)(*BTABLE = (uint16_t)(wRegValue & 0xFFF8))
+
+/* GetCNTR */
+#define _GetCNTR()   ((uint16_t) *CNTLR)
+
+/* GetISTR */
+#define _GetISTR()   ((uint16_t) *ISTR)
+
+/* GetFNR */
+#define _GetFNR()    ((uint16_t) *FNR)
+
+/* GetDADDR */
+#define _GetDADDR()  ((uint16_t) *DADDR)
+
+/* GetBTABLE */
+#define _GetBTABLE() ((uint16_t) *BTABLE)
+
+/* SetENDPOINT */
+#define _SetENDPOINT(bEpNum,wRegValue)  (*(EP0REG + bEpNum)= \
+    (uint16_t)wRegValue)
+
+/* GetENDPOINT */
+#define _GetENDPOINT(bEpNum)        ((uint16_t)(*(EP0REG + bEpNum)))
+
+#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
+                                  ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType )))
+
+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
+
+/*******************************************************************************
+* Macro Name     : SetEPTxStatus
+* Description    : sets the status for tx transfer (bits STAT_TX[1:0]).
+* Input          : bEpNum: Endpoint Number. 
+*                  wState: new state
+* Return         : None.
+*******************************************************************************/
+#define _SetEPTxStatus(bEpNum,wState) {\
+    register uint16_t _wRegVal;       \
+    _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\
+    /* toggle first bit ? */     \
+    if((EPTX_DTOG1 & wState)!= 0)      \
+      _wRegVal ^= EPTX_DTOG1;        \
+    /* toggle second bit ?  */         \
+    if((EPTX_DTOG2 & wState)!= 0)      \
+      _wRegVal ^= EPTX_DTOG2;        \
+    _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX));    \
+  } /* _SetEPTxStatus */
+
+/*******************************************************************************
+* Macro Name     : SetEPRxStatus
+* Description    : sets the status for rx transfer (bits STAT_TX[1:0])
+* Input          : bEpNum: Endpoint Number. 
+*                  wState: new state.
+* Return         : None.
+*******************************************************************************/
+#define _SetEPRxStatus(bEpNum,wState) {\
+    register uint16_t _wRegVal;   \
+    \
+    _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\
+    /* toggle first bit ? */  \
+    if((EPRX_DTOG1 & wState)!= 0) \
+      _wRegVal ^= EPRX_DTOG1;  \
+    /* toggle second bit ? */  \
+    if((EPRX_DTOG2 & wState)!= 0) \
+      _wRegVal ^= EPRX_DTOG2;  \
+    _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
+  } /* _SetEPRxStatus */
+
+/*******************************************************************************
+* Macro Name     : SetEPRxTxStatus
+* Description    : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+* Input          : bEpNum: Endpoint Number. 
+*                  wStaterx: new state.
+*                  wStatetx: new state.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+#define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\
+    register uint32_t _wRegVal;   \
+    \
+    _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\
+    /* toggle first bit ? */  \
+    if((EPRX_DTOG1 & wStaterx)!= 0) \
+      _wRegVal ^= EPRX_DTOG1;  \
+    /* toggle second bit ? */  \
+    if((EPRX_DTOG2 & wStaterx)!= 0) \
+      _wRegVal ^= EPRX_DTOG2;  \
+    /* toggle first bit ? */     \
+    if((EPTX_DTOG1 & wStatetx)!= 0)      \
+      _wRegVal ^= EPTX_DTOG1;        \
+    /* toggle second bit ?  */         \
+    if((EPTX_DTOG2 & wStatetx)!= 0)      \
+      _wRegVal ^= EPTX_DTOG2;        \
+    _SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX);    \
+  } /* _SetEPRxTxStatus */
+
+/*******************************************************************************
+* Macro Name     : GetEPTxStatus / GetEPRxStatus 
+* Description    : gets the status for tx/rx transfer (bits STAT_TX[1:0]
+*                  /STAT_RX[1:0])
+* Input          : bEpNum: Endpoint Number. 
+* Return         : status .
+*******************************************************************************/
+#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STAT)
+
+#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STAT)
+
+/*******************************************************************************
+* Macro Name     : SetEPTxValid / SetEPRxValid 
+* Description    : sets directly the VALID tx/rx-status into the enpoint register
+* Input          : bEpNum: Endpoint Number. 
+* Return         : None.
+*******************************************************************************/
+#define _SetEPTxValid(bEpNum)     (_SetEPTxStatus(bEpNum, EP_TX_VALID))
+
+#define _SetEPRxValid(bEpNum)     (_SetEPRxStatus(bEpNum, EP_RX_VALID))
+
+/*******************************************************************************
+* Macro Name     : GetTxStallStatus / GetRxStallStatus.
+* Description    : checks stall condition in an endpoint.
+* Input          : bEpNum: Endpoint Number. 
+* Return         : TRUE = endpoint in stall condition.
+*******************************************************************************/
+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \
+                                   == EP_TX_STALL)
+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \
+                                   == EP_RX_STALL)
+
+/*******************************************************************************
+* Macro Name     : SetEP_KIND / ClearEP_KIND.
+* Description    : set & clear EP_KIND bit.
+* Input          : bEpNum: Endpoint Number. 
+* Return         : None.
+*******************************************************************************/
+#define _SetEP_KIND(bEpNum)    (_SetENDPOINT(bEpNum, \
+                                (EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
+#define _ClearEP_KIND(bEpNum)  (_SetENDPOINT(bEpNum, \
+                                (EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK))))
+
+/*******************************************************************************
+* Macro Name     : Set_Status_Out / Clear_Status_Out.
+* Description    : Sets/clears directly STATUS_OUT bit in the endpoint register.
+* Input          : bEpNum: Endpoint Number. 
+* Return         : None.
+*******************************************************************************/
+#define _Set_Status_Out(bEpNum)    _SetEP_KIND(bEpNum)
+#define _Clear_Status_Out(bEpNum)  _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+* Macro Name     : SetEPDoubleBuff / ClearEPDoubleBuff.
+* Description    : Sets/clears directly EP_KIND bit in the endpoint register.
+* Input          : bEpNum: Endpoint Number. 
+* Return         : None.
+*******************************************************************************/
+#define _SetEPDoubleBuff(bEpNum)   _SetEP_KIND(bEpNum)
+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+* Macro Name     : ClearEP_CTR_RX / ClearEP_CTR_TX.
+* Description    : Clears bit CTR_RX / CTR_TX in the endpoint register.
+* Input          : bEpNum: Endpoint Number. 
+* Return         : None.
+*******************************************************************************/
+#define _ClearEP_CTR_RX(bEpNum)   (_SetENDPOINT(bEpNum,\
+                                   _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
+#define _ClearEP_CTR_TX(bEpNum)   (_SetENDPOINT(bEpNum,\
+                                   _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
+
+/*******************************************************************************
+* Macro Name     : ToggleDTOG_RX / ToggleDTOG_TX .
+* Description    : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+* Input          : bEpNum: Endpoint Number. 
+* Return         : None.
+*******************************************************************************/
+#define _ToggleDTOG_RX(bEpNum)    (_SetENDPOINT(bEpNum, \
+                                   EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+#define _ToggleDTOG_TX(bEpNum)    (_SetENDPOINT(bEpNum, \
+                                   EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+
+/*******************************************************************************
+* Macro Name     : ClearDTOG_RX / ClearDTOG_TX.
+* Description    : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+* Input          : bEpNum: Endpoint Number. 
+* Return         : None.
+*******************************************************************************/
+#define _ClearDTOG_RX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\
+    _ToggleDTOG_RX(bEpNum)
+#define _ClearDTOG_TX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\
+    _ToggleDTOG_TX(bEpNum)
+/*******************************************************************************
+* Macro Name     : SetEPAddress.
+* Description    : Sets address in an endpoint register.
+* Input          : bEpNum: Endpoint Number.
+*                  bAddr: Address. 
+* Return         : None.
+*******************************************************************************/
+#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
+    EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
+
+/*******************************************************************************
+* Macro Name     : GetEPAddress.
+* Description    : Gets address in an endpoint register.
+* Input          : bEpNum: Endpoint Number.
+* Return         : None.
+*******************************************************************************/
+#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
+
+#define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8  )*2 + PMAAddr))
+#define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr))
+#define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr))
+#define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr))
+
+/*******************************************************************************
+* Macro Name     : SetEPTxAddr / SetEPRxAddr.
+* Description    : sets address of the tx/rx buffer.
+* Input          : bEpNum: Endpoint Number.
+*                  wAddr: address to be set (must be word aligned).
+* Return         : None.
+*******************************************************************************/
+#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
+#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
+
+/*******************************************************************************
+* Macro Name     : GetEPTxAddr / GetEPRxAddr.
+* Description    : Gets address of the tx/rx buffer.
+* Input          : bEpNum: Endpoint Number.
+* Return         : address of the buffer.
+*******************************************************************************/
+#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
+#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
+
+/*******************************************************************************
+* Macro Name     : SetEPCountRxReg.
+* Description    : Sets counter of rx buffer with no. of blocks.
+* Input          : pdwReg: pointer to counter.
+*                  wCount: Counter.
+* Return         : None.
+*******************************************************************************/
+#define _BlocksOf32(dwReg,wCount,wNBlocks) {\
+    wNBlocks = wCount >> 5;\
+    if((wCount & 0x1f) == 0)\
+      wNBlocks--;\
+    *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\
+  }/* _BlocksOf32 */
+
+#define _BlocksOf2(dwReg,wCount,wNBlocks) {\
+    wNBlocks = wCount >> 1;\
+    if((wCount & 0x1) != 0)\
+      wNBlocks++;\
+    *pdwReg = (uint32_t)(wNBlocks << 10);\
+  }/* _BlocksOf2 */
+
+#define _SetEPCountRxReg(dwReg,wCount)  {\
+    uint16_t wNBlocks;\
+    if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\
+    else {_BlocksOf2(dwReg,wCount,wNBlocks);}\
+  }/* _SetEPCountRxReg */
+
+
+
+#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\
+    uint32_t *pdwReg = _pEPTxCount(bEpNum); \
+    _SetEPCountRxReg(pdwReg, wCount);\
+  }
+
+/*******************************************************************************
+* Macro Name     : SetEPTxCount / SetEPRxCount.
+* Description    : sets counter for the tx/rx buffer.
+* Input          : bEpNum: endpoint number.
+*                  wCount: Counter value.
+* Return         : None.
+*******************************************************************************/
+#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)
+#define _SetEPRxCount(bEpNum,wCount) {\
+    uint32_t *pdwReg = _pEPRxCount(bEpNum); \
+    _SetEPCountRxReg(pdwReg, wCount);\
+  }
+
+/*******************************************************************************
+* Macro Name     : GetEPTxCount / GetEPRxCount.
+* Description    : gets counter of the tx buffer.
+* Input          : bEpNum: endpoint number.
+* Return         : Counter value.
+*******************************************************************************/
+#define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
+#define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
+
+/*******************************************************************************
+* Macro Name     : SetEPDblBuf0Addr / SetEPDblBuf1Addr.
+* Description    : Sets buffer 0/1 address in a double buffer endpoint.
+* Input          : bEpNum: endpoint number.
+*                : wBuf0Addr: buffer 0 address.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}
+#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}
+
+/*******************************************************************************
+* Macro Name     : SetEPDblBuffAddr.
+* Description    : Sets addresses in a double buffer endpoint.
+* Input          : bEpNum: endpoint number.
+*                : wBuf0Addr: buffer 0 address.
+*                : wBuf1Addr = buffer 1 address.
+* Return         : None.
+*******************************************************************************/
+#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \
+    _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\
+    _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\
+  } /* _SetEPDblBuffAddr */
+
+/*******************************************************************************
+* Macro Name     : GetEPDblBuf0Addr / GetEPDblBuf1Addr.
+* Description    : Gets buffer 0/1 address of a double buffer endpoint.
+* Input          : bEpNum: endpoint number.
+* Return         : None.
+*******************************************************************************/
+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
+
+/*******************************************************************************
+* Macro Name     : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count.
+* Description    : Gets buffer 0/1 address of a double buffer endpoint.
+* Input          : bEpNum: endpoint number.
+*                : bDir: endpoint dir  EP_DBUF_OUT = OUT 
+*                                      EP_DBUF_IN  = IN 
+*                : wCount: Counter value    
+* Return         : None.
+*******************************************************************************/
+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount)  { \
+    if(bDir == EP_DBUF_OUT)\
+      /* OUT endpoint */ \
+    {_SetEPRxDblBuf0Count(bEpNum,wCount);} \
+    else if(bDir == EP_DBUF_IN)\
+      /* IN endpoint */ \
+      *_pEPTxCount(bEpNum) = (uint32_t)wCount;  \
+  } /* SetEPDblBuf0Count*/
+
+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount)  { \
+    if(bDir == EP_DBUF_OUT)\
+      /* OUT endpoint */ \
+    {_SetEPRxCount(bEpNum,wCount);}\
+    else if(bDir == EP_DBUF_IN)\
+      /* IN endpoint */\
+      *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
+  } /* SetEPDblBuf1Count */
+
+#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\
+    _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
+    _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
+  } /* _SetEPDblBuffCount  */
+
+/*******************************************************************************
+* Macro Name     : GetEPDblBuf0Count / GetEPDblBuf1Count.
+* Description    : Gets buffer 0/1 rx/tx counter for double buffering.
+* Input          : bEpNum: endpoint number.
+* Return         : None.
+*******************************************************************************/
+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
+
+	
+extern __IO uint16_t wIstr;  /* ISTR register last read value */
+
+
+void SetCNTR(uint16_t /*wRegValue*/);
+void SetISTR(uint16_t /*wRegValue*/);
+void SetDADDR(uint16_t /*wRegValue*/);
+void SetBTABLE(uint16_t /*wRegValue*/);
+void SetBTABLE(uint16_t /*wRegValue*/);
+uint16_t GetCNTR(void);
+uint16_t GetISTR(void);
+uint16_t GetFNR(void);
+uint16_t GetDADDR(void);
+uint16_t GetBTABLE(void);
+void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
+uint16_t GetENDPOINT(uint8_t /*bEpNum*/);
+void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
+uint16_t GetEPType(uint8_t /*bEpNum*/);
+void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir);
+uint16_t GetEPTxStatus(uint8_t /*bEpNum*/);
+uint16_t GetEPRxStatus(uint8_t /*bEpNum*/);
+void SetEPTxValid(uint8_t /*bEpNum*/);
+void SetEPRxValid(uint8_t /*bEpNum*/);
+uint16_t GetTxStallStatus(uint8_t /*bEpNum*/);
+uint16_t GetRxStallStatus(uint8_t /*bEpNum*/);
+void SetEP_KIND(uint8_t /*bEpNum*/);
+void ClearEP_KIND(uint8_t /*bEpNum*/);
+void Set_Status_Out(uint8_t /*bEpNum*/);
+void Clear_Status_Out(uint8_t /*bEpNum*/);
+void SetEPDoubleBuff(uint8_t /*bEpNum*/);
+void ClearEPDoubleBuff(uint8_t /*bEpNum*/);
+void ClearEP_CTR_RX(uint8_t /*bEpNum*/);
+void ClearEP_CTR_TX(uint8_t /*bEpNum*/);
+void ToggleDTOG_RX(uint8_t /*bEpNum*/);
+void ToggleDTOG_TX(uint8_t /*bEpNum*/);
+void ClearDTOG_RX(uint8_t /*bEpNum*/);
+void ClearDTOG_TX(uint8_t /*bEpNum*/);
+void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
+uint8_t GetEPAddress(uint8_t /*bEpNum*/);
+void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+uint16_t GetEPTxAddr(uint8_t /*bEpNum*/);
+uint16_t GetEPRxAddr(uint8_t /*bEpNum*/);
+void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/);
+void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+uint16_t GetEPTxCount(uint8_t /*bEpNum*/);
+uint16_t GetEPRxCount(uint8_t /*bEpNum*/);
+void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
+void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
+void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
+uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/);
+uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/);
+void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/);
+uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/);
+EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
+void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir);
+uint16_t ToWord(uint8_t, uint8_t);
+uint16_t ByteSwap(uint16_t);
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* __USB_REGS_H */
+
+
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_sil.h

@@ -0,0 +1,34 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_sil.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB Simplified Interface Layer firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_SIL_H
+#define __USB_SIL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32f10x.h"
+
+uint32_t USB_SIL_Init(void);
+uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
+uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer);
+	 
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* __USB_SIL_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/inc/usb_type.h

@@ -0,0 +1,31 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_type.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : This file contains all the functions prototypes for the  
+ *                      USB types firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __USB_TYPE_H
+#define __USB_TYPE_H
+#include "debug.h"
+#include "usb_conf.h"
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+typedef enum
+{
+  FALSE = 0, TRUE  = !FALSE
+}
+bool;
+
+#endif /* __USB_TYPE_H */
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/src/usb_core.c

@@ -0,0 +1,949 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_core.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Standard protocol processing (USB v2.0)
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+
+/* Global define */
+#define ValBit(VAR,Place)    (VAR & (1 << Place))
+#define SetBit(VAR,Place)    (VAR |= (1 << Place))
+#define ClrBit(VAR,Place)    (VAR &= ((1 << Place) ^ 255))
+#define Send0LengthData() { _SetEPTxCount(ENDP0, 0); \
+    vSetEPTxStatus(EP_TX_VALID); \
+  }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn() Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 
+#define StatusInfo1 StatusInfo.bw.bb0
+
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = FALSE;
+
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+
+/*********************************************************************
+ * @fn      Standard_GetConfiguration.
+ *
+ * @brief   Return the current configuration variable address.
+ *
+ * @param   Length - How many bytes are needed.
+ *
+ * @return  Return 1 - if the request is invalid when "Length" is 0.
+ *           Return "Buffer" if the "Length" is not 0.
+ */	
+uint8_t *Standard_GetConfiguration(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->Current_Configuration);
+    return 0;
+  }
+  pUser_Standard_Requests->User_GetConfiguration();
+	
+  return (uint8_t *)&pInformation->Current_Configuration;
+}
+
+/*********************************************************************
+ * @fn      Standard_SetConfiguration.
+ *
+ * @brief   This routine is called to set the configuration value
+ *          Then each class should configure device itself.
+ *
+ * @return  Return USB_SUCCESS - if the request is performed.
+ *           Return USB_UNSUPPORT - if the request is invalid.
+ */
+RESULT Standard_SetConfiguration(void)
+{
+  if ((pInformation->USBwValue0 <=
+      Device_Table.Total_Configuration) && (pInformation->USBwValue1 == 0)
+      && (pInformation->USBwIndex == 0)) 
+  {
+    pInformation->Current_Configuration = pInformation->USBwValue0;
+    pUser_Standard_Requests->User_SetConfiguration();
+    return USB_SUCCESS;
+  }
+  else
+  {
+    return USB_UNSUPPORT;
+  }
+}
+
+/*********************************************************************
+ * @fn      Standard_GetInterface.
+ *
+ * @brief   Return the Alternate Setting of the current interface.
+ *
+ * @param   Length - How many bytes are needed.
+ *
+ * @return  Return 1 - if the request is invalid when "Length" is 0.
+ *           Return "Buffer" if the "Length" is not 0.
+ */	
+uint8_t *Standard_GetInterface(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->Current_AlternateSetting);
+    return 0;
+  }
+  pUser_Standard_Requests->User_GetInterface();
+	
+  return (uint8_t *)&pInformation->Current_AlternateSetting;
+}
+
+/*********************************************************************
+ * @fn      Standard_SetInterface.
+ *
+ * @brief   This routine is called to set the interface.
+ *          hen each class should configure the interface them self.
+ *
+ * @return  Return USB_SUCCESS - if the request is performed.
+ *           Return USB_UNSUPPORT - if the request is invalid.
+ */
+RESULT Standard_SetInterface(void)
+{
+  RESULT Re;
+  Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+  if (pInformation->Current_Configuration != 0)
+  {
+    if ((Re != USB_SUCCESS) || (pInformation->USBwIndex1 != 0)
+        || (pInformation->USBwValue1 != 0))
+    {
+      return  USB_UNSUPPORT;
+    }
+    else if (Re == USB_SUCCESS)
+    {
+      pUser_Standard_Requests->User_SetInterface();
+      pInformation->Current_Interface = pInformation->USBwIndex0;
+      pInformation->Current_AlternateSetting = pInformation->USBwValue0;
+      return USB_SUCCESS;
+    }
+  }
+
+  return USB_UNSUPPORT;
+}
+
+/*********************************************************************
+ * @fn      Standard_GetStatus.
+ *
+ * @brief   Copy the device request data to "StatusInfo buffer".
+ *
+ * @param   Length - How many bytes are needed.
+ *
+ * @return  Return 0 - if the request is at end of data block,
+ *           or is invalid when "Length" is 0.
+ */	
+uint8_t *Standard_GetStatus(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 2;
+    return 0;
+  }
+  StatusInfo.w = 0;
+
+  if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+  {
+    uint8_t Feature = pInformation->Current_Feature;
+
+    if (ValBit(Feature, 5))
+    {
+      SetBit(StatusInfo0, 1);
+    }
+    else
+    {
+      ClrBit(StatusInfo0, 1);
+    }      
+    if (ValBit(Feature, 6))
+    {
+      SetBit(StatusInfo0, 0);
+    }
+    else 
+    {
+      ClrBit(StatusInfo0, 0);
+    }
+  }
+  else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+  {
+    return (uint8_t *)&StatusInfo;
+  }
+  else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+  {
+    uint8_t Related_Endpoint;
+    uint8_t wIndex0 = pInformation->USBwIndex0;
+
+    Related_Endpoint = (wIndex0 & 0x0f);
+    if (ValBit(wIndex0, 7))
+    {
+      if (_GetTxStallStatus(Related_Endpoint))
+      {
+        SetBit(StatusInfo0, 0); 
+      }
+    }
+    else
+    {
+      if (_GetRxStallStatus(Related_Endpoint))
+      {
+        SetBit(StatusInfo0, 0); 
+      }
+    }
+
+  }
+  else
+  {
+    return NULL;
+  }
+  pUser_Standard_Requests->User_GetStatus();
+	
+  return (uint8_t *)&StatusInfo;
+}
+
+/*********************************************************************
+ * @fn      Standard_ClearFeature.
+ *
+ * @brief   Clear or disable a specific feature.
+ *
+ * @return  Return USB_SUCCESS - if the request is performed.
+ *           Return USB_UNSUPPORT - if the request is invalid.
+ */
+RESULT Standard_ClearFeature(void)
+{
+  uint32_t     Type_Rec = Type_Recipient;
+  uint32_t     Status;
+	
+  if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+  {
+    ClrBit(pInformation->Current_Feature, 5);
+    return USB_SUCCESS;
+  }
+  else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+  {
+    DEVICE* pDev;
+    uint32_t Related_Endpoint;
+    uint32_t wIndex0;
+    uint32_t rEP;
+
+    if ((pInformation->USBwValue != ENDPOINT_STALL)
+        || (pInformation->USBwIndex1 != 0))
+    {
+      return USB_UNSUPPORT;
+    }
+
+    pDev = &Device_Table;
+    wIndex0 = pInformation->USBwIndex0;
+    rEP = wIndex0 & ~0x80;
+    Related_Endpoint = ENDP0 + rEP;
+
+    if (ValBit(pInformation->USBwIndex0, 7))
+    {
+      Status = _GetEPTxStatus(Related_Endpoint);
+    }
+    else
+    {
+      Status = _GetEPRxStatus(Related_Endpoint);
+    }
+
+    if ((rEP >= pDev->Total_Endpoint) || (Status == 0)
+        || (pInformation->Current_Configuration == 0))
+    {
+      return USB_UNSUPPORT;
+    }
+
+    if (wIndex0 & 0x80)
+    {
+      if (_GetTxStallStatus(Related_Endpoint ))
+      {
+        ClearDTOG_TX(Related_Endpoint);
+        SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+      }
+    }
+    else
+    {
+      if (_GetRxStallStatus(Related_Endpoint))
+      {
+        if (Related_Endpoint == ENDP0)
+        {
+          SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize);
+          _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+        }
+        else
+        {
+          ClearDTOG_RX(Related_Endpoint);
+          _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+        }
+      }
+    }
+    pUser_Standard_Requests->User_ClearFeature();
+    return USB_SUCCESS;
+  }
+
+  return USB_UNSUPPORT;
+}
+
+/*********************************************************************
+ * @fn      Standard_SetEndPointFeature
+ *
+ * @brief   Set or enable a specific feature of EndPoint
+ *
+ * @return  Return USB_SUCCESS - if the request is performed.
+ *           Return USB_UNSUPPORT - if the request is invalid.
+ */
+RESULT Standard_SetEndPointFeature(void)
+{
+  uint32_t    wIndex0;
+  uint32_t    Related_Endpoint;
+  uint32_t    rEP;
+  uint32_t    Status;
+
+  wIndex0 = pInformation->USBwIndex0;
+  rEP = wIndex0 & ~0x80;
+  Related_Endpoint = ENDP0 + rEP;
+
+  if (ValBit(pInformation->USBwIndex0, 7))
+  {
+    Status = _GetEPTxStatus(Related_Endpoint);
+  }
+  else
+  {
+    Status = _GetEPRxStatus(Related_Endpoint);
+  }
+
+  if (Related_Endpoint >= Device_Table.Total_Endpoint
+      || pInformation->USBwValue != 0 || Status == 0
+      || pInformation->Current_Configuration == 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else
+  {
+    if (wIndex0 & 0x80)
+    {
+      _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+    }
+    else
+    {
+      _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+    }
+  }
+  pUser_Standard_Requests->User_SetEndPointFeature();
+	
+  return USB_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      Standard_SetDeviceFeature.
+ *
+ * @brief   Set or enable a specific feature of Device.
+ *
+ * @return  Return USB_SUCCESS - if the request is performed.
+ *           Return USB_UNSUPPORT - if the request is invalid.
+ */
+RESULT Standard_SetDeviceFeature(void)
+{
+  SetBit(pInformation->Current_Feature, 5);
+  pUser_Standard_Requests->User_SetDeviceFeature();
+	
+  return USB_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      Standard_GetDescriptorData.
+ *
+ * @brief   Standard_GetDescriptorData is used for descriptors transfer.
+ *          This routine is used for the descriptors resident in Flash
+ *          or RAM
+ *          pDesc can be in either Flash or RAM
+ *          The purpose of this routine is to have a versatile way to
+ *          response descriptors request. It allows user to generate
+ *          certain descriptors with software or read descriptors from
+ *          external storage part by part.
+ * @param   Length - How many bytes are needed.
+ *          pDesc - A pointer points to descriptor struct.
+ *          The structure gives the initial address of the descriptor and
+ *           its original size.
+ *
+ * @return  Address of a part of the descriptor pointed by the Usb_
+ *          wOffset The buffer pointed by this address contains at least
+ *          Length bytes.
+ */	
+uint8_t *Standard_GetDescriptorData(uint16_t Length, ONE_DESCRIPTOR *pDesc)
+{
+  uint32_t  wOffset;
+
+  wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+	
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+    return 0;
+  }
+
+  return pDesc->Descriptor + wOffset;
+}
+
+/*********************************************************************
+ * @fn      DataStageOut.
+ *
+ * @brief   Data stage of a Control Write Transfer.
+ *
+ * @return  none
+ */
+void DataStageOut(void)
+{
+  ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
+  uint32_t save_rLength;
+
+  save_rLength = pEPinfo->Usb_rLength;
+
+  if (pEPinfo->CopyData && save_rLength)
+  {
+    uint8_t *Buffer;
+    uint32_t Length;
+
+    Length = pEPinfo->PacketSize;
+		
+    if (Length > save_rLength)
+    {
+      Length = save_rLength;
+    }
+
+    Buffer = (*pEPinfo->CopyData)(Length);
+    pEPinfo->Usb_rLength -= Length;
+    pEPinfo->Usb_rOffset += Length;
+    PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length);
+  }
+
+  if (pEPinfo->Usb_rLength != 0)
+  {
+    vSetEPRxStatus(EP_RX_VALID);
+    SetEPTxCount(ENDP0, 0);
+    vSetEPTxStatus(EP_TX_VALID);
+  }
+	
+  if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+  {
+    pInformation->ControlState = OUT_DATA;
+  }
+  else
+  {
+    if (pEPinfo->Usb_rLength > 0)
+    {
+      pInformation->ControlState = LAST_OUT_DATA;
+    }
+    else if (pEPinfo->Usb_rLength == 0)
+    {
+      pInformation->ControlState = WAIT_STATUS_IN;
+      USB_StatusIn();
+    }
+  }
+}
+
+/*********************************************************************
+ * @fn      DataStageIn.
+ *
+ * @brief   Data stage of a Control Read Transfer.
+ *
+ * @return  none
+ */
+void DataStageIn(void)
+{
+  ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
+  uint32_t save_wLength = pEPinfo->Usb_wLength;
+  uint32_t ControlState = pInformation->ControlState;
+
+  uint8_t *DataBuffer;
+  uint32_t Length;
+
+  if ((save_wLength == 0) && (ControlState == LAST_IN_DATA))
+  {
+    if(Data_Mul_MaxPacketSize == TRUE)
+    {
+      Send0LengthData();
+      ControlState = LAST_IN_DATA;
+      Data_Mul_MaxPacketSize = FALSE;
+    }
+    else 
+    {
+      ControlState = WAIT_STATUS_OUT;
+      vSetEPTxStatus(EP_TX_STALL);
+ 
+    }
+		
+    goto Expect_Status_Out;
+  }
+
+  Length = pEPinfo->PacketSize;
+  ControlState = (save_wLength <= Length) ? LAST_IN_DATA : IN_DATA;
+
+  if (Length > save_wLength)
+  {
+    Length = save_wLength;
+  }
+
+  DataBuffer = (*pEPinfo->CopyData)(Length);
+  
+  UserToPMABufferCopy(DataBuffer, GetEPTxAddr(ENDP0), Length);
+
+  SetEPTxCount(ENDP0, Length);
+
+  pEPinfo->Usb_wLength -= Length;
+  pEPinfo->Usb_wOffset += Length;
+  vSetEPTxStatus(EP_TX_VALID);
+
+  USB_StatusOut();
+
+Expect_Status_Out:
+  pInformation->ControlState = ControlState;
+}
+
+/*********************************************************************
+ * @fn      NoData_Setup0.
+ *
+ * @brief   Proceed the processing of setup request without data stage.
+ *
+ * @return  none
+ */
+void NoData_Setup0(void)
+{
+  RESULT Result = USB_UNSUPPORT;
+  uint32_t RequestNo = pInformation->USBbRequest;
+  uint32_t ControlState;
+
+  if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+  {
+    if (RequestNo == SET_CONFIGURATION)
+    {
+      Result = Standard_SetConfiguration();
+    }
+    else if (RequestNo == SET_ADDRESS)
+    {
+      if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0)
+          || (pInformation->USBwIndex != 0)
+          || (pInformation->Current_Configuration != 0))
+      {
+        ControlState = STALLED;
+        goto exit_NoData_Setup0;
+      }
+      else
+      {
+        Result = USB_SUCCESS;
+      }
+    }
+    else if (RequestNo == SET_FEATURE)
+    {
+      if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) \
+          && (pInformation->USBwIndex == 0))
+      {
+        Result = Standard_SetDeviceFeature();
+      }
+      else
+      {
+        Result = USB_UNSUPPORT;
+      }
+    }
+    else if (RequestNo == CLEAR_FEATURE)
+    {
+      if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP
+          && pInformation->USBwIndex == 0
+          && ValBit(pInformation->Current_Feature, 5))
+      {
+        Result = Standard_ClearFeature();
+      }
+      else
+      {
+        Result = USB_UNSUPPORT;
+      }
+    }
+
+  }
+  else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+  {
+    if (RequestNo == SET_INTERFACE)
+    {
+      Result = Standard_SetInterface();
+    }
+  }
+
+  else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+  {
+    if (RequestNo == CLEAR_FEATURE)
+    {
+      Result = Standard_ClearFeature();
+    }
+    else if (RequestNo == SET_FEATURE)
+    {
+      Result = Standard_SetEndPointFeature();
+    }
+  }
+  else
+  {
+    Result = USB_UNSUPPORT;
+  }
+
+  if (Result != USB_SUCCESS)
+  {
+    Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+    if (Result == USB_NOT_READY)
+    {
+      ControlState = PAUSE;
+      goto exit_NoData_Setup0;
+    }
+  }
+
+  if (Result != USB_SUCCESS)
+  {
+    ControlState = STALLED;
+    goto exit_NoData_Setup0;
+  }
+
+  ControlState = WAIT_STATUS_IN;
+
+  USB_StatusIn();
+
+exit_NoData_Setup0:
+  pInformation->ControlState = ControlState;
+  return;
+}
+
+/*********************************************************************
+ * @fn      Data_Setup0.
+ *
+ * @brief   Proceed the processing of setup request without data stage.
+ *
+ * @return  none
+ */
+void Data_Setup0(void)
+{
+  uint8_t *(*CopyRoutine)(uint16_t);
+  RESULT Result;
+  uint32_t Request_No = pInformation->USBbRequest;
+  uint32_t Related_Endpoint, Reserved;
+  uint32_t wOffset, Status;
+
+  CopyRoutine = NULL;
+  wOffset = 0;
+	
+  if (Request_No == GET_DESCRIPTOR)
+  {
+    if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+    {
+      uint8_t wValue1 = pInformation->USBwValue1;
+      if (wValue1 == DEVICE_DESCRIPTOR)
+      {
+        CopyRoutine = pProperty->GetDeviceDescriptor;
+      }
+      else if (wValue1 == CONFIG_DESCRIPTOR)
+      {
+        CopyRoutine = pProperty->GetConfigDescriptor;
+      }
+      else if (wValue1 == STRING_DESCRIPTOR)
+      {
+        CopyRoutine = pProperty->GetStringDescriptor;
+      } 
+    }
+  }
+  else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0)
+           && (pInformation->USBwLength == 0x0002)
+           && (pInformation->USBwIndex1 == 0))
+  {
+  
+    if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+        && (pInformation->USBwIndex == 0))
+    {
+      CopyRoutine = Standard_GetStatus;
+    }
+    else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+    {
+      if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS)
+          && (pInformation->Current_Configuration != 0))
+      {
+        CopyRoutine = Standard_GetStatus;
+      }
+    }
+    else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+    {
+      Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+      Reserved = pInformation->USBwIndex0 & 0x70;
+
+      if (ValBit(pInformation->USBwIndex0, 7))
+      {
+        Status = _GetEPTxStatus(Related_Endpoint);
+      }
+      else
+      {
+        Status = _GetEPRxStatus(Related_Endpoint);
+      }
+
+      if ((Related_Endpoint < Device_Table.Total_Endpoint) && (Reserved == 0)
+          && (Status != 0))
+      {
+        CopyRoutine = Standard_GetStatus;
+      }
+    }
+
+  }
+  else if (Request_No == GET_CONFIGURATION)
+  {
+    if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+    {
+      CopyRoutine = Standard_GetConfiguration;
+    }
+  }
+  else if (Request_No == GET_INTERFACE)
+  {
+    if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+        && (pInformation->Current_Configuration != 0) && (pInformation->USBwValue == 0)
+        && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+        && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS))
+    {
+      CopyRoutine = Standard_GetInterface;
+    }
+
+  }
+  
+  if (CopyRoutine)
+  {
+    pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+    pInformation->Ctrl_Info.CopyData = CopyRoutine;
+    (*CopyRoutine)(0);
+    Result = USB_SUCCESS;
+  }
+  else
+  {
+    Result = (*pProperty->Class_Data_Setup)(pInformation->USBbRequest);
+		
+    if (Result == USB_NOT_READY)
+    {
+      pInformation->ControlState = PAUSE;
+      return;
+    }
+  }
+
+  if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+  {
+    pInformation->ControlState = PAUSE;
+    return;
+  }
+	
+  if ((Result == USB_UNSUPPORT) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+  {
+    pInformation->ControlState = STALLED;
+    return;
+  }
+
+  if (ValBit(pInformation->USBbmRequestType, 7))
+  {
+    __IO uint32_t wLength = pInformation->USBwLength;
+    if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+    {
+      pInformation->Ctrl_Info.Usb_wLength = wLength;
+    } 
+    else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+    {
+      if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+      {
+        Data_Mul_MaxPacketSize = FALSE;
+      }
+      else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+      {
+        Data_Mul_MaxPacketSize = TRUE;
+      }
+    }   
+
+    pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+    DataStageIn();
+  }
+  else
+  {
+    pInformation->ControlState = OUT_DATA;
+    vSetEPRxStatus(EP_RX_VALID); 
+  }
+
+  return;
+}
+
+/*********************************************************************
+ * @fn      Setup0_Process
+ *
+ * @brief   Get the device request data and dispatch to individual process.
+ *
+ * @return  Post0_Process.
+ */
+uint8_t Setup0_Process(void)
+{
+  union
+  {
+    uint8_t* b;
+    uint16_t* w;
+  } pBuf;
+  uint16_t offset = 1;
+  
+  pBuf.b = PMAAddr + (uint8_t *)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+  if (pInformation->ControlState != PAUSE)
+  {
+    pInformation->USBbmRequestType = *pBuf.b++; /* bmRequestType */
+    pInformation->USBbRequest = *pBuf.b++; /* bRequest */
+    pBuf.w += offset;  /* word not accessed because of 32 bits addressing */
+    pInformation->USBwValue = ByteSwap(*pBuf.w++); /* wValue */
+    pBuf.w += offset;  /* word not accessed because of 32 bits addressing */
+    pInformation->USBwIndex  = ByteSwap(*pBuf.w++); /* wIndex */
+    pBuf.w += offset;  /* word not accessed because of 32 bits addressing */
+    pInformation->USBwLength = *pBuf.w; /* wLength */
+  }
+  pInformation->ControlState = SETTING_UP;
+	
+  if (pInformation->USBwLength == 0)
+  {
+    NoData_Setup0();
+  }
+  else
+  {
+    Data_Setup0();
+  }
+  return Post0_Process();
+}
+
+/*********************************************************************
+ * @fn      In0_Process
+ *
+ * @brief   Process the IN token on all default endpoint.
+ *
+ * @return  Post0_Process.
+ */
+uint8_t In0_Process(void)
+{
+  uint32_t ControlState = pInformation->ControlState;
+
+  if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
+  {
+    DataStageIn();
+    ControlState = pInformation->ControlState;
+  }
+  else if (ControlState == WAIT_STATUS_IN)
+  {
+    if ((pInformation->USBbRequest == SET_ADDRESS) &&
+        (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+    {
+      SetDeviceAddress(pInformation->USBwValue0);
+      pUser_Standard_Requests->User_SetDeviceAddress();
+    }
+    (*pProperty->Process_Status_IN)();
+    ControlState = STALLED;
+  }
+  else
+  {
+    ControlState = STALLED;
+  }
+
+  pInformation->ControlState = ControlState;
+
+  return Post0_Process();
+}
+
+/*********************************************************************
+ * @fn      Out0_Process
+ *
+ * @brief   Process the OUT token on all default endpoint.
+ *
+ * @return  Post0_Process.
+ */
+uint8_t Out0_Process(void)
+{
+  uint32_t ControlState = pInformation->ControlState;
+
+  if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
+  {
+    ControlState = STALLED;
+  }
+  else if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA))
+  {
+    DataStageOut();
+    ControlState = pInformation->ControlState; 
+  }
+  else if (ControlState == WAIT_STATUS_OUT)
+  {
+    (*pProperty->Process_Status_OUT)();
+    ControlState = STALLED;
+  }
+  else
+  {
+    ControlState = STALLED;
+  }
+
+  pInformation->ControlState = ControlState;
+
+  return Post0_Process();
+}
+
+/*********************************************************************
+ * @fn      Post0_Process
+ *
+ * @brief   Stall the Endpoint 0 in case of error.
+ *
+ * @return  0 - if the control State is in PAUSE
+ *          1 - if not.
+ */
+uint8_t Post0_Process(void)
+{  
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+
+  if (pInformation->ControlState == STALLED)
+  {
+    vSetEPRxStatus(EP_RX_STALL);
+    vSetEPTxStatus(EP_TX_STALL);
+  }
+
+  return (pInformation->ControlState == PAUSE);
+}
+
+/*********************************************************************
+ * @fn      SetDeviceAddress..
+ *
+ * @brief   Set the device and all the used Endpoints addresses.
+ *
+ * @param   Val: device address.
+ *
+ * @return  none
+ */	
+void SetDeviceAddress(uint8_t Val)
+{
+  uint32_t i;
+  uint32_t nEP = Device_Table.Total_Endpoint;
+	
+  for (i = 0; i < nEP; i++)
+  {
+    _SetEPAddress((uint8_t)i, (uint8_t)i);
+  } 
+	
+  _SetDADDR(Val | DADDR_EF); 
+}
+
+/*********************************************************************
+ * @fn      NOP_Process
+ *
+ * @brief   No operation function.
+ *
+ * @return  none
+ */
+void NOP_Process(void)
+{
+}
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/src/usb_init.c

@@ -0,0 +1,39 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_init.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Initialization routines & global variables
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+
+uint8_t	EPindex;
+DEVICE_INFO *pInformation;
+DEVICE_PROP *pProperty;
+uint16_t	SaveState ;
+uint16_t  wInterrupt_Mask;
+DEVICE_INFO	Device_Info;
+USER_STANDARD_REQUESTS  *pUser_Standard_Requests;
+
+/*********************************************************************
+ * @fn      USB_Init
+ *
+ * @brief   USB system initialization
+ *
+ * @return  none
+ */
+void USB_Init(void)
+{
+  pInformation = &Device_Info;
+  pInformation->ControlState = 2;
+  pProperty = &Device_Property;
+  pUser_Standard_Requests = &User_Standard_Requests;
+  pProperty->Init();
+}
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/src/usb_int.c

@@ -0,0 +1,129 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_int.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Endpoint CTR (Low and High) interrupt's service routines
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+
+/* Private variables */
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+/* Extern variables */
+extern void (*pEpInt_IN[7])(void);    /*  Handles IN  interrupts   */
+extern void (*pEpInt_OUT[7])(void);   /*  Handles OUT interrupts   */
+
+/*********************************************************************
+ * @fn      CTR_LP.
+ *
+ * @brief   Low priority Endpoint Correct Transfer interrupt's service routine.
+ *
+ * @return  none
+ */
+void CTR_LP(void)
+{
+  __IO uint16_t wEPVal = 0;
+	
+  while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
+  {
+    EPindex = (uint8_t)(wIstr & ISTR_EP_ID);
+		
+    if (EPindex == 0)
+    {
+	    SaveRState = _GetENDPOINT(ENDP0);
+	    SaveTState = SaveRState & EPTX_STAT;
+	    SaveRState &=  EPRX_STAT;	
+
+	    _SetEPRxTxStatus(ENDP0,EP_RX_NAK,EP_TX_NAK);
+			
+      if ((wIstr & ISTR_DIR) == 0)
+      {
+        _ClearEP_CTR_TX(ENDP0);
+        In0_Process();
+
+        _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+				
+				return;
+      }
+      else
+      {
+        wEPVal = _GetENDPOINT(ENDP0);
+        
+        if ((wEPVal &EP_SETUP) != 0)
+        {
+          _ClearEP_CTR_RX(ENDP0);
+          Setup0_Process();
+		      _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+					
+          return;
+        }
+        else if ((wEPVal & EP_CTR_RX) != 0)
+        {
+          _ClearEP_CTR_RX(ENDP0);
+          Out0_Process();
+		     _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+					
+          return;
+        }
+      }
+    }
+    else
+    {
+      wEPVal = _GetENDPOINT(EPindex);
+      if ((wEPVal & EP_CTR_RX) != 0)
+      {
+        _ClearEP_CTR_RX(EPindex);
+        (*pEpInt_OUT[EPindex-1])();
+      } 
+
+      if ((wEPVal & EP_CTR_TX) != 0)
+      {
+        _ClearEP_CTR_TX(EPindex);     
+        (*pEpInt_IN[EPindex-1])();
+      }
+    }
+  }
+}
+
+/*********************************************************************
+ * @fn      CTR_HP.
+ *
+ * @brief   High Priority Endpoint Correct Transfer interrupt's service routine.
+ *
+ * @return  none
+ */
+void CTR_HP(void)
+{
+  uint32_t wEPVal = 0;
+
+  while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
+  {
+    _SetISTR((uint16_t)CLR_CTR); 
+    EPindex = (uint8_t)(wIstr & ISTR_EP_ID);   
+    wEPVal = _GetENDPOINT(EPindex);
+		
+    if ((wEPVal & EP_CTR_RX) != 0)
+    {
+      _ClearEP_CTR_RX(EPindex); 
+      (*pEpInt_OUT[EPindex-1])();
+    } 
+    else if ((wEPVal & EP_CTR_TX) != 0)
+    {
+      _ClearEP_CTR_TX(EPindex);   
+      (*pEpInt_IN[EPindex-1])();
+    } 
+  }
+}
+
+
+
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/src/usb_mem.c

@@ -0,0 +1,70 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_mem.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Utility functions for memory transfers to/from PMA
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+
+
+/*********************************************************************
+ * @fn      UserToPMABufferCopy
+ *
+ * @brief   Copy a buffer from user memory area to packet memory area (PMA)
+ *
+ * @param   pbUsrBuf - pointer to user memory area.
+ *          wPMABufAddr - address into PMA.
+ *          wNBytes - no. of bytes to be copied.
+ *
+ * @return  none
+ */	
+void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = (wNBytes + 1) >> 1;   
+  uint32_t i, temp1, temp2;
+  uint16_t *pdwVal;
+  pdwVal = (uint16_t *)(wPMABufAddr * 2 + PMAAddr);
+	
+  for (i = n; i != 0; i--){
+    temp1 = (uint16_t) * pbUsrBuf;
+    pbUsrBuf++;
+    temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+    *pdwVal++ = temp2;
+    pdwVal++;
+    pbUsrBuf++;
+  }
+}
+
+/*********************************************************************
+ * @fn      PMAToUserBufferCopy
+ *
+ * @brief   Copy a buffer from user memory area to packet memory area (PMA)
+ *
+ * @param   pbUsrBuf - pointer to user memory area.
+ *          wPMABufAddr - address into PMA.
+ *          wNBytes - no. of bytes to be copied.
+ *
+ * @return  none
+ */
+void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = (wNBytes + 1) >> 1;
+  uint32_t i;
+  uint32_t *pdwVal;
+	
+  pdwVal = (uint32_t *)(wPMABufAddr * 2 + PMAAddr);
+	
+  for (i = n; i != 0; i--){
+    *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+    pbUsrBuf++;
+  } 
+}
+
+
+
+
+
+

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/src/usb_regs.c

@@ -0,0 +1,875 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_regs.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Interface functions to USB cell registers
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+
+/*********************************************************************
+ * @fn      SetCNTR.
+ *
+ * @brief   Set the CNTR register value.
+ *
+ * @param   wRegValue - new register value.
+ *
+ * @return  none
+ */	
+void SetCNTR(uint16_t wRegValue)
+{
+  _SetCNTR(wRegValue);
+}
+
+/*********************************************************************
+ * @fn      GetCNTR.
+ *
+ * @brief   returns the CNTR register value.
+ *
+ * @return  CNTR register Value.
+ */
+uint16_t GetCNTR(void)
+{
+  return(_GetCNTR());
+}
+
+/*********************************************************************
+ * @fn      SetISTR.
+ *
+ * @brief   Set the CNTR register value.
+ *
+ * @param   wRegValue - new register value.
+ *
+ * @return  none
+ */	
+void SetISTR(uint16_t wRegValue)
+{
+  _SetISTR(wRegValue);
+}
+
+/*********************************************************************
+ * @fn      GetISTR
+ *
+ * @brief   Returns the ISTR register value.
+ *
+ * @return  ISTR register Value
+ */
+uint16_t GetISTR(void)
+{
+  return(_GetISTR());
+}
+
+/*********************************************************************
+ * @fn      GetFNR
+ *
+ * @brief   Returns the FNR register value.
+ *
+ * @return  FNR register Value
+ */
+uint16_t GetFNR(void)
+{
+  return(_GetFNR());
+}
+
+/*********************************************************************
+ * @fn      SetDADDR
+ *
+ * @brief   Set the DADDR register value.
+ *
+ * @param   wRegValue - new register value.
+ *
+ * @return  none
+ */	
+void SetDADDR(uint16_t wRegValue)
+{
+  _SetDADDR(wRegValue);
+}
+
+/*********************************************************************
+ * @fn      GetDADDR
+ *
+ * @brief   Returns the DADDR register value.
+ *
+ * @return  DADDR register Value
+ */
+uint16_t GetDADDR(void)
+{
+  return(_GetDADDR());
+}
+
+/*********************************************************************
+ * @fn      SetBTABLE
+ *
+ * @brief   Set the CNTR register value.
+ *
+ * @param   wRegValue - new register value.
+ *
+ * @return  none
+ */	
+void SetBTABLE(uint16_t wRegValue)
+{
+  _SetBTABLE(wRegValue);
+}
+
+/*********************************************************************
+ * @fn      GetBTABLE.
+ *
+ * @brief   Returns the BTABLE register value.
+ *
+ * @return  BTABLE address.
+ */	
+uint16_t GetBTABLE(void)
+{
+  return(_GetBTABLE());
+}
+
+/*********************************************************************
+ * @fn      SetENDPOINT
+ *
+ * @brief   Set the Endpoint register value.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          wRegValue.
+ *
+ * @return  none
+ */	
+void SetENDPOINT(uint8_t bEpNum, uint16_t wRegValue)
+{
+  _SetENDPOINT(bEpNum, wRegValue);
+}
+
+/*********************************************************************
+ * @fn      GetENDPOINT
+ *
+ * @brief   Return the Endpoint register value.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Endpoint register value.
+ */	
+uint16_t GetENDPOINT(uint8_t bEpNum)
+{
+  return(_GetENDPOINT(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      SetEPType
+ *
+ * @brief   Set the Endpoint register value.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          wType - type definition.
+ *
+ * @return  none
+ */	
+void SetEPType(uint8_t bEpNum, uint16_t wType)
+{
+  _SetEPType(bEpNum, wType);
+}
+
+/*********************************************************************
+ * @fn      GetEPType
+ *
+ * @brief   Returns the endpoint type.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Endpoint Type
+ */	
+uint16_t GetEPType(uint8_t bEpNum)
+{
+  return(_GetEPType(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      SetEPTxStatus
+ *
+ * @brief   Set the status of Tx endpoint.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          wState - new state.
+ *
+ * @return  none
+ */	
+void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
+{
+  _SetEPTxStatus(bEpNum, wState);
+}
+
+/*********************************************************************
+ * @fn      SetEPRxStatus
+ *
+ * @brief   Set the status of Tx endpoint.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          wState - new state.
+ *
+ * @return  none
+ */
+void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
+{
+  _SetEPRxStatus(bEpNum, wState);
+}
+
+/*********************************************************************
+ * @fn      SetDouBleBuffEPStall
+ *
+ * @brief   sets the status for Double Buffer Endpoint to STALL
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          bDir - Endpoint direction.
+ *
+ * @return  none
+ */
+void SetDouBleBuffEPStall(uint8_t bEpNum, uint8_t bDir)
+{
+  uint16_t Endpoint_DTOG_Status;
+	
+  Endpoint_DTOG_Status = GetENDPOINT(bEpNum);
+	
+  if (bDir == EP_DBUF_OUT)
+  { 
+    _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DTOG1);
+  }
+  else if (bDir == EP_DBUF_IN)
+  { 
+    _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DTOG1);
+  }
+}
+
+/*********************************************************************
+ * @fn      GetEPTxStatus
+ *
+ * @brief   Returns the endpoint Tx status.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Endpoint TX Status
+ */
+uint16_t GetEPTxStatus(uint8_t bEpNum)
+{
+  return(_GetEPTxStatus(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      GetEPRxStatus
+ *
+ * @brief   Returns the endpoint Tx status.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Endpoint RX Status
+ */
+uint16_t GetEPRxStatus(uint8_t bEpNum)
+{
+  return(_GetEPRxStatus(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      SetEPTxValid
+ *
+ * @brief   Valid the endpoint Tx Status.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void SetEPTxValid(uint8_t bEpNum)
+{
+  _SetEPTxStatus(bEpNum, EP_TX_VALID);
+}
+
+/*********************************************************************
+ * @fn      SetEPRxValid
+ *
+ * @brief   Valid the endpoint Rx Status.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void SetEPRxValid(uint8_t bEpNum)
+{
+  _SetEPRxStatus(bEpNum, EP_RX_VALID);
+}
+
+/*********************************************************************
+ * @fn      SetEP_KIND
+ *
+ * @brief   Clear the EP_KIND bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void SetEP_KIND(uint8_t bEpNum)
+{
+  _SetEP_KIND(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      ClearEP_KIND
+ *
+ * @brief   set the  EP_KIND bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ClearEP_KIND(uint8_t bEpNum)
+{
+  _ClearEP_KIND(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      Clear_Status_Out
+ *
+ * @brief   Clear the Status Out of the related Endpoint
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void Clear_Status_Out(uint8_t bEpNum)
+{
+  _ClearEP_KIND(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      Set_Status_Out
+ *
+ * @brief   Set the Status Out of the related Endpoint
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void Set_Status_Out(uint8_t bEpNum)
+{
+  _SetEP_KIND(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      SetEPDoubleBuff
+ *
+ * @brief   Enable the double buffer feature for the endpoint. 
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void SetEPDoubleBuff(uint8_t bEpNum)
+{
+  _SetEP_KIND(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      ClearEPDoubleBuff
+ *
+ * @brief   Disable the double buffer feature for the endpoint. 
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ClearEPDoubleBuff(uint8_t bEpNum)
+{
+  _ClearEP_KIND(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      GetTxStallStatus
+ *
+ * @brief   Returns the Stall status of the Tx endpoint.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+uint16_t GetTxStallStatus(uint8_t bEpNum)
+{
+  return(_GetTxStallStatus(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      GetRxStallStatus
+ *
+ * @brief   Returns the Stall status of the Rx endpoint.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Rx Stall status.
+ */
+uint16_t GetRxStallStatus(uint8_t bEpNum)
+{
+  return(_GetRxStallStatus(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      ClearEP_CTR_RX
+ *
+ * @brief   Clear the CTR_RX bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ClearEP_CTR_RX(uint8_t bEpNum)
+{
+  _ClearEP_CTR_RX(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      ClearEP_CTR_TX
+ *
+ * @brief   Clear the CTR_TX bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ClearEP_CTR_TX(uint8_t bEpNum)
+{
+  _ClearEP_CTR_TX(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      ToggleDTOG_RX
+ *
+ * @brief   Toggle the DTOG_RX bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ToggleDTOG_RX(uint8_t bEpNum)
+{
+  _ToggleDTOG_RX(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      ToggleDTOG_TX
+ *
+ * @brief   Toggle the DTOG_TX bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ToggleDTOG_TX(uint8_t bEpNum)
+{
+  _ToggleDTOG_TX(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      ClearDTOG_RX.
+ *
+ * @brief   Clear the DTOG_RX bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ClearDTOG_RX(uint8_t bEpNum)
+{
+  _ClearDTOG_RX(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      ClearDTOG_TX.
+ *
+ * @brief   Clear the DTOG_TX bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  none
+ */
+void ClearDTOG_TX(uint8_t bEpNum)
+{
+  _ClearDTOG_TX(bEpNum);
+}
+
+/*********************************************************************
+ * @fn      SetEPAddress
+ *
+ * @brief   Set the endpoint address.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          bAddr - New endpoint address.
+ *
+ * @return  none
+ */
+void SetEPAddress(uint8_t bEpNum, uint8_t bAddr)
+{
+  _SetEPAddress(bEpNum, bAddr);
+}
+
+/*********************************************************************
+ * @fn      GetEPAddress
+ *
+ * @brief   Clear the DTOG_TX bit.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Endpoint address.
+ */
+uint8_t GetEPAddress(uint8_t bEpNum)
+{
+  return(_GetEPAddress(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      SetEPTxAddr
+ *
+ * @brief   Set the endpoint Tx buffer address.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          bAddr - New endpoint address.
+ *
+ * @return  none
+ */
+void SetEPTxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+  _SetEPTxAddr(bEpNum, wAddr);
+}
+
+/*********************************************************************
+ * @fn      SetEPRxAddr
+ *
+ * @brief   Set the endpoint Rx buffer address.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          bAddr - New endpoint address.
+ *
+ * @return  none
+ */
+void SetEPRxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+  _SetEPRxAddr(bEpNum, wAddr);
+}
+
+/*********************************************************************
+ * @fn      GetEPTxAddr
+ *
+ * @brief   Returns the endpoint Tx buffer address.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Rx buffer address. 
+ */
+uint16_t GetEPTxAddr(uint8_t bEpNum)
+{
+  return(_GetEPTxAddr(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      GetEPRxAddr.
+ *
+ * @brief   Returns the endpoint Rx buffer address.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Rx buffer address. 
+ */
+uint16_t GetEPRxAddr(uint8_t bEpNum)
+{
+  return(_GetEPRxAddr(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      SetEPTxCount.
+ *
+ * @brief   Set the Tx count.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          wCount - new count value.
+ *
+ * @return  none
+ */
+void SetEPTxCount(uint8_t bEpNum, uint16_t wCount)
+{
+  _SetEPTxCount(bEpNum, wCount);
+}
+
+/*********************************************************************
+ * @fn      SetEPCountRxReg.
+ *
+ * @brief   Set the Count Rx Register value.
+ *
+ * @param   *pdwReg - Endpoint Number. 
+ *          wCount - new count value.
+ *
+ * @return  none
+ */
+void SetEPCountRxReg(uint32_t *pdwReg, uint16_t wCount)
+{
+  _SetEPCountRxReg(dwReg, wCount);
+}
+
+/*********************************************************************
+ * @fn      SetEPTxCount.
+ *
+ * @brief   Set the Tx count.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *          wCount - new count value.
+ *
+ * @return  none
+ */
+void SetEPRxCount(uint8_t bEpNum, uint16_t wCount)
+{
+  _SetEPRxCount(bEpNum, wCount);
+}
+
+/*********************************************************************
+ * @fn      GetEPTxCount
+ *
+ * @brief   Get the Tx count.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Tx count value.
+ */
+uint16_t GetEPTxCount(uint8_t bEpNum)
+{
+  return(_GetEPTxCount(bEpNum));
+}
+/*********************************************************************
+ * @fn      GetEPRxCount
+ *
+ * @brief   Get the Rx count.
+ *
+ * @param   bEpNum - Endpoint Number. 
+ *
+ * @return  Rx count value.
+ */
+uint16_t GetEPRxCount(uint8_t bEpNum)
+{
+  return(_GetEPRxCount(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      SetEPDblBuffAddr
+ *
+ * @brief   Set the addresses of the buffer 0 and 1.
+ *
+ * @param   bEpNum - Endpoint Number.
+ *          wBuf0Addr - new address of buffer 0. 
+ *          wBuf1Addr - new address of buffer 1.
+ *
+ * @return  none
+ */
+void SetEPDblBuffAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
+{
+  _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
+}
+
+/*********************************************************************
+ * @fn      SetEPDblBuf0Addr
+ *
+ * @brief   Set the Buffer 1 address.
+ *
+ * @param   bEpNum - Endpoint Number.
+ *          wBuf0Addr - new address.
+ *
+ * @return  none
+ */
+void SetEPDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
+{
+  _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
+}
+
+/*********************************************************************
+ * @fn      SetEPDblBuf1Addr
+ *
+ * @brief   Set the Buffer 1 address.
+ *
+ * @param   bEpNum - Endpoint Number.
+ *          wBuf1Addr - new address.
+ *
+ * @return  none
+ */
+void SetEPDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
+{
+  _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
+}
+
+/*********************************************************************
+ * @fn      GetEPDblBuf0Addr
+ *
+ * @brief   Returns the address of the Buffer 0.
+ *
+ * @param   bEpNum - Endpoint Number.
+ *
+ * @return  none
+ */
+uint16_t GetEPDblBuf0Addr(uint8_t bEpNum)
+{
+  return(_GetEPDblBuf0Addr(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      GetEPDblBuf1Addr
+ *
+ * @brief   Returns the address of the Buffer 1.
+ *
+ * @param   bEpNum - Endpoint Number.
+ *
+ * @return  Address of the Buffer 1.
+ */
+uint16_t GetEPDblBuf1Addr(uint8_t bEpNum)
+{
+  return(_GetEPDblBuf1Addr(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      SetEPDblBuffCount
+ *
+ * @brief   Set the number of bytes for a double Buffer endpoint. 
+ *
+ * @param   bEpNum,bDir, wCount
+ *
+ * @return  none
+ */
+void SetEPDblBuffCount(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+  _SetEPDblBuffCount(bEpNum, bDir, wCount);
+}
+
+/*********************************************************************
+ * @fn      SetEPDblBuf0Count
+ *
+ * @brief   Set the number of bytes for a double Buffer endpoint. 
+ *
+ * @param   bEpNum,bDir, wCount
+ *
+ * @return  none
+ */
+void SetEPDblBuf0Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+  _SetEPDblBuf0Count(bEpNum, bDir, wCount);
+}
+
+/*********************************************************************
+ * @fn      SetEPDblBuf1Count
+ *
+ * @brief   Set the number of bytes for a double Buffer endpoint. 
+ *
+ * @param   bEpNum,bDir, wCount
+ *
+ * @return  none
+ */
+void SetEPDblBuf1Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+  _SetEPDblBuf1Count(bEpNum, bDir, wCount);
+}
+
+/*********************************************************************
+ * @fn      GetEPDblBuf0Count
+ *
+ * @brief   Returns the number of byte received in the buffer 0 of a double 
+ *           Buffer endpoint.
+ *
+ * @param   bEpNum - Endpoint Number.
+ *
+ * @return  Endpoint Buffer 0 count
+ */
+uint16_t GetEPDblBuf0Count(uint8_t bEpNum)
+{
+  return(_GetEPDblBuf0Count(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      GetEPDblBuf1Count
+ *
+ * @brief   Returns the number of byte received in the buffer 1 of a double 
+ *           Buffer endpoint.
+ *
+ * @param   bEpNum - Endpoint Number.
+ *
+ * @return  Endpoint Buffer 1 count
+ */
+uint16_t GetEPDblBuf1Count(uint8_t bEpNum)
+{
+  return(_GetEPDblBuf1Count(bEpNum));
+}
+
+/*********************************************************************
+ * @fn      GetEPDblBufDir
+ *
+ * @brief   gets direction of the double buffered endpoint
+ *
+ * @param   bEpNum - Endpoint Number.
+ *
+ * @return  EP_DBUF_OUT, EP_DBUF_IN,
+ *          EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
+{
+  if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
+    return(EP_DBUF_OUT);
+  else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
+    return(EP_DBUF_IN);
+  else
+    return(EP_DBUF_ERR);
+}
+
+/*********************************************************************
+ * @fn      FreeUserBuffer
+ *
+ * @brief   free buffer used from the application realizing it to the line
+ *          toggles bit SW_BUF in the double buffered endpoint register
+ *
+ * @param   bEpNum, bDir
+ *
+ * @return  none
+ */
+void FreeUserBuffer(uint8_t bEpNum, uint8_t bDir)
+{
+  if (bDir == EP_DBUF_OUT)
+  {
+    _ToggleDTOG_TX(bEpNum);
+  }
+  else if (bDir == EP_DBUF_IN)
+  { 
+    _ToggleDTOG_RX(bEpNum);
+  }
+}
+
+/*********************************************************************
+ * @fn      ToWord
+ *
+ * @brief   merge two byte in a word.
+ *
+ * @param   bh - byte high, bl - bytes low.
+ *
+ * @return  resulted word
+ */
+uint16_t ToWord(uint8_t bh, uint8_t bl)
+{
+  uint16_t wRet;
+  wRet = (uint16_t)bl | ((uint16_t)bh << 8);
+	
+  return(wRet);
+}
+
+/*********************************************************************
+ * @fn      ByteSwap
+ *
+ * @brief   Swap two byte in a word.
+ *
+ * @param   wSwW - word to Swap
+ *
+ * @return  resulted word
+ */
+uint16_t ByteSwap(uint16_t wSwW)
+{
+  uint8_t bTemp;
+  uint16_t wRet;
+  bTemp = (uint8_t)(wSwW & 0xff);
+  wRet =  (wSwW >> 8) | ((uint16_t)bTemp << 8);
+	
+  return(wRet);
+}

Example/EpaperModuleTest_CH32F103/CH32F103/USBLIB/USB-Driver/src/usb_sil.c

@@ -0,0 +1,74 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_sil.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2019/10/15
+ * Description        : Simplified Interface Layer for Global Initialization and 
+ *			           Endpoint  Rea/Write operations.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#include "usb_lib.h"
+
+
+/*********************************************************************
+ * @fn      USB_SIL_Init
+ *
+ * @brief   Initialize the USB Device IP and the Endpoint 0.
+ *
+ * @return  Status.
+ */
+uint32_t USB_SIL_Init(void)
+{
+  _SetISTR(0);
+  wInterrupt_Mask = IMR_MSK;
+  _SetCNTR(wInterrupt_Mask);
+	
+  return 0;
+}
+
+/*********************************************************************
+ * @fn      USB_SIL_Write
+ *
+ * @brief   Write a buffer of data to a selected endpoint.
+ *
+ * @param   bEpAddr - The address of the non control endpoint.
+ *          pBufferPointer - The pointer to the buffer of data to be written
+ *          to the endpoint.
+ *
+ * @return  Status.
+ */
+uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
+{
+  UserToPMABufferCopy(pBufferPointer, GetEPTxAddr(bEpAddr & 0x7F), wBufferSize);
+  SetEPTxCount((bEpAddr & 0x7F), wBufferSize);
+  
+  return 0;
+}
+
+/*********************************************************************
+ * @fn      USB_SIL_Read
+ *
+ * @brief   Write a buffer of data to a selected endpoint.
+ *
+ * @param   bEpAddr - The address of the non control endpoint.
+ *          pBufferPointer - The pointer to the buffer of data to be written
+ *          to the endpoint.
+ *
+ * @return  Number of received data (in Bytes).
+ */
+uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer)
+{
+  uint32_t DataLength = 0;
+
+  DataLength = GetEPRxCount(bEpAddr & 0x7F); 
+  PMAToUserBufferCopy(pBufferPointer, GetEPRxAddr(bEpAddr & 0x7F), DataLength);
+
+  return DataLength;
+}
+
+
+
+
+
+