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Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Include/apm32f10x.h
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Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Include/system_apm32f10x.h
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/*!
* @file system_apm32f10x.h
*
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __SYSTEM_APM32F10X_H
#define __SYSTEM_APM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock;
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_APM32F10X_H */
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s
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;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
; *
; * @version V1.0.2
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD TMR8_BRK_IRQHandler ; TMR8 Break
DCD TMR8_UP_IRQHandler ; TMR8 Update
DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_IRQHandler ; TMR6
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD 0 ; Reserved
DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX
DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_IRQHandler [WEAK]
EXPORT TMR1_UP_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBDWakeUp_IRQHandler [WEAK]
EXPORT TMR8_BRK_IRQHandler [WEAK]
EXPORT TMR8_UP_IRQHandler [WEAK]
EXPORT TMR8_TRG_COM_IRQHandler [WEAK]
EXPORT TMR8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT EMMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TMR6_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT USBD2_HP_CAN2_TX_IRQHandler [WEAK]
EXPORT USBD2_LP_CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USBD1_HP_CAN1_TX_IRQHandler
USBD1_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_IRQHandler
TMR1_UP_IRQHandler
TMR1_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTCAlarm_IRQHandler
USBDWakeUp_IRQHandler
TMR8_BRK_IRQHandler
TMR8_UP_IRQHandler
TMR8_TRG_COM_IRQHandler
TMR8_CC_IRQHandler
ADC3_IRQHandler
EMMC_IRQHandler
SDIO_IRQHandler
TMR5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TMR6_IRQHandler
TMR7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
USBD2_HP_CAN2_TX_IRQHandler
USBD2_LP_CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;*******************************END OF FILE************************************
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s
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;/*!
; * @file startup_apm32f10x_md.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md
; *
; * @version V1.0.2
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD FPU_IRQHandler ; FPU
DCD QSPI_IRQHandler ; QSPI
DCD USBD2_HP_IRQHandler ; USBD2 High Priority
DCD USBD2_LP_IRQHandler ; USBD2 Low Priority
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_IRQHandler [WEAK]
EXPORT TMR1_UP_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBDWakeUp_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT USBD2_HP_IRQHandler [WEAK]
EXPORT USBD2_LP_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USBD1_HP_CAN1_TX_IRQHandler
USBD1_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_IRQHandler
TMR1_UP_IRQHandler
TMR1_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTCAlarm_IRQHandler
USBDWakeUp_IRQHandler
FPU_IRQHandler
QSPI_IRQHandler
USBD2_HP_IRQHandler
USBD2_LP_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;*******************************END OF FILE************************************
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s
+281
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;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
// external interrupts handler
.word WWDT_IRQHandler // Window Watchdog
.word PVD_IRQHandler // PVD through EINT Line detect
.word TAMPER_IRQHandler // Tamper
.word RTC_IRQHandler // RTC
.word FLASH_IRQHandler // Flash
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line 0
.word EINT1_IRQHandler // EINT Line 1
.word EINT2_IRQHandler // EINT Line 2
.word EINT3_IRQHandler // EINT Line 3
.word EINT4_IRQHandler // EINT Line 4
.word DMA1_Channel1_IRQHandler // DMA1 Channel 1
.word DMA1_Channel2_IRQHandler // DMA1 Channel 2
.word DMA1_Channel3_IRQHandler // DMA1 Channel 3
.word DMA1_Channel4_IRQHandler // DMA1 Channel 4
.word DMA1_Channel5_IRQHandler // DMA1 Channel 5
.word DMA1_Channel6_IRQHandler // DMA1 Channel 6
.word DMA1_Channel7_IRQHandler // DMA1 Channel 7
.word ADC1_2_IRQHandler // ADC1 & ADC2
.word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX
.word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // EINT Line 9..5
.word TMR1_BRK_IRQHandler // TMR1 Break
.word TMR1_UP_IRQHandler // TMR1 Update
.word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // EINT Line 15..10
.word RTCAlarm_IRQHandler // RTC Alarm through EINT Line
.word USBDWakeUp_IRQHandler // USBD Wakeup from suspend
.word TMR8_BRK_IRQHandler // TMR8 Break
.word TMR8_UP_IRQHandler // TMR8 Update
.word TMR8_TRG_COM_IRQHandler // TMR8 Trigger and Commutation
.word TMR8_CC_IRQHandler // TMR8 Capture Compare
.word ADC3_IRQHandler // ADC3
.word EMMC_IRQHandler // EMMC
.word SDIO_IRQHandler // SDIO
.word TMR5_IRQHandler // TMR5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TMR6_IRQHandler // TMR6
.word TMR7_IRQHandler // TMR7
.word DMA2_Channel1_IRQHandler // DMA2 Channel1
.word DMA2_Channel2_IRQHandler // DMA2 Channel2
.word DMA2_Channel3_IRQHandler // DMA2 Channel3
.word DMA2_Channel4_5_IRQHandler // DMA2 Channel4 & Channel5
.word 0 // Reserved
.word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX
.word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.size g_pfnVectors, .-g_pfnVectors
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
b .
.size NMI_Handler, . - NMI_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
b .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
b .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
b .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
b .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
b .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
b .
.size SysTick_Handler, . - SysTick_Handler
/* IQR Handler */
.section .text.Default_Handler,"ax",%progbits
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WWDT_IRQHandler
IRQ PVD_IRQHandler
IRQ TAMPER_IRQHandler
IRQ RTC_IRQHandler
IRQ FLASH_IRQHandler
IRQ RCM_IRQHandler
IRQ EINT0_IRQHandler
IRQ EINT1_IRQHandler
IRQ EINT2_IRQHandler
IRQ EINT3_IRQHandler
IRQ EINT4_IRQHandler
IRQ DMA1_Channel1_IRQHandler
IRQ DMA1_Channel2_IRQHandler
IRQ DMA1_Channel3_IRQHandler
IRQ DMA1_Channel4_IRQHandler
IRQ DMA1_Channel5_IRQHandler
IRQ DMA1_Channel6_IRQHandler
IRQ DMA1_Channel7_IRQHandler
IRQ ADC1_2_IRQHandler
IRQ USBD1_HP_CAN1_TX_IRQHandler
IRQ USBD1_LP_CAN1_RX0_IRQHandler
IRQ CAN1_RX1_IRQHandler
IRQ CAN1_SCE_IRQHandler
IRQ EINT9_5_IRQHandler
IRQ TMR1_BRK_IRQHandler
IRQ TMR1_UP_IRQHandler
IRQ TMR1_TRG_COM_IRQHandler
IRQ TMR1_CC_IRQHandler
IRQ TMR2_IRQHandler
IRQ TMR3_IRQHandler
IRQ TMR4_IRQHandler
IRQ I2C1_EV_IRQHandler
IRQ I2C1_ER_IRQHandler
IRQ I2C2_EV_IRQHandler
IRQ I2C2_ER_IRQHandler
IRQ SPI1_IRQHandler
IRQ SPI2_IRQHandler
IRQ USART1_IRQHandler
IRQ USART2_IRQHandler
IRQ USART3_IRQHandler
IRQ EINT15_10_IRQHandler
IRQ RTCAlarm_IRQHandler
IRQ USBDWakeUp_IRQHandler
IRQ TMR8_BRK_IRQHandler
IRQ TMR8_UP_IRQHandler
IRQ TMR8_TRG_COM_IRQHandler
IRQ TMR8_CC_IRQHandler
IRQ ADC3_IRQHandler
IRQ EMMC_IRQHandler
IRQ SDIO_IRQHandler
IRQ TMR5_IRQHandler
IRQ SPI3_IRQHandler
IRQ UART4_IRQHandler
IRQ UART5_IRQHandler
IRQ TMR6_IRQHandler
IRQ TMR7_IRQHandler
IRQ DMA2_Channel1_IRQHandler
IRQ DMA2_Channel2_IRQHandler
IRQ DMA2_Channel3_IRQHandler
IRQ DMA2_Channel4_5_IRQHandler
IRQ USBD2_HP_CAN2_TX_IRQHandler
IRQ USBD2_LP_CAN2_RX0_IRQHandler
IRQ CAN2_RX1_IRQHandler
IRQ CAN2_SCE_IRQHandler
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s
+246
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@@ -0,0 +1,246 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
// external interrupts handler
.word WWDT_IRQHandler // Window Watchdog
.word PVD_IRQHandler // PVD through EINT Line detect
.word TAMPER_IRQHandler // Tamper
.word RTC_IRQHandler // RTC
.word FLASH_IRQHandler // Flash
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line 0
.word EINT1_IRQHandler // EINT Line 1
.word EINT2_IRQHandler // EINT Line 2
.word EINT3_IRQHandler // EINT Line 3
.word EINT4_IRQHandler // EINT Line 4
.word DMA1_Channel1_IRQHandler // DMA1 Channel 1
.word DMA1_Channel2_IRQHandler // DMA1 Channel 2
.word DMA1_Channel3_IRQHandler // DMA1 Channel 3
.word DMA1_Channel4_IRQHandler // DMA1 Channel 4
.word DMA1_Channel5_IRQHandler // DMA1 Channel 5
.word DMA1_Channel6_IRQHandler // DMA1 Channel 6
.word DMA1_Channel7_IRQHandler // DMA1 Channel 7
.word ADC1_2_IRQHandler // ADC1_2
.word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX
.word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // EINT Line 9..5
.word TMR1_BRK_IRQHandler // TMR1 Break
.word TMR1_UP_IRQHandler // TMR1 Update
.word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // EINT Line 15..10
.word RTCAlarm_IRQHandler // RTC Alarm through EINT Line
.word USBDWakeUp_IRQHandler // USBD Wakeup from suspend
.word FPU_IRQHandler // FPU
.word QSPI_IRQHandler // QSPI
.word USBD2_HP_IRQHandler // USBD2 High Priority
.word USBD2_LP_IRQHandler // USBD2 Low Priority
.size g_pfnVectors, .-g_pfnVectors
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
b .
.size NMI_Handler, . - NMI_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
b .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
b .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
b .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
b .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
b .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
b .
.size SysTick_Handler, . - SysTick_Handler
/* IQR Handler */
.section .text.Default_Handler,"ax",%progbits
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WWDT_IRQHandler
IRQ PVD_IRQHandler
IRQ TAMPER_IRQHandler
IRQ RTC_IRQHandler
IRQ FLASH_IRQHandler
IRQ RCM_IRQHandler
IRQ EINT0_IRQHandler
IRQ EINT1_IRQHandler
IRQ EINT2_IRQHandler
IRQ EINT3_IRQHandler
IRQ EINT4_IRQHandler
IRQ DMA1_Channel1_IRQHandler
IRQ DMA1_Channel2_IRQHandler
IRQ DMA1_Channel3_IRQHandler
IRQ DMA1_Channel4_IRQHandler
IRQ DMA1_Channel5_IRQHandler
IRQ DMA1_Channel6_IRQHandler
IRQ DMA1_Channel7_IRQHandler
IRQ ADC1_2_IRQHandler
IRQ USBD1_HP_CAN1_TX_IRQHandler
IRQ USBD1_LP_CAN1_RX0_IRQHandler
IRQ CAN1_RX1_IRQHandler
IRQ CAN1_SCE_IRQHandler
IRQ EINT9_5_IRQHandler
IRQ TMR1_BRK_IRQHandler
IRQ TMR1_UP_IRQHandler
IRQ TMR1_TRG_COM_IRQHandler
IRQ TMR1_CC_IRQHandler
IRQ TMR2_IRQHandler
IRQ TMR3_IRQHandler
IRQ TMR4_IRQHandler
IRQ I2C1_EV_IRQHandler
IRQ I2C1_ER_IRQHandler
IRQ I2C2_EV_IRQHandler
IRQ I2C2_ER_IRQHandler
IRQ SPI1_IRQHandler
IRQ SPI2_IRQHandler
IRQ USART1_IRQHandler
IRQ USART2_IRQHandler
IRQ USART3_IRQHandler
IRQ EINT15_10_IRQHandler
IRQ RTCAlarm_IRQHandler
IRQ USBDWakeUp_IRQHandler
IRQ FPU_IRQHandler
IRQ QSPI_IRQHandler
IRQ USBD2_HP_IRQHandler
IRQ USBD2_LP_IRQHandler
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s
+504
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@@ -0,0 +1,504 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD TMR8_BRK_IRQHandler ; TMR8 Break
DCD TMR8_UP_IRQHandler ; TMR8 Update
DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_IRQHandler ; TMR6
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD 0 ; Reserved
DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX
DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_HP_CAN1_TX_IRQHandler
B USBD1_HP_CAN1_TX_IRQHandler
PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_LP_CAN1_RX0_IRQHandler
B USBD1_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_IRQHandler
B TMR1_BRK_IRQHandler
PUBWEAK TMR1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_IRQHandler
B TMR1_UP_IRQHandler
PUBWEAK TMR1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_IRQHandler
B TMR1_TRG_COM_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBDWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBDWakeUp_IRQHandler
B USBDWakeUp_IRQHandler
PUBWEAK TMR8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_BRK_IRQHandler
B TMR8_BRK_IRQHandler
PUBWEAK TMR8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_UP_IRQHandler
B TMR8_UP_IRQHandler
PUBWEAK TMR8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_TRG_COM_IRQHandler
B TMR8_TRG_COM_IRQHandler
PUBWEAK TMR8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_CC_IRQHandler
B TMR8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK EMMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EMMC_IRQHandler
B EMMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TMR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR5_IRQHandler
B TMR5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TMR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR6_IRQHandler
B TMR6_IRQHandler
PUBWEAK TMR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR7_IRQHandler
B TMR7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
PUBWEAK USBD2_HP_CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_HP_CAN2_TX_IRQHandler
B USBD2_HP_CAN2_TX_IRQHandler
PUBWEAK USBD2_LP_CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_LP_CAN2_RX0_IRQHandler
B USBD2_LP_CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
END
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s
+404
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@@ -0,0 +1,404 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD FPU_IRQHandler ; FPU
DCD QSPI_IRQHandler ; QSPI
DCD USBD2_HP_IRQHandler ; USBD2 High Priority
DCD USBD2_LP_IRQHandler ; USBD2 Low Priority
__Vectors_End
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_HP_CAN1_TX_IRQHandler
B USBD1_HP_CAN1_TX_IRQHandler
PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_LP_CAN1_RX0_IRQHandler
B USBD1_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_IRQHandler
B TMR1_BRK_IRQHandler
PUBWEAK TMR1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_IRQHandler
B TMR1_UP_IRQHandler
PUBWEAK TMR1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_IRQHandler
B TMR1_TRG_COM_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBDWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBDWakeUp_IRQHandler
B USBDWakeUp_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK QSPI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
QSPI_IRQHandler
B QSPI_IRQHandler
PUBWEAK USBD2_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_HP_IRQHandler
B USBD2_HP_IRQHandler
PUBWEAK USBD2_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_LP_IRQHandler
B USBD2_LP_IRQHandler
END
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/system_apm32f10x.c
+566
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@@ -0,0 +1,566 @@
/*!
* @file system_apm32f10x.c
*
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x.h"
/*****************************************************************
* If SYSCLK source is PLL,SystemCoreClock will contain the *
* HSE_VALUE or HSI_VALUE multiplied/divided by the PLL factors. *
******************************************************************/
//#define SYSTEM_CLOCK_HSE HSE_VALUE
//#define SYSTEM_CLOCK_24MHz (24000000)
//#define SYSTEM_CLOCK_36MHz (36000000)
//#define SYSTEM_CLOCK_48MHz (48000000)
//#define SYSTEM_CLOCK_56MHz (56000000)
//#define SYSTEM_CLOCK_72MHz (72000000)
#define SYSTEM_CLOCK_96MHz (96000000)
/** #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00
#ifdef SYSTEM_CLOCK_HSE
uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE;
#elif defined SYSTEM_CLOCK_24MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz;
#elif defined SYSTEM_CLOCK_36MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz;
#elif defined SYSTEM_CLOCK_48MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz;
#elif defined SYSTEM_CLOCK_56MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz;
#elif defined SYSTEM_CLOCK_72MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz;
#else
uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz;
#endif
static void SystemClockConfig(void);
#ifdef SYSTEM_CLOCK_HSE
static void SystemClockHSE(void);
#elif defined SYSTEM_CLOCK_24MHz
static void SystemClock24M(void);
#elif defined SYSTEM_CLOCK_36MHz
static void SystemClock36M(void);
#elif defined SYSTEM_CLOCK_48MHz
static void SystemClock48M(void);
#elif defined SYSTEM_CLOCK_56MHz
static void SystemClock56M(void);
#elif defined SYSTEM_CLOCK_72MHz
static void SystemClock72M(void);
#elif defined SYSTEM_CLOCK_96MHz
static void SystemClock96M(void);
#endif
/*!
* @brief Setup the microcontroller system
*
* @param None
*
* @retval None
*
*/
void SystemInit (void)
{
/** Set HSIEN bit */
RCM->CTRL_B.HSIEN = BIT_SET;
/** Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
RCM->CFG &= (uint32_t)0xF8FF0000;
/** Reset HSEEN, CSSEN and PLLEN bits */
RCM->CTRL &= (uint32_t)0xFEF6FFFF;
/** Reset HSEBCFG bit */
RCM->CTRL_B.HSEBCFG = BIT_RESET;
/** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
RCM->CFG &= (uint32_t)0xFF80FFFF;
/** Disable all interrupts and clear pending bits */
RCM->INT = 0x009F0000;
SystemClockConfig();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else
SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET;
#endif
}
/*!
* @brief Update SystemCoreClock variable according to Clock Register Values
* The SystemCoreClock variable contains the core clock (HCLK)
*
* @param None
*
* @retval None
*
*/
void SystemCoreClockUpdate (void)
{
uint32_t sysClock, pllMull, pllSource, Prescaler;
uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
sysClock = RCM->CFG_B.SCLKSELSTS;
switch(sysClock)
{
/** sys clock is HSI */
case 0:
SystemCoreClock = HSI_VALUE;
break;
/** sys clock is HSE */
case 1:
SystemCoreClock = HSE_VALUE;
break;
/** sys clock is PLL */
case 2:
pllMull = RCM->CFG_B.PLLMULCFG + 2;
pllSource = RCM->CFG_B.PLLSRCSEL;
/** PLL entry clock source is HSE */
if(pllSource == BIT_SET)
{
SystemCoreClock = HSE_VALUE * pllMull;
/** HSE clock divided by 2 */
if(pllSource == RCM->CFG_B.PLLHSEPSC)
{
SystemCoreClock >>= 1;
}
}
/** PLL entry clock source is HSI/2 */
else
{
SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
}
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
Prescaler = AHBPrescTable[RCM->CFG_B.AHBPSC];
SystemCoreClock >>= Prescaler;
}
/*!
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClockConfig(void)
{
#ifdef SYSTEM_CLOCK_HSE
SystemClockHSE();
#elif defined SYSTEM_CLOCK_24MHz
SystemClock24M();
#elif defined SYSTEM_CLOCK_36MHz
SystemClock36M();
#elif defined SYSTEM_CLOCK_48MHz
SystemClock48M();
#elif defined SYSTEM_CLOCK_56MHz
SystemClock56M();
#elif defined SYSTEM_CLOCK_72MHz
SystemClock72M();
#elif defined SYSTEM_CLOCK_96MHz
SystemClock96M();
#endif
}
#if defined SYSTEM_CLOCK_HSE
/*!
* @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClockHSE(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 0 wait state */
FMC->CTRL1_B.WS = 0;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK */
RCM->CFG_B.APB1PSC = 0;
/** Select HSE as system clock source */
RCM->CFG_B.SCLKSEL = 1;
/** Wait till HSE is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x01);
}
}
#elif defined SYSTEM_CLOCK_24MHz
/*!
* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock24M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 0 wait state */
FMC->CTRL1_B.WS = 0;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK */
RCM->CFG_B.APB1PSC = 0;
/** PLL: (HSE / 2) * 6 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLHSEPSC = 1;
RCM->CFG_B.PLLMULCFG = 4;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_36MHz
/*!
* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock36M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 1 wait state */
FMC->CTRL1_B.WS = 1;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK */
RCM->CFG_B.APB1PSC = 0;
/** PLL: (HSE / 2) * 9 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLHSEPSC = 1;
RCM->CFG_B.PLLMULCFG = 7;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS != 0x02);
}
}
#elif defined SYSTEM_CLOCK_48MHz
/*!
* @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock48M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 1 wait state */
FMC->CTRL1_B.WS = 1;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 6 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 4;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_56MHz
/*!
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock56M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 2 wait state */
FMC->CTRL1_B.WS = 2;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 7 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 5;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_72MHz
/*!
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock72M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 2 wait state */
FMC->CTRL1_B.WS = 2;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 9 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 7;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_96MHz
/*!
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock96M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 3 wait state */
FMC->CTRL1_B.WS = 3;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 12 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 10;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#endif