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Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h
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/*!
* @file apm32f10x_adc.h
*
* @brief This file contains all the functions prototypes for the ADC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_ADC_H
#define __APM32F10X_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup ADC_Driver ADC Driver
@{
*/
/** @addtogroup ADC_Enumerations Enumerations
@{
*/
/**
* @brief ADC configuration Mode
*/
typedef enum
{
ADC_MODE_INDEPENDENT = ((uint32_t)0x00000000), //!< Independent mode
ADC_MODE_REG_INJEC_SIMULT = ((uint32_t)0x00010000), //!< Combined regular simultaneous and injected simultaneous mode
ADC_MODE_REG_SIMULT_ALTER_TRIG = ((uint32_t)0x00020000), //!< Combined regular simultaneous and alternate trigger mode
ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), //!< Combined injected simultaneous and fast interleaved mode
ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), //!< Combined injected simultaneous and slow interleaved mode
ADC_MODE_INJEC_SIMULT = ((uint32_t)0x00050000), //!< Injected simultaneous mode
ADC_MODE_REG_SIMULT = ((uint32_t)0x00060000), //!< Regular simultaneous mode
ADC_MODE_FAST_INTERL = ((uint32_t)0x00070000), //!< Fast interleaved mode
ADC_MODE_SLOW_INTERL = ((uint32_t)0x00080000), //!< Slow interleaved mode
ADC_MODE_ALTER_TRIG = ((uint32_t)0x00090000) //!< Alternate trigger mode
} ADC_MODE_T;
/**
* @brief ADC external trigger sources for regular channels conversion enumeration
*/
typedef enum
{
ADC_EXT_TRIG_CONV_TMR1_CC1 = ((uint32_t)0x00000000),
ADC_EXT_TRIG_CONV_TMR1_CC2 = ((uint32_t)0x00020000),
ADC_EXT_TRIG_CONV_TMR2_CC2 = ((uint32_t)0x00060000),
ADC_EXT_TRIG_CONV_TMR3_TRGO = ((uint32_t)0x00080000),
ADC_EXT_TRIG_CONV_TMR4_CC4 = ((uint32_t)0x000A0000),
ADC_EXT_TRIG_CONV_EINT9_T8_TRGO = ((uint32_t)0x000C0000),
ADC_EXT_TRIG_CONV_TMR1_CC3 = ((uint32_t)0x00040000),
ADC_EXT_TRIG_CONV_None = ((uint32_t)0x000E0000),
ADC_EXT_TRIG_CONV_TMR3_CC1 = ((uint32_t)0x00000000),
ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00020000),
ADC_EXT_TRIG_CONV_TMR8_CC1 = ((uint32_t)0x00060000),
ADC_EXT_TRIG_CONV_TMR8_TRGO = ((uint32_t)0x00080000),
ADC_EXT_TRIG_CONV_TMR5_CC1 = ((uint32_t)0x000A0000),
ADC_EXT_TRIG_CONV_TMR5_CC3 = ((uint32_t)0x000C0000)
} ADC_EXT_TRIG_CONV_T;
/**
* @brief ADC Data Align
*/
typedef enum
{
ADC_DATA_ALIGN_RIGHT = 0x00000000,
ADC_DATA_ALIGN_LEFT = 0x00000800
} ADC_DATA_ALIGN_T;
/**
* @brief ADC Channels
*/
typedef enum
{
ADC_CHANNEL_0 = ((uint8_t)0x00),
ADC_CHANNEL_1 = ((uint8_t)0x01),
ADC_CHANNEL_2 = ((uint8_t)0x02),
ADC_CHANNEL_3 = ((uint8_t)0x03),
ADC_CHANNEL_4 = ((uint8_t)0x04),
ADC_CHANNEL_5 = ((uint8_t)0x05),
ADC_CHANNEL_6 = ((uint8_t)0x06),
ADC_CHANNEL_7 = ((uint8_t)0x07),
ADC_CHANNEL_8 = ((uint8_t)0x08),
ADC_CHANNEL_9 = ((uint8_t)0x09),
ADC_CHANNEL_10 = ((uint8_t)0x0A),
ADC_CHANNEL_11 = ((uint8_t)0x0B),
ADC_CHANNEL_12 = ((uint8_t)0x0C),
ADC_CHANNEL_13 = ((uint8_t)0x0D),
ADC_CHANNEL_14 = ((uint8_t)0x0E),
ADC_CHANNEL_15 = ((uint8_t)0x0F),
ADC_CHANNEL_16 = ((uint8_t)0x10),
ADC_CHANNEL_TEMP_SENSOR = ((uint8_t)0x10),
ADC_CHANNEL_17 = ((uint8_t)0x11),
ADC_CHANNEL_V_REFINT = ((uint8_t)0x11)
} ADC_CHANNEL_T;
/**
* @brief ADC Sampling Time
*/
typedef enum
{
ADC_SAMPLETIME_1CYCLES5 = ((uint8_t)0x00),
ADC_SAMPLETIME_7CYCLES5 = ((uint8_t)0x01),
ADC_SAMPLETIME_13CYCLES5 = ((uint8_t)0x02),
ADC_SAMPLETIME_28CYCLES5 = ((uint8_t)0x03),
ADC_SAMPLETIME_41CYCLES5 = ((uint8_t)0x04),
ADC_SAMPLETIME_55CYCLES5 = ((uint8_t)0x05),
ADC_SAMPLETIME_71CYCLES5 = ((uint8_t)0x06),
ADC_SAMPLETIME_239CYCLES5 = ((uint8_t)0x07)
} ADC_SAMPLETIME_T;
/**
* @brief ADC external trigger sources for injected channels conversion
*/
typedef enum
{
/** for ADC1 and ADC2 */
ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO = ((uint8_t)0x02),
ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1 = ((uint8_t)0x03),
ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4 = ((uint8_t)0x04),
ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO = ((uint8_t)0x05),
ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4 = ((uint8_t)0x06),
/** for ADC1, ADC2 and ADC3 */
ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO = ((uint8_t)0x00),
ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4 = ((uint8_t)0x01),
ADC_EXT_TRIG_INJEC_CONV_NONE = ((uint8_t)0x07),
/** for ADC3 only */
ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3 = ((uint8_t)0x02),
ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2 = ((uint8_t)0x03),
ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4 = ((uint8_t)0x04),
ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO = ((uint8_t)0x05),
ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4 = ((uint8_t)0x06)
} ADC_EXT_TRIG_INJEC_CONV_T;
/**
* @brief ADC Injected channels
*/
typedef enum
{
ADC_INJEC_CHANNEL_1 = ((uint8_t)0x14),
ADC_INJEC_CHANNEL_2 = ((uint8_t)0x18),
ADC_INJEC_CHANNEL_3 = ((uint8_t)0x1C),
ADC_INJEC_CHANNEL_4 = ((uint8_t)0x20)
} ADC_INJEC_CHANNEL_T;
/**
* @brief ADC Analog Watchdog Selection
*/
typedef enum
{
ADC_ANALOG_WATCHDOG_SINGLE_REG = ((uint32_t)0x00800200),
ADC_ANALOG_WATCHDOG_SINGLE_INJEC = ((uint32_t)0x00400200),
ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC = ((uint32_t)0x00C00200),
ADC_ANALOG_WATCHDOG_ALL_REG = ((uint32_t)0x00800000),
ADC_ANALOG_WATCHDOG_ALL_INJEC = ((uint32_t)0x00400000),
ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC = ((uint32_t)0x00C00000),
ADC_ANALOG_WATCHDOG_NONE = ((uint32_t)0x00000000)
} ADC_ANALOG_WATCHDOG_T;
/**
* @brief ADC Interrupt definition
*/
typedef enum
{
ADC_INT_AWD = ((uint16_t)0x0140), //!< Analog Watchdog interrupt
ADC_INT_EOC = ((uint16_t)0x0220), //!< End Of Conversion interrupt
ADC_INT_INJEOC = ((uint16_t)0x0480) //!< Injected Channel End Of Conversion interrupt
} ADC_INT_T;
/**
* @brief ADC Flag
*/
typedef enum
{
ADC_FLAG_AWD = ((uint8_t)0x01), //!< Analog Watchdog event occur flag
ADC_FLAG_EOC = ((uint8_t)0x02), //!< End Of Conversion flag
ADC_FLAG_INJEOC = ((uint8_t)0x04), //!< Injected Channel End Of Conversion flag
ADC_FLAG_INJCS = ((uint8_t)0x08), //!< Injected Channel Conversion Start flag
ADC_FLAG_REGCS = ((uint8_t)0x10) //!< Regular Channel Conversion Start flag
} ADC_FLAG_T;
/**@} end of group ADC_Enumerations*/
/** @addtogroup ADC_Macros Macros
@{
*/
/** ADC_IJD Offset */
#define INJDATA_OFFSET ((uint8_t)0x28)
/** ADC_RDG register address */
#define RDG_ADDRESS ((uint32_t)0x4001244C)
/** INJSEQ register config */
#define INJSEQ_SET_INJSEQC ((uint32_t)0x0000001F)
#define INJSEQ_SET_INJSEQLEN ((uint32_t)0x00300000)
/** SMPTIM register SET */
#define SMPCYCCFG_SET_SMPTIM1 ((uint32_t)0x00000007)
#define SMPCYCCFG_SET_SMPTIM2 ((uint32_t)0x00000007)
/** REGSEQ register SET */
#define REGSEQC_SET_REGSEQ3 ((uint32_t)0x0000001F)
#define REGSEQC_SET_REGSEQ2 ((uint32_t)0x0000001F)
#define REGSEQC_SET_REGSEQ1 ((uint32_t)0x0000001F)
/**@} end of group ADC_Macros*/
/** @addtogroup ADC_Structure Data Structure
@{
*/
/**
* @brief ADC Config structure definition
*/
typedef struct
{
ADC_MODE_T mode;
uint8_t scanConvMode; //!< This parameter can be ENABLE or DISABLE.
uint8_t continuosConvMode; //!< This parameter can be ENABLE or DISABLE.
ADC_EXT_TRIG_CONV_T externalTrigConv;
ADC_DATA_ALIGN_T dataAlign;
uint8_t nbrOfChannel; //!< This parameter must range from 1 to 16.
} ADC_Config_T;
/**@} end of group ADC_Structure*/
/** @addtogroup ADC_Fuctions Fuctions
@{
*/
/** ADC reset and common configuration */
void ADC_Reset(ADC_T* adc);
void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig);
void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime);
void ADC_Enable(ADC_T* adc);
void ADC_Disable(ADC_T* adc);
/** ADC for DMA */
void ADC_EnableDMA(ADC_T* adc);
void ADC_DisableDMA(ADC_T* adc);
/** ADC Calibration */
void ADC_ResetCalibration(ADC_T* adc);
uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc);
void ADC_StartCalibration(ADC_T* adc);
uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc);
/** ADC software start conversion */
void ADC_EnableSoftwareStartConv(ADC_T* adc);
void ADC_DisableSoftwareStartConv(ADC_T* adc);
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc);
/** ADC Discontinuous mode */
void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number);
void ADC_EnableDiscMode(ADC_T* adc);
void ADC_DisableDiscMode(ADC_T* adc);
/** ADC External trigger conversion */
void ADC_EnableExternalTrigConv(ADC_T* adc);
void ADC_DisableExternalTrigConv(ADC_T* adc);
/** ADC Conversion result */
uint16_t ADC_ReadConversionValue(ADC_T* adc);
uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc);
/** ADC Automatic injected group */
void ADC_EnableAutoInjectedConv(ADC_T* adc);
void ADC_DisableAutoInjectedConv(ADC_T* adc);
void ADC_EnableInjectedDiscMode(ADC_T* adc);
void ADC_DisableInjectedDiscMode(ADC_T* adc);
/** ADC External trigger for injected channels conversion */
void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
void ADC_EnableExternalTrigInjectedConv(ADC_T* adc);
void ADC_DisableExternalTrigInjectedConv(ADC_T* adc);
/** ADC Start of the injected channels conversion */
void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc);
void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc);
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc);
/** ADC injected channel */
void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length);
void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel);
/** ADC analog watchdog */
void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog);
void ADC_DisableAnalogWatchdog(ADC_T* adc);
void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold);
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel);
/** ADC temperature sensor */
void ADC_EnableTempSensorVrefint(ADC_T* adc);
void ADC_DisableTempSensorVrefint(ADC_T* adc);
/** Interrupt and flag */
void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt);
void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt);
uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag);
void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag);
uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag);
void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag);
/**@} end of group ADC_Fuctions*/
/**@} end of group ADC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /** __APM32F10X_ADC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h
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/*!
* @file apm32f10x_bakr.h
*
* @brief This file contains all the functions prototypes for the BAKPR firmware library.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_BAKPR_H
#define __APM32F10X_BAKPR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup BAKPR_Driver BAKPR Driver
@{
*/
/** @addtogroup BAKPR_Enumerations Enumerations
@{
*/
/**
* @brief BAKPR TAMPER Pin Active Level
*/
typedef enum
{
BAKPR_TAMPER_PIN_LEVEL_HIGH,
BAKPR_TAMPER_PIN_LEVEL_LOW
} BAKPR_TAMPER_PIN_LEVEL_T;
/**
* @brief BAKPR RTC output source
*/
typedef enum
{
BAKPR_RTC_OUTPUT_SOURCE_NONE,
BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK,
BAKPR_RTC_OUTPUT_SOURCE_ALARM,
BAKPR_RTC_OUTPUT_SOURCE_SECOND
} BAKPR_RTC_OUTPUT_SOURCE_T;
/**
* @brief BAKPR DATA register Addr
*/
typedef enum
{
BAKPR_DATA1 = ((uint16_t)0x0004),
BAKPR_DATA2 = ((uint16_t)0x0008),
BAKPR_DATA3 = ((uint16_t)0x000C),
BAKPR_DATA4 = ((uint16_t)0x0010),
BAKPR_DATA5 = ((uint16_t)0x0014),
BAKPR_DATA6 = ((uint16_t)0x0018),
BAKPR_DATA7 = ((uint16_t)0x001C),
BAKPR_DATA8 = ((uint16_t)0x0020),
BAKPR_DATA9 = ((uint16_t)0x0024),
BAKPR_DATA10 = ((uint16_t)0x0028),
BAKPR_DATA11 = ((uint16_t)0x0040),
BAKPR_DATA12 = ((uint16_t)0x0044),
BAKPR_DATA13 = ((uint16_t)0x0048),
BAKPR_DATA14 = ((uint16_t)0x004C),
BAKPR_DATA15 = ((uint16_t)0x0050),
BAKPR_DATA16 = ((uint16_t)0x0054),
BAKPR_DATA17 = ((uint16_t)0x0058),
BAKPR_DATA18 = ((uint16_t)0x005C),
BAKPR_DATA19 = ((uint16_t)0x0060),
BAKPR_DATA20 = ((uint16_t)0x0064),
BAKPR_DATA21 = ((uint16_t)0x0068),
BAKPR_DATA22 = ((uint16_t)0x006C),
BAKPR_DATA23 = ((uint16_t)0x0070),
BAKPR_DATA24 = ((uint16_t)0x0074),
BAKPR_DATA25 = ((uint16_t)0x0078),
BAKPR_DATA26 = ((uint16_t)0x007C),
BAKPR_DATA27 = ((uint16_t)0x0080),
BAKPR_DATA28 = ((uint16_t)0x0084),
BAKPR_DATA29 = ((uint16_t)0x0088),
BAKPR_DATA30 = ((uint16_t)0x008C),
BAKPR_DATA31 = ((uint16_t)0x0090),
BAKPR_DATA32 = ((uint16_t)0x0094),
BAKPR_DATA33 = ((uint16_t)0x0098),
BAKPR_DATA34 = ((uint16_t)0x009C),
BAKPR_DATA35 = ((uint16_t)0x00A0),
BAKPR_DATA36 = ((uint16_t)0x00A4),
BAKPR_DATA37 = ((uint16_t)0x00A8),
BAKPR_DATA38 = ((uint16_t)0x00AC),
BAKPR_DATA39 = ((uint16_t)0x00B0),
BAKPR_DATA40 = ((uint16_t)0x00B4),
BAKPR_DATA41 = ((uint16_t)0x00B8),
BAKPR_DATA42 = ((uint16_t)0x00BC)
} BAKPR_DATA_T;
/**@} end of group BAKPR_Enumerations*/
/** @addtogroup BAKPR_Fuctions Fuctions
@{
*/
/** BAKPR reset and configuration */
void BAKPR_Reset(void);
void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value);
void BAKPR_EnableTamperPin(void);
void BAKPR_DisableTamperPin(void);
void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure);
void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue);
void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data);
uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData);
/** Interrupts and flags */
void BAKPR_EnableInterrupt(void);
void BAKPR_DisableInterrupt(void);
uint8_t BAKPR_ReadStatusFlag(void);
void BAKPR_ClearStatusFlag(void);
uint8_t BAKPR_ReadIntFlag(void);
void BAKPR_ClearIntFlag(void);
/**@} end of group BAKPR_Fuctions*/
/**@} end of group BAKPR_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_BAKPR_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h
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/*!
* @file apm32f10x_can.h
*
* @brief This file contains all the functions prototypes for the CAN firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_CAN_H
#define __APM32F10X_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup CAN_Driver CAN Driver
@{
*/
/** @addtogroup CAN_Enumerations Enumerations
@{
*/
/**
* @brief CAN mode
*/
typedef enum
{
CAN_MODE_NORMAL = ((uint8_t)0x00), //!< normal mode
CAN_MODE_LOOPBACK = ((uint8_t)0x01), //!< loopback mode
CAN_MODE_SILENT = ((uint8_t)0x02), //!< silent mode
CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03) //!< loopback combined with silent mode
} CAN_MODE_T;
/**
* @brief CAN synchronisation jump width
*/
typedef enum
{
CAN_SJW_1 = ((uint8_t)0x00), //!< 1 time quantum
CAN_SJW_2 = ((uint8_t)0x01), //!< 2 time quantum
CAN_SJW_3 = ((uint8_t)0x02), //!< 3 time quantum
CAN_SJW_4 = ((uint8_t)0x03) //!< 4 time quantum
} CAN_SJW_T;
/**
* @brief CAN time quantum in bit segment 1
*/
typedef enum
{
CAN_TIME_SEGMENT1_1 = ((uint8_t)0x00), //!< 1 time quanta
CAN_TIME_SEGMENT1_2 = ((uint8_t)0x01), //!< 2 time quanta
CAN_TIME_SEGMENT1_3 = ((uint8_t)0x02), //!< 3 time quanta
CAN_TIME_SEGMENT1_4 = ((uint8_t)0x03), //!< 4 time quanta
CAN_TIME_SEGMENT1_5 = ((uint8_t)0x04), //!< 5 time quanta
CAN_TIME_SEGMENT1_6 = ((uint8_t)0x05), //!< 6 time quanta
CAN_TIME_SEGMENT1_7 = ((uint8_t)0x06), //!< 7 time quanta
CAN_TIME_SEGMENT1_8 = ((uint8_t)0x07), //!< 8 time quanta
CAN_TIME_SEGMENT1_9 = ((uint8_t)0x08), //!< 9 time quanta
CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09), //!< 10 time quanta
CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A), //!< 11 time quanta
CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B), //!< 12 time quanta
CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C), //!< 13 time quanta
CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D), //!< 14 time quanta
CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E), //!< 15 time quanta
CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F) //!< 16 time quanta
} CAN_TIME_SEGMENT1_T;
/**
* @brief CAN time quantum in bit segment 2
*/
typedef enum
{
CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, //!< 1 time quanta
CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, //!< 2 time quanta
CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, //!< 3 time quanta
CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, //!< 4 time quanta
CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, //!< 5 time quanta
CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, //!< 6 time quanta
CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, //!< 7 time quanta
CAN_TIME_SEGMENT2_8 = (uint8_t)0x07 //!< 8 time quanta
} CAN_TIME_SEGMENT2_T;
/**
* @brief CAN filter FIFO
*/
typedef enum
{
CAN_FILTER_FIFO_0 = ((uint8_t)0x00), //!< filter FIFO 0
CAN_FILTER_FIFO_1 = ((uint8_t)0x01) //!< filter FIFO 1
} CAN_FILTER_FIFO_T;
/**
* @brief CAN filter mode
*/
typedef enum
{
CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),//!< identifier/mask mode
CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) //!< identifier list mode
} CAN_FILTER_MODE_T;
/**
* @brief CAN filter scale
*/
typedef enum
{
CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters
CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01) //!< One 32-bit filter
} CAN_FILTER_SCALE_T;
/**
* @brief CAN identifier type
*/
typedef enum
{
CAN_TYPEID_STD = ((uint32_t)0x00000000), //!< Standard Id
CAN_TYPEID_EXT = ((uint32_t)0x00000004) //!< Extended Id
} CAN_TYPEID_T;
/**
* @brief CAN_remote_transmission_request
*/
typedef enum
{
CAN_RTXR_DATA = ((uint32_t)0x00000000), //!< Data frame
CAN_RTXR_REMOTE = ((uint32_t)0x00000002) //!< Remote frame
} CAN_RTXR_T;
/**
* @brief Mailboxes definition
*/
typedef enum
{
CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0
CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1
CAN_TX_MAILBIX_2 = ((uint8_t)0x02) //!< Tx mailbox2
} CAN_TX_MAILBIX_T;
/**
* @brief CAN receive FIFO number constants
*/
typedef enum
{
CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0
CAN_RX_FIFO_1 = ((uint8_t)0x01) //!< receive FIFO 1
} CAN_RX_FIFO_T;
/**
* @brief CAN Operating Mode
*/
typedef enum
{
CAN_OPERATING_MODE_INIT = ((uint8_t)0x00), //!< Initialization mode
CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), //!< Normal mode
CAN_OPERATING_MODE_SLEEP = ((uint8_t)0x02) //!< sleep mode
} CAN_OPERATING_MODE_T;
/**
* @brief CAN Interrupts
*/
typedef enum
{
CAN_INT_TXME = ((uint32_t)0x00000001), //!< Transmit mailbox empty Interrupt
CAN_INT_F0MP = ((uint32_t)0x00000002), //!< FIFO 0 message pending Interrupt
CAN_INT_F0FULL = ((uint32_t)0x00000004), //!< FIFO 0 full Interrupt
CAN_INT_F0OVR = ((uint32_t)0x00000008), //!< FIFO 0 overrun Interrupt
CAN_INT_F1MP = ((uint32_t)0x00000010), //!< FIFO 1 message pending Interrupt
CAN_INT_F1FULL = ((uint32_t)0x00000020), //!< FIFO 1 full Interrupt
CAN_INT_F1OVR = ((uint32_t)0x00000040), //!< FIFO 1 overrun Interrupt
CAN_INT_ERRW = ((uint32_t)0x00000100), //!< Error warning Interrupt
CAN_INT_ERRP = ((uint32_t)0x00000200), //!< Error passive Interrupt
CAN_INT_BOF = ((uint32_t)0x00000400), //!< Bus-off Interrupt
CAN_INT_LEC = ((uint32_t)0x00000800), //!< Last error record code Interrupt
CAN_INT_ERR = ((uint32_t)0x00008000), //!< Error Interrupt
CAN_INT_WUP = ((uint32_t)0x00010000), //!< Wake-up Interrupt
CAN_INT_SLEEP = ((uint32_t)0x00020000) //!< Sleep acknowledge Interrupt
} CAN_INT_T;
/**
* @brief CAN Flags
*/
typedef enum
{
/** Error flag*/
CAN_FLAG_ERRW = ((uint32_t)0x10F00001), //!< Error Warning Flag
CAN_FLAG_ERRP = ((uint32_t)0x10F00002), //!< Error Passive Flag
CAN_FLAG_BOF = ((uint32_t)0x10F00004), //!< Bus-Off Flag
CAN_FLAG_LERRC = ((uint32_t)0x30F00070), //!< Last error record code Flag
/** Operating Mode Flags */
CAN_FLAG_WUPI = ((uint32_t)0x31000008), //!< Wake up Flag
CAN_FLAG_SLEEP = ((uint32_t)0x31000012), //!< Sleep acknowledge Flag
/** Receive Flags */
CAN_FLAG_F0MP = ((uint32_t)0x12000003), //!< FIFO 0 Message Pending Flag
CAN_FLAG_F0FULL = ((uint32_t)0x32000008), //!< FIFO 0 Full Flag
CAN_FLAG_F0OVR = ((uint32_t)0x32000010), //!< FIFO 0 Overrun Flag
CAN_FLAG_F1MP = ((uint32_t)0x14000003), //!< FIFO 1 Message Pending Flag
CAN_FLAG_F1FULL = ((uint32_t)0x34000008), //!< FIFO 1 Full Flag
CAN_FLAG_F1OVR = ((uint32_t)0x34000010), //!< FIFO 1 Overrun Flag
/** Transmit Flags */
CAN_FLAG_REQC0 = ((uint32_t)0x38000001), //!< Request MailBox0 Flag
CAN_FLAG_REQC1 = ((uint32_t)0x38000100), //!< Request MailBox1 Flag
CAN_FLAG_REQC2 = ((uint32_t)0x38010000) //!< Request MailBox2 Flag
} CAN_FLAG_T;
/**@} end of group CAN_Enumerations*/
/**
* @brief CAN Config structure definition
*/
/**
* @brief CAN config structure definition
*/
typedef struct
{
uint8_t autoBusOffManage; //!< Enable or disable the automatic bus-off management.
uint8_t autoWakeUpMode; //!< Enable or disable the automatic wake-up mode.
uint8_t nonAutoRetran; //!< Enable or disable the non-automatic retransmission mode.
uint8_t rxFIFOLockMode; //!< Enable or disable the Receive FIFO Locked mode.
uint8_t txFIFOPriority; //!< Enable or disable the transmit FIFO priority.
CAN_MODE_T mode; //!< Specifies the CAN operating mode.
CAN_SJW_T syncJumpWidth; /** Specifies the maximum number of time quanta the CAN hardware
* is allowed to lengthen or shorten a bit to perform resynchronization.
*/
CAN_TIME_SEGMENT1_T timeSegment1; //!< Specifies the number of time quanta in Bit Segment 1.
CAN_TIME_SEGMENT2_T timeSegment2; //!< Specifies the number of time quanta in Bit Segment 2.
uint16_t prescaler; //!< Specifies the length of a time quantum. It can be 1 to 1024.
} CAN_Config_T;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF.
uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
CAN_TYPEID_T typeID;
CAN_RTXR_T remoteTxReq;
uint8_t dataLengthCode;//!< Specifies the data length code. It can be 0 to 8.
uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
} CAN_TxMessage_T;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF.
uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
uint32_t typeID;
uint32_t remoteTxReq;
uint8_t dataLengthCode; //!< Specifies the data length code. It can be 0 to 8.
uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
uint8_t filterMatchIndex;//!< Specifies the filter match index. It can be 0 to 0xFF.
} CAN_RxMessage_T;
/**
* @brief CAN filter config structure definition
*/
typedef struct
{
uint8_t filterNumber; //!< Specifies the filter number. It can be 0 to 13.
uint16_t filterIdHigh; //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
uint16_t filterIdLow; //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
uint16_t filterMaskIdHigh; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF.
uint16_t filterMaskIdLow; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF.
uint16_t filterActivation; //!< Specifies the filter Activation. It can be ENABLE or DISABLE.
CAN_FILTER_FIFO_T filterFIFO;
CAN_FILTER_MODE_T filterMode;
CAN_FILTER_SCALE_T filterScale;
} CAN_FilterConfig_T;
/**@} end of group CAN_Structure*/
/** @addtogroup CAN_Fuctions Fuctions
@{
*/
/** CAN reset and configuration */
void CAN_Reset(CAN_T* can);
uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig);
void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig);
void CAN_ConfigStructInit(CAN_Config_T* canConfig);
void CAN_EnableDBGFreeze(CAN_T* can);
void CAN_DisableDBGFreeze(CAN_T* can);
void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum);
/** CAN frames transmit */
uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage);
uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
/** CAN frames receive */
void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage);
void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
/** CAN operation modes */
uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode);
uint8_t CAN_SleepMode(CAN_T* can);
uint8_t CAN_WakeUpMode(CAN_T* can);
/** CAN bus error management */
uint8_t CAN_ReadLastErrorCode(CAN_T* can);
uint8_t CAN_ReadRxErrorCounter(CAN_T* can);
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can);
/** CAN interrupt and flag */
void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt);
void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt);
uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag);
void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag);
uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag);
void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag);
/**@} end of group CAN_Fuctions*/
/**@} end of group CAN_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_CAN_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h
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/*!
* @file apm32f10x_crc.h
*
* @brief This file contains all the functions prototypes for the CRC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_CRC_H
#define __APM32F10X_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup CRC_Driver CRC Driver
@{
*/
/** @addtogroup CRC_Fuctions Fuctions
@{
*/
/** Reset DATA */
void CRC_ResetDATA(void);
/** Operation functions */
uint32_t CRC_CalculateCRC(uint32_t data);
uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen);
uint32_t CRC_ReadCRC(void);
void CRC_WriteIDRegister(uint8_t inData);
uint8_t CRC_ReadIDRegister(void);
/**@} end of group CRC_Fuctions*/
/**@} end of group CRC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_CRC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h
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/*!
* @file apm32f10x_dac.h
*
* @brief This file contains all the functions prototypes for the DAC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DAC_H
#define __APM32F10X_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DAC_Driver DAC Driver
@{
*/
/** @addtogroup DAC_Enumerations Enumerations
@{
*/
/**
* @brief DAC Channel selection
*/
typedef enum
{
DAC_CHANNEL_1 = 0x00000000,
DAC_CHANNEL_2 = 0x00000010
}DAC_CHANNEL_T;
/**
* @brief DAC trigger selection
*/
typedef enum
{
DAC_TRIGGER_NONE = 0x00000000,
DAC_TRIGGER_TMR6_TRGO = 0x00000004,
DAC_TRIGGER_TMR8_TRGO = 0x0000000C,
DAC_TRIGGER_TMR7_TRGO = 0x00000014,
DAC_TRIGGER_TMR5_TRGO = 0x0000001C,
DAC_TRIGGER_TMR2_TRGO = 0x00000024,
DAC_TRIGGER_TMR4_TRGO = 0x0000002C,
DAC_TRIGGER_EINT9 = 0x00000034,
DAC_TRIGGER_SOFT = 0x0000003C
}DAC_TRIGGER_T;
/**
* @brief DAC wave generation
*/
typedef enum
{
DAC_WAVE_GENERATION_NONE = 0x00000000,
DAC_WAVE_GENERATION_NOISE = 0x00000040,
DAC_WAVE_GENERATION_TRIANGLE = 0x00000080
}DAC_WAVE_GENERATION_T;
/**
* @brief DAC channelx mask/amplitude selector
*/
typedef enum
{
DAC_LFSR_MASK_BIT11_1 = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_2 = 0x00000100, //!< Mask bit[11:2] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_3 = 0x00000200, //!< Mask bit[11:3] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_4 = 0x00000300, //!< Mask bit[11:4] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_5 = 0x00000400, //!< Mask bit[11:5] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_6 = 0x00000500, //!< Mask bit[11:6] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_7 = 0x00000600, //!< Mask bit[11:7] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_8 = 0x00000700, //!< Mask bit[11:8] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_9 = 0x00000800, //!< Mask bit[11:9] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_10 = 0x00000900, //!< Mask bit[11:10] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11 = 0x00000A00, //!< Mask bit11 of LFSR for noise wave generation
DAC_LFSR_MASK_NONE = 0x00000B00, //!< Mask none bit of LFSR for noise wave generation
DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, //!< Triangle amplitude equal to 1
DAC_TRIANGLE_AMPLITUDE_3 = 0x00000100, //!< Triangle amplitude equal to 3
DAC_TRIANGLE_AMPLITUDE_7 = 0x00000200, //!< Triangle amplitude equal to 7
DAC_TRIANGLE_AMPLITUDE_15 = 0x00000300, //!< Triangle amplitude equal to 15
DAC_TRIANGLE_AMPLITUDE_31 = 0x00000400, //!< Triangle amplitude equal to 31
DAC_TRIANGLE_AMPLITUDE_63 = 0x00000500, //!< Triangle amplitude equal to 63
DAC_TRIANGLE_AMPLITUDE_127 = 0x00000600, //!< Triangle amplitude equal to 127
DAC_TRIANGLE_AMPLITUDE_255 = 0x00000700, //!< Triangle amplitude equal to 255
DAC_TRIANGLE_AMPLITUDE_511 = 0x00000800, //!< Triangle amplitude equal to 511
DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023
DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047
DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00 //!< Triangle amplitude equal to 4095
}DAC_MASK_AMPLITUDE_SEL_T;
/**
* @brief DAC output buffer
*/
typedef enum
{
DAC_OUTPUT_BUFFER_ENBALE = 0x00000000,
DAC_OUTPUT_BUFFER_DISABLE = 0x00000002
}DAC_OUTPUT_BUFFER_T;
/**
* @brief DAC data align
*/
typedef enum
{
DAC_ALIGN_12BIT_R = 0x00000000,
DAC_ALIGN_12BIT_L = 0x00000004,
DAC_ALIGN_8BIT_R = 0x00000008
}DAC_ALIGN_T;
/**@} end of group DAC_Enumerations*/
/** @addtogroup DAC_Structure Data Structure
@{
*/
/**
* @brief DAC Config structure definition
*/
typedef struct
{
DAC_TRIGGER_T trigger;
DAC_OUTPUT_BUFFER_T outputBuffer;
DAC_WAVE_GENERATION_T waveGeneration;
DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect;
}DAC_Config_T;
/**@} end of group DAC_Structure*/
/** @addtogroup DAC_Fuctions Fuctions
@{
*/
/** DAC Reset and Configuration */
void DAC_Reset(void);
void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig);
void DAC_ConfigStructInit(DAC_Config_T* dacConfig);
void DAC_Enable(DAC_CHANNEL_T channel);
void DAC_Disable(DAC_CHANNEL_T channel);
/** DAC channel for DAM */
void DAC_DMA_Enable(DAC_CHANNEL_T channel);
void DAC_DMA_Disable(DAC_CHANNEL_T channel);
/** DAC channel software trigger */
void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel);
void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel);
void DAC_EnableDualSoftwareTrigger(void);
void DAC_DisableDualSoftwareTrigger(void);
/** DAC channel wave generation */
void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
/** DAC set channel data */
void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data);
void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data);
void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1);
/** DAC read data output value */
uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel);
/**@} end of group DAC_Fuctions*/
/**@} end of group DAC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DAC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h
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/*!
* @file apm32f10x_dbgmcu.h
*
* @brief This file contains all the functions prototypes for the DBUGMCU firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DBGMCU_H
#define __APM32F10X_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DBGMCU_Driver DBGMCU Driver
@{
*/
/** @addtogroup DBGMCU_Enumerations Enumerations
@{
*/
enum
{
DBGMCU_SLEEP = ((uint32_t)0x00000001),
DBGMCU_STOP = ((uint32_t)0x00000002),
DBGMCU_STANDBY = ((uint32_t)0x00000004),
DBGMCU_IWDT_STOP = ((uint32_t)0x00000100),
DBGMCU_WWDT_STOP = ((uint32_t)0x00000200),
DBGMCU_TMR1_STOP = ((uint32_t)0x00000400),
DBGMCU_TMR2_STOP = ((uint32_t)0x00000800),
DBGMCU_TMR3_STOP = ((uint32_t)0x00001000),
DBGMCU_TMR4_STOP = ((uint32_t)0x00002000),
DBGMCU_CAN1_STOP = ((uint32_t)0x00004000),
DBGMCU_I2C1_SMBUS_TIMEOUT = ((uint32_t)0x00008000),
DBGMCU_I2C2_SMBUS_TIMEOUT = ((uint32_t)0x00010000),
DBGMCU_TMR8_STOP = ((uint32_t)0x00020000),
DBGMCU_TMR5_STOP = ((uint32_t)0x00040000),
DBGMCU_TMR6_STOP = ((uint32_t)0x00080000),
DBGMCU_TMR7_STOP = ((uint32_t)0x00100000),
DBGMCU_CAN2_STOP = ((uint32_t)0x00200000),
DBGMCU_TMR15_STOP = ((uint32_t)0x00400000),
DBGMCU_TMR16_STOP = ((uint32_t)0x00800000),
DBGMCU_TMR17_STOP = ((uint32_t)0x01000000),
DBGMCU_TMR12_STOP = ((uint32_t)0x02000000),
DBGMCU_TMR13_STOP = ((uint32_t)0x04000000),
DBGMCU_TMR14_STOP = ((uint32_t)0x08000000),
DBGMCU_TMR9_STOP = ((uint32_t)0x10000000),
DBGMCU_TMR10_STOP = ((uint32_t)0x20000000),
DBGMCU_TMR11_STOP = ((uint32_t)0x40000000),
};
/**@} end of group DBGMCU_Enumerations*/
/** @addtogroup DBGMCU_Fuctions Fuctions
@{
*/
uint32_t DBGMCU_ReadDEVID(void);
uint32_t DBGMCU_ReadREVID(void);
void DBGMCU_Enable(uint32_t periph);
void DBGMCU_Disable(uint32_t periph);
/**@} end of group DBGMCU_Fuctions*/
/**@} end of group DBGMCU_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DBGMCU_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h
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/*!
* @file apm32f10x_dma.h
*
* @brief This file contains all the functions prototypes for the DMA firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DMA_H
#define __APM32F10X_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DMA_Driver DMA Driver
@{
*/
/** @addtogroup DMA_Enumerations Enumerations
@{
*/
/**
* @brief DMA Transmission direction
*/
typedef enum
{
DMA_DIR_PERIPHERAL_SRC,
DMA_DIR_PERIPHERAL_DST
} DMA_DIR_T;
/**
* @brief DMA Peripheral address increment
*/
typedef enum
{
DMA_PERIPHERAL_INC_DISABLE,
DMA_PERIPHERAL_INC_ENABLE
} DMA_PERIPHERAL_INC_T;
/**
* @brief DMA Memory address increment
*/
typedef enum
{
DMA_MEMORY_INC_DISABLE,
DMA_MEMORY_INC_ENABLE
} DMA_MEMORY_INC_T;
/**
* @brief DMA Peripheral Data Size
*/
typedef enum
{
DMA_PERIPHERAL_DATA_SIZE_BYTE,
DMA_PERIPHERAL_DATA_SIZE_HALFWORD,
DMA_PERIPHERAL_DATA_SIZE_WOED
} DMA_PERIPHERAL_DATA_SIZE_T;
/**
* @brief DMA Memory Data Size
*/
typedef enum
{
DMA_MEMORY_DATA_SIZE_BYTE,
DMA_MEMORY_DATA_SIZE_HALFWORD,
DMA_MEMORY_DATA_SIZE_WOED
} DMA_MEMORY_DATA_SIZE_T;
/**
* @brief DMA Mode
*/
typedef enum
{
DMA_MODE_NORMAL,
DMA_MODE_CIRCULAR
} DMA_LOOP_MODE_T;
/**
* @brief DMA priority level
*/
typedef enum
{
DMA_PRIORITY_LOW,
DMA_PRIORITY_MEDIUM,
DMA_PRIORITY_HIGH,
DMA_PRIORITY_VERYHIGH
} DMA_PRIORITY_T;
/**
* @brief DMA Memory to Memory
*/
typedef enum
{
DMA_M2MEN_DISABLE,
DMA_M2MEN_ENABLE
} DMA_M2MEN_T;
/**
* @brief DMA interrupt
*/
typedef enum
{
DMA_INT_TC = 0x00000002,
DMA_INT_HT = 0x00000004,
DMA_INT_TERR = 0x00000008
} DMA_INT_T;
/**
* @brief DMA Flag
*/
typedef enum
{
DMA1_FLAG_GINT1 = 0x00000001,
DMA1_FLAG_TC1 = 0x00000002,
DMA1_FLAG_HT1 = 0x00000004,
DMA1_FLAG_TERR1 = 0x00000008,
DMA1_FLAG_GINT2 = 0x00000010,
DMA1_FLAG_TC2 = 0x00000020,
DMA1_FLAG_HT2 = 0x00000040,
DMA1_FLAG_TERR2 = 0x00000080,
DMA1_FLAG_GINT3 = 0x00000100,
DMA1_FLAG_TC3 = 0x00000200,
DMA1_FLAG_HT3 = 0x00000400,
DMA1_FLAG_TERR3 = 0x00000800,
DMA1_FLAG_GINT4 = 0x00001000,
DMA1_FLAG_TC4 = 0x00002000,
DMA1_FLAG_HT4 = 0x00004000,
DMA1_FLAG_TERR4 = 0x00008000,
DMA1_FLAG_GINT5 = 0x00010000,
DMA1_FLAG_TC5 = 0x00020000,
DMA1_FLAG_HT5 = 0x00040000,
DMA1_FLAG_TERR5 = 0x00080000,
DMA1_FLAG_GINT6 = 0x00100000,
DMA1_FLAG_TC6 = 0x00200000,
DMA1_FLAG_HT6 = 0x00400000,
DMA1_FLAG_TERR6 = 0x00800000,
DMA1_FLAG_GINT7 = 0x01000000,
DMA1_FLAG_TC7 = 0x02000000,
DMA1_FLAG_HT7 = 0x04000000,
DMA1_FLAG_TERR7 = 0x08000000,
DMA2_FLAG_GINT1 = 0x10000001,
DMA2_FLAG_TC1 = 0x10000002,
DMA2_FLAG_HT1 = 0x10000004,
DMA2_FLAG_TERR1 = 0x10000008,
DMA2_FLAG_GINT2 = 0x10000010,
DMA2_FLAG_TC2 = 0x10000020,
DMA2_FLAG_HT2 = 0x10000040,
DMA2_FLAG_TERR2 = 0x10000080,
DMA2_FLAG_GINT3 = 0x10000100,
DMA2_FLAG_TC3 = 0x10000200,
DMA2_FLAG_HT3 = 0x10000400,
DMA2_FLAG_TERR3 = 0x10000800,
DMA2_FLAG_GINT4 = 0x10001000,
DMA2_FLAG_TC4 = 0x10002000,
DMA2_FLAG_HT4 = 0x10004000,
DMA2_FLAG_TERR4 = 0x10008000,
DMA2_FLAG_GINT5 = 0x10010000,
DMA2_FLAG_TC5 = 0x10020000,
DMA2_FLAG_HT5 = 0x10040000,
DMA2_FLAG_TERR5 = 0x10080000
} DMA_FLAG_T;
/**
* @brief DMA Interrupt Flag
*/
typedef enum
{
DMA1_INT_FLAG_GINT1 = 0x00000001,
DMA1_INT_FLAG_TC1 = 0x00000002,
DMA1_INT_FLAG_HT1 = 0x00000004,
DMA1_INT_FLAG_TERR1 = 0x00000008,
DMA1_INT_FLAG_GINT2 = 0x00000010,
DMA1_INT_FLAG_TC2 = 0x00000020,
DMA1_INT_FLAG_HT2 = 0x00000040,
DMA1_INT_FLAG_TERR2 = 0x00000080,
DMA1_INT_FLAG_GINT3 = 0x00000100,
DMA1_INT_FLAG_TC3 = 0x00000200,
DMA1_INT_FLAG_HT3 = 0x00000400,
DMA1_INT_FLAG_TERR3 = 0x00000800,
DMA1_INT_FLAG_GINT4 = 0x00001000,
DMA1_INT_FLAG_TC4 = 0x00002000,
DMA1_INT_FLAG_HT4 = 0x00004000,
DMA1_INT_FLAG_TERR4 = 0x00008000,
DMA1_INT_FLAG_GINT5 = 0x00010000,
DMA1_INT_FLAG_TC5 = 0x00020000,
DMA1_INT_FLAG_HT5 = 0x00040000,
DMA1_INT_FLAG_TERR5 = 0x00080000,
DMA1_INT_FLAG_GINT6 = 0x00100000,
DMA1_INT_FLAG_TC6 = 0x00200000,
DMA1_INT_FLAG_HT6 = 0x00400000,
DMA1_INT_FLAG_TERR6 = 0x00800000,
DMA1_INT_FLAG_GINT7 = 0x01000000,
DMA1_INT_FLAG_TC7 = 0x02000000,
DMA1_INT_FLAG_HT7 = 0x04000000,
DMA1_INT_FLAG_TERR7 = 0x08000000,
DMA2_INT_FLAG_GINT1 = 0x10000001,
DMA2_INT_FLAG_TC1 = 0x10000002,
DMA2_INT_FLAG_HT1 = 0x10000004,
DMA2_INT_FLAG_TERR1 = 0x10000008,
DMA2_INT_FLAG_GINT2 = 0x10000010,
DMA2_INT_FLAG_TC2 = 0x10000020,
DMA2_INT_FLAG_HT2 = 0x10000040,
DMA2_INT_FLAG_TERR2 = 0x10000080,
DMA2_INT_FLAG_GINT3 = 0x10000100,
DMA2_INT_FLAG_TC3 = 0x10000200,
DMA2_INT_FLAG_HT3 = 0x10000400,
DMA2_INT_FLAG_TERR3 = 0x10000800,
DMA2_INT_FLAG_GINT4 = 0x10001000,
DMA2_INT_FLAG_TC4 = 0x10002000,
DMA2_INT_FLAG_HT4 = 0x10004000,
DMA2_INT_FLAG_TERR4 = 0x10008000,
DMA2_INT_FLAG_GINT5 = 0x10010000,
DMA2_INT_FLAG_TC5 = 0x10020000,
DMA2_INT_FLAG_HT5 = 0x10040000,
DMA2_INT_FLAG_TERR5 = 0x10080000
} DMA_INT_FLAG_T;
/**@} end of group DMA_Enumerations*/
/** @addtogroup DMA_Structure Data Structure
@{
*/
/**
* @brief DMA Config struct definition
*/
typedef struct
{
uint32_t peripheralBaseAddr;
uint32_t memoryBaseAddr;
DMA_DIR_T dir;
uint32_t bufferSize;
DMA_PERIPHERAL_INC_T peripheralInc;
DMA_MEMORY_INC_T memoryInc;
DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize;
DMA_MEMORY_DATA_SIZE_T memoryDataSize;
DMA_LOOP_MODE_T loopMode;
DMA_PRIORITY_T priority;
DMA_M2MEN_T M2M;
} DMA_Config_T;
/**@} end of group DMA_Structure*/
/** @addtogroup DMA_Fuctions Fuctions
@{
*/
/** Reset and configuration */
void DMA_Reset(DMA_Channel_T *channel);
void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
void DMA_ConfigStructInit( DMA_Config_T* dmaConfig);
void DMA_Enable(DMA_Channel_T *channel);
void DMA_Disable(DMA_Channel_T *channel);
/** Data number */
void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber);
uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel);
/** Interrupt and flag */
void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
void DMA_ClearStatusFlag(uint32_t flag);
uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
void DMA_ClearIntFlag(uint32_t flag);
/**@} end of group DMA_Fuctions*/
/**@} end of group DMA_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DMA_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h
+379
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/*!
* @file apm32f10x_dmc.h
*
* @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DMC_H
#define __APM32F10X_DMC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DMC_Driver DMC Driver
@{
*/
/** @addtogroup DMC_Enumerations Enumerations
@{
*/
/**
* @brief Bank Address Width
*/
typedef enum
{
DMC_BANK_WIDTH_1,
DMC_BANK_WIDTH_2
}DMC_BANK_WIDTH_T;
/**
* @brief Row Address Width
*/
typedef enum
{
DMC_ROW_WIDTH_11 = 0x0A,
DMC_ROW_WIDTH_12,
DMC_ROW_WIDTH_13,
DMC_ROW_WIDTH_14,
DMC_ROW_WIDTH_15,
DMC_ROW_WIDTH_16
}DMC_ROW_WIDTH_T;
/**
* @brief Column Address Width
*/
typedef enum
{
DMC_COL_WIDTH_8 = 0x07,
DMC_COL_WIDTH_9,
DMC_COL_WIDTH_10,
DMC_COL_WIDTH_11,
DMC_COL_WIDTH_12,
DMC_COL_WIDTH_13,
DMC_COL_WIDTH_14,
DMC_COL_WIDTH_15
}DMC_COL_WIDTH_T;
/**
* @brief CAS Latency Select
*/
typedef enum
{
DMC_CAS_LATENCY_1,
DMC_CAS_LATENCY_2,
DMC_CAS_LATENCY_3,
DMC_CAS_LATENCY_4
}DMC_CAS_LATENCY_T;
/**
* @brief RAS Minimun Time Select
*/
typedef enum
{
DMC_RAS_MINIMUM_1,
DMC_RAS_MINIMUM_2,
DMC_RAS_MINIMUM_3,
DMC_RAS_MINIMUM_4,
DMC_RAS_MINIMUM_5,
DMC_RAS_MINIMUM_6,
DMC_RAS_MINIMUM_7,
DMC_RAS_MINIMUM_8,
DMC_RAS_MINIMUM_9,
DMC_RAS_MINIMUM_10,
DMC_RAS_MINIMUM_11,
DMC_RAS_MINIMUM_12,
DMC_RAS_MINIMUM_13,
DMC_RAS_MINIMUM_14,
DMC_RAS_MINIMUM_15,
DMC_RAS_MINIMUM_16
}DMC_RAS_MINIMUM_T;
/**
* @brief RAS To CAS Delay Time Select
*/
typedef enum
{
DMC_DELAY_TIME_1,
DMC_DELAY_TIME_2,
DMC_DELAY_TIME_3,
DMC_DELAY_TIME_4,
DMC_DELAY_TIME_5,
DMC_DELAY_TIME_6,
DMC_DELAY_TIME_7,
DMC_DELAY_TIME_8
}DMC_DELAY_TIME_T;
/**
* @brief Precharge Period Select
*/
typedef enum
{
DMC_PRECHARGE_1,
DMC_PRECHARGE_2,
DMC_PRECHARGE_3,
DMC_PRECHARGE_4,
DMC_PRECHARGE_5,
DMC_PRECHARGE_6,
DMC_PRECHARGE_7,
DMC_PRECHARGE_8
}DMC_PRECHARGE_T;
/**
* @brief Last Data Next Precharge For Write Time Select
*/
typedef enum
{
DMC_NEXT_PRECHARGE_1,
DMC_NEXT_PRECHARGE_2,
DMC_NEXT_PRECHARGE_3,
DMC_NEXT_PRECHARGE_4
}DMC_NEXT_PRECHARGE_T;
/**
* @brief Auto-Refresh Period Select
*/
typedef enum
{
DMC_AUTO_REFRESH_1,
DMC_AUTO_REFRESH_2,
DMC_AUTO_REFRESH_3,
DMC_AUTO_REFRESH_4,
DMC_AUTO_REFRESH_5,
DMC_AUTO_REFRESH_6,
DMC_AUTO_REFRESH_7,
DMC_AUTO_REFRESH_8,
DMC_AUTO_REFRESH_9,
DMC_AUTO_REFRESH_10,
DMC_AUTO_REFRESH_11,
DMC_AUTO_REFRESH_12,
DMC_AUTO_REFRESH_13,
DMC_AUTO_REFRESH_14,
DMC_AUTO_REFRESH_15,
DMC_AUTO_REFRESH_16,
}DMC_AUTO_REFRESH_T;
/**
* @brief Active-to-active Command Period Select
*/
typedef enum
{
DMC_ATA_CMD_1,
DMC_ATA_CMD_2,
DMC_ATA_CMD_3,
DMC_ATA_CMD_4,
DMC_ATA_CMD_5,
DMC_ATA_CMD_6,
DMC_ATA_CMD_7,
DMC_ATA_CMD_8,
DMC_ATA_CMD_9,
DMC_ATA_CMD_10,
DMC_ATA_CMD_11,
DMC_ATA_CMD_12,
DMC_ATA_CMD_13,
DMC_ATA_CMD_14,
DMC_ATA_CMD_15,
DMC_ATA_CMD_16,
}DMC_ATA_CMD_T;
/**
* @brief Clock PHASE
*/
typedef enum
{
DMC_CLK_PHASE_NORMAL,
DMC_CLK_PHASE_REVERSE
}DMC_CLK_PHASE_T;
/**
* @brief DMC Memory Size
*/
typedef enum
{
DMC_MEMORY_SIZE_0,
DMC_MEMORY_SIZE_64KB,
DMC_MEMORY_SIZE_128KB,
DMC_MEMORY_SIZE_256KB,
DMC_MEMORY_SIZE_512KB,
DMC_MEMORY_SIZE_1MB,
DMC_MEMORY_SIZE_2MB,
DMC_MEMORY_SIZE_4MB,
DMC_MEMORY_SIZE_8MB,
DMC_MEMORY_SIZE_16MB,
DMC_MEMORY_SIZE_32MB,
DMC_MEMORY_SIZE_64MB,
DMC_MEMORY_SIZE_128MB,
DMC_MEMORY_SIZE_256MB,
}DMC_MEMORY_SIZE_T;
/**
* @brief Open Banks Of Number
*/
typedef enum
{
DMC_BANK_NUMBER_1,
DMC_BANK_NUMBER_2,
DMC_BANK_NUMBER_3,
DMC_BANK_NUMBER_4,
DMC_BANK_NUMBER_5,
DMC_BANK_NUMBER_6,
DMC_BANK_NUMBER_7,
DMC_BANK_NUMBER_8,
DMC_BANK_NUMBER_9,
DMC_BANK_NUMBER_10,
DMC_BANK_NUMBER_11,
DMC_BANK_NUMBER_12,
DMC_BANK_NUMBER_13,
DMC_BANK_NUMBER_14,
DMC_BANK_NUMBER_15,
DMC_BANK_NUMBER_16,
}DMC_BANK_NUMBER_T;
/**
* @brief Full refresh type
*/
typedef enum
{
DMC_REFRESH_ROW_ONE, //!< Refresh one row
DMC_REFRESH_ROW_ALL, //!< Refresh all row
}DMC_REFRESH_T;
/**
* @brief Precharge type
*/
typedef enum
{
DMC_PRECHARGE_IM, //!< Immediate precharge
DMC_PRECHARGE_DELAY, //!< Delayed precharge
}DMC_PRECHARE_T;
/**
* @brief WRAP Burst Type
*/
typedef enum
{
DMC_WRAPB_4,
DMC_WRAPB_8,
}DMC_WRPB_T;
/**@} end of group DMC_Enumerations*/
/** @addtogroup DMC_Structure Data Structure
@{
*/
/**
* @brief Timing config definition
*/
typedef struct
{
uint32_t latencyCAS : 2; //!< DMC_CAS_LATENCY_T
uint32_t tRAS : 4; //!< DMC_RAS_MINIMUM_T
uint32_t tRCD : 3; //!< DMC_DELAY_TIME_T
uint32_t tRP : 3; //!< DMC_PRECHARGE_T
uint32_t tWR : 2; //!< DMC_NEXT_PRECHARGE_T
uint32_t tARP : 4; //!< DMC_AUTO_REFRESH_T
uint32_t tCMD : 4; //!< DMC_ATA_CMD_T
uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF
uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF
}DMC_TimingConfig_T;
/**
* @brief Config struct definition
*/
typedef struct
{
DMC_MEMORY_SIZE_T memorySize; //!< Memory size(byte)
DMC_BANK_WIDTH_T bankWidth; //!< Number of bank bits
DMC_ROW_WIDTH_T rowWidth; //!< Number of row address bits
DMC_COL_WIDTH_T colWidth; //!< Number of col address bits
DMC_CLK_PHASE_T clkPhase; //!< Clock phase
DMC_TimingConfig_T timing; //!< Timing
}DMC_Config_T;
/**@} end of group DMC_Structure*/
/** @addtogroup DMC_Fuctions Fuctions
@{
*/
/** Enable / Disable */
void DMC_Enable(void);
void DMC_Disable(void);
void DMC_EnableInit(void);
/** Global config */
void DMC_Config(DMC_Config_T* dmcConfig);
void DMC_ConfigStructInit(DMC_Config_T* dmcConfig);
/** Address */
void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
/** Timing */
void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig);
void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig);
void DMC_ConfigStableTimePowerup(uint16_t stableTime);
void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
void DMC_ConfigRefreshPeriod(uint16_t period);
/** Refresh mode */
void DMC_EixtSlefRefreshMode(void);
void DMC_EnterSlefRefreshMode(void);
/** Accelerate Module */
void DMC_EnableAccelerateModule(void);
void DMC_DisableAccelerateModule(void);
/** Config */
void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
void DMC_EnableUpdateMode(void);
void DMC_EnterPowerdownMode(void);
void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh);
void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
void DMC_ConfigWRAPB(DMC_WRPB_T burst);
/** read flag */
uint8_t DMC_ReadSelfRefreshStatus(void);
/**@} end of group DMC_Fuctions*/
/**@} end of group DMC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DMC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h
+135
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/*!
* @file apm32f10x_eint.h
*
* @brief This file contains all the functions prototypes for the EINT firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_EINT_H
#define __APM32F10X_EINT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup EINT_Driver EINT Driver
@{
*/
/** @addtogroup EINT_Enumerations Enumerations
@{
*/
/**
* @brief EINT mode enumeration
*/
typedef enum
{
EINT_MODE_INTERRUPT = 0x00,
EINT_MODE_EVENT = 0x04
} EINT_MODE_T;
/**
* @brief EINT Trigger enumeration
*/
typedef enum
{
EINT_TRIGGER_RISING = 0x08,
EINT_TRIGGER_FALLING = 0x0C,
EINT_TRIGGER_RISING_FALLING = 0x10
} EINT_TRIGGER_T;
typedef enum
{
EINT_LINENONE = 0x00000, //!<No interrupt selected >
EINT_LINE_0 = 0x00001, //!< External interrupt line 0
EINT_LINE_1 = 0x00002, //!< External interrupt line 1
EINT_LINE_2 = 0x00004, //!< External interrupt line 2
EINT_LINE_3 = 0x00008, //!< External interrupt line 3
EINT_LINE_4 = 0x00010, //!< External interrupt line 4
EINT_LINE_5 = 0x00020, //!< External interrupt line 5
EINT_LINE_6 = 0x00040, //!< External interrupt line 6
EINT_LINE_7 = 0x00080, //!< External interrupt line 7
EINT_LINE_8 = 0x00100, //!< External interrupt line 8
EINT_LINE_9 = 0x00200, //!< External interrupt line 9
EINT_LINE_10 = 0x00400, //!< External interrupt line 10
EINT_LINE_11 = 0x00800, //!< External interrupt line 11
EINT_LINE_12 = 0x01000, //!< External interrupt line 12
EINT_LINE_13 = 0x02000, //!< External interrupt line 13
EINT_LINE_14 = 0x04000, //!< External interrupt line 14
EINT_LINE_15 = 0x08000, //!< External interrupt line 15
EINT_LINE_16 = 0x10000, //!< External interrupt line 16 Connected to the PVD Output
EINT_LINE_17 = 0x20000, //!< External interrupt line 17 Connected to the RTC Alarm event
EINT_LINE_18 = 0x40000, //!< External interrupt line 18 Connected to the USB Device
} EINT_LINE_T;
/**@} end of group EINT_Enumerations*/
/** @addtogroup EINT_Structure Data Structure
@{
*/
/**
* @brief EINT Config structure definition
*/
typedef struct
{
uint32_t line;
EINT_MODE_T mode;
EINT_TRIGGER_T trigger;
uint8_t lineCmd;
} EINT_Config_T;
/**@} end of group EINT_Structure*/
/** @addtogroup EINT_Fuctions Fuctions
@{
*/
/** Reset and configuration */
void EINT_Reset(void);
void EINT_Config( EINT_Config_T* eintConfig);
void EINT_ConfigStructInit(EINT_Config_T* eintConfig);
/** Interrupt and flag */
void EINT_SelectSWInterrupt(uint32_t line);
uint8_t EINT_ReadStatusFlag(EINT_LINE_T line);
void EINT_ClearStatusFlag(uint32_t line);
uint8_t EINT_ReadIntFlag(EINT_LINE_T line);
void EINT_ClearIntFlag(uint32_t line);
/**@} end of group EINT_Fuctions*/
/**@} end of group EINT_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10XEINT_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h
+369
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/*!
* @file apm32f10x_emmc.h
*
* @brief This file contains all the functions prototypes for the EMMC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_EMMC_H
#define __APM32F10X_EMMC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup EMMC_Driver EMMC Driver
@{
*/
/** @addtogroup EMMC_Enumerations Enumerations
@{
*/
/**
* @brief EMMC NORSRAM_Bank
*/
typedef enum
{
EMMC_BANK1_NORSRAM_1 = 0x00000000,
EMMC_BANK1_NORSRAM_2 = 0x00000002,
EMMC_BANK1_NORSRAM_3 = 0x00000004,
EMMC_BANK1_NORSRAM_4 = 0x00000006
} EMMC_BANK1_NORSRAM_T;
/**
* @brief EMMC NAND and PC Card Bank
*/
typedef enum
{
EMMC_BANK2_NAND = 0x00000010,
EMMC_BANK3_NAND = 0x00000100,
EMMC_BANK4_PCCARD = 0x00001000
} EMMC_BANK_NAND_T;
/**
* @brief EMMC_Data_Address_Bus_Multiplexing
*/
typedef enum
{
EMMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000,
EMMC_DATA_ADDRESS_MUX_ENABLE = 0x00000002
} EMMC_DATA_ADDRESS_MUX_T;
/**
* @brief EMMC_Memory_Type
*/
typedef enum
{
EMMC_MEMORY_TYPE_SRAM = 0x00000000,
EMMC_MEMORY_TYPE_PSRAM = 0x00000004,
EMMC_MEMORY_TYPE_NOR = 0x00000008
} EMMC_MEMORY_TYPE_T;
/**
* @brief EMMC_Data_Width
*/
typedef enum
{
EMMC_MEMORY_DATA_WIDTH_8BIT = 0x00000000,
EMMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010
} EMMC_MEMORY_DATA_WIDTH_T;
/**
* @brief EMMC_Burst_Access_Mode
*/
typedef enum
{
EMMC_BURST_ACCESS_MODE_DISABLE = 0x00000000,
EMMC_BURST_ACCESS_MODE_ENABLE = 0x00000100
} EMMC_BURST_ACCESS_MODE_T;
/**
* @brief EMMC_AsynchronousWait
*/
typedef enum
{
EMMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000,
EMMC_ASYNCHRONOUS_WAIT_ENABLE = 0x00008000
} EMMC_ASYNCHRONOUS_WAIT_T;
/**
* @brief EMMC_Wait_Signal_Polarity
*/
typedef enum
{
EMMC_WAIT_SIGNAL_POLARITY_LOW = 0x00000000,
EMMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200
} EMMC_WAIT_SIGNAL_POLARITY_T;
/**
* @brief EMMC_Wrap_Mode
*/
typedef enum
{
EMMC_WRAP_MODE_DISABLE = 0x00000000,
EMMC_WRAP_MODE_ENABLE = 0x00000400
} EMMC_WRAP_MODE_T;
/**
* @brief EMMC_Wait_Timing
*/
typedef enum
{
EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000,
EMMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800
} EMMC_WAIT_SIGNAL_ACTIVE_T;
/**
* @brief EMMC_Write_Operation
*/
typedef enum
{
EMMC_WRITE_OPERATION_DISABLE = 0x00000000,
EMMC_WRITE_OPERATION_ENABLE = 0x00001000
} EMMC_WRITE_OPERATION_T;
/**
* @brief EMMC_Wait_Signal
*/
typedef enum
{
EMMC_WAITE_SIGNAL_DISABLE = 0x00000000,
EMMC_WAITE_SIGNAL_ENABLE = 0x00002000
} EMMC_WAITE_SIGNAL_T;
/**
* @brief EMMC_Extended_Mode
*/
typedef enum
{
EMMC_EXTENDEN_MODE_DISABLE = 0x00000000,
EMMC_EXTENDEN_MODE_ENABLE = 0x00004000
} EMMC_EXTENDEN_MODE_T;
/**
* @brief EMMC_Write_Burst
*/
typedef enum
{
EMMC_WRITE_BURST_DISABLE = 0x00000000,
EMMC_WRITE_BURST_ENABLE = 0x00080000
} EMMC_WRITE_BURST_T;
/**
* @brief EMMC_WAIT_FEATURE
*/
typedef enum
{
EMMC_WAIT_FEATURE_DISABLE = 0x00000000,
EMMC_WAIT_FEATURE_ENABLE = 0x00000002
} EMMC_WAIT_FEATURE_T;
/**
* @brief EMMC_ECC
*/
typedef enum
{
EMMC_ECC_DISABLE = 0x00000000,
EMMC_ECC_ENABLE = 0x00000040
} EMMC_ECC_T;
/**
* @brief EMMC_ECC_Page_Size
*/
typedef enum
{
EMMC_ECC_PAGE_SIZE_BYTE_256 = 0x00000000,
EMMC_ECC_PAGE_SIZE_BYTE_512 = 0x00020000,
EMMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000,
EMMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000,
EMMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000,
EMMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000
} EMMC_ECC_PAGE_SIZE_BYTE_T;
/**
* @brief EMMC_Access_Mode
*/
typedef enum
{
EMMC_ACCESS_MODE_A = 0x00000000,
EMMC_ACCESS_MODE_B = 0x10000000,
EMMC_ACCESS_MODE_C = 0x20000000,
EMMC_ACCESS_MODE_D = 0x30000000
} EMMC_ACCESS_MODE_T;
/**
* @brief EMMC_Interrupt_sources
*/
typedef enum
{
EMMC_INT_EDGE_RISING = 0x00000008,
EMMC_INT_LEVEL_HIGH = 0x00000010,
EMMC_INT_EDGE_FALLING = 0x00000020
} EMMC_INT_T;
/**
* @brief EMMC_Flags
*/
typedef enum
{
EMMC_FLAG_EDGE_RISING = 0x00000001,
EMMC_FLAG_LEVEL_HIGH = 0x00000002,
EMMC_FLAG_EDGE_FALLING = 0x00000004,
EMMC_FLAG_FIFO_EMPTY = 0x00000040
} EMMC_FLAG_T;
/**@} end of group EMMC_Enumerations*/
/** @addtogroup EMMC_Structure Data Structure
@{
*/
/**
* @brief Timing parameters for NOR/SRAM Banks
*/
typedef struct
{
uint32_t addressSetupTime;
uint32_t addressHodeTime;
uint32_t dataSetupTime;
uint32_t busTurnaroundTime;
uint32_t clockDivision;
uint32_t dataLatency;
EMMC_ACCESS_MODE_T accessMode;
} EMMC_NORSRAMTimingConfig_T;
/**
* @brief EMMC NOR/SRAM Config structure
*/
typedef struct
{
EMMC_BANK1_NORSRAM_T bank;
EMMC_DATA_ADDRESS_MUX_T dataAddressMux;
EMMC_MEMORY_TYPE_T memoryType;
EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth;
EMMC_BURST_ACCESS_MODE_T burstAcceesMode;
EMMC_ASYNCHRONOUS_WAIT_T asynchronousWait;
EMMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity;
EMMC_WRAP_MODE_T wrapMode;
EMMC_WAIT_SIGNAL_ACTIVE_T waitSignalActive;
EMMC_WRITE_OPERATION_T writeOperation;
EMMC_WAITE_SIGNAL_T waiteSignal;
EMMC_EXTENDEN_MODE_T extendedMode;
EMMC_WRITE_BURST_T writeBurst;
EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct;
EMMC_NORSRAMTimingConfig_T* writeTimingStruct;
} EMMC_NORSRAMConfig_T;
/**
* @brief Timing parameters for NAND and PCCARD Banks
*/
typedef struct
{
uint32_t setupTime;
uint32_t waitSetupTime;
uint32_t holdSetupTime;
uint32_t HiZSetupTime;
} EMMC_NAND_PCCARDTimingConfig_T;
/**
* @brief EMMC NAND Config structure
*/
typedef struct
{
EMMC_BANK_NAND_T bank;
EMMC_WAIT_FEATURE_T waitFeature;
EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth;
EMMC_ECC_T ECC;
EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
uint32_t TCLRSetupTime;
uint32_t TARSetupTime;
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
} EMMC_NANDConfig_T;
/**
* @brief EMMC PCCARD Config structure
*/
typedef struct
{
EMMC_WAIT_FEATURE_T waitFeature;
uint32_t TCLRSetupTime;
uint32_t TARSetupTime;
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
} EMMC_PCCARDConfig_T;
/**@} end of group EMMC_Structure*/
/** @addtogroup EMMC_Fuctions Fuctions
@{
*/
/** EMMC reset */
void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank);
void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
void EMMC_ResetPCCard(void);
/** EMMC Configuration */
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
/** EMMC bank control */
void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
void EMMC_EnableNAND(EMMC_BANK_NAND_T bank);
void EMMC_DisableNAND(EMMC_BANK_NAND_T bank);
void EMMC_EnablePCCARD(void);
void EMMC_DisablePCCARD(void);
void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank);
void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank);
uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank);
/** Interrupt and flag */
void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag);
void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag);
void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
/**@} end of group EMMC_Fuctions*/
/**@} end of group EMMC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_EMMC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h
+265
View File
@@ -0,0 +1,265 @@
/*!
* @file apm32f10x_fmc.h
*
* @brief This file contains all the functions prototypes for the FMC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_FMC_H
#define __APM32F10X_FMC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup FMC_Driver FMC Driver
@{
*/
/** @addtogroup FMC_Enumerations Enumerations
@{
*/
/**
* @brief Flash Latency
*/
typedef enum
{
FMC_LATENCY_0,
FMC_LATENCY_1,
FMC_LATENCY_2
} FMC_LATENCY_T;
/**
* @brief FMC Status
*/
typedef enum
{
FMC_STATUS_BUSY = 1, //!< flash busy
FMC_STATUS_ERROR_PG, //!< flash programming error
FMC_STATUS_ERROR_WRP, //!< flash write protection error
FMC_STATUS_COMPLETE, //!< flash operation complete
FMC_STATUS_TIMEOUT //!< flash time out
} FMC_STATUS_T;
/**
* @brief Option Bytes IWatchdog
*/
typedef enum
{
OB_IWDT_HARD = 0x0000,
OB_IWDT_SOTF = 0x0001
} OB_IWDT_T;
/**
* @brief Option Bytes nRST STOP
*/
typedef enum
{
OB_STOP_RST = 0x0000,
OB_STOP_NORST = 0x0002
} OB_STOP_T;
/**
* @brief Option Bytes nRST STDBY
*/
typedef enum
{
OB_STDBY_RST = 0x0000,
OB_STDBY_NORST = 0x0004
} OB_STDBY_T;
/**
* @brief FMC Interrupts
*/
typedef enum
{
FMC_INT_ERR,
FMC_INT_OC
} FMC_INT_T;
/**
* @brief FMC flag
*/
typedef enum
{
FMC_FLAG_BUSY = 0x00000001, //!< FMC Busy flag
FMC_FLAG_OC = 0x00000020, //!< FMC End of Operation flag
FMC_FLAG_PE = 0x00000004, //!< FMC Program error flag
FMC_FLAG_WPE = 0x00000010, //!< FMC Write protected error flag
FMC_FLAG_OBE = 0x10000001, //!< FMC Option Byte error flag
} FMC_FLAG_T;
/**@} end of group FMC_Enumerations*/
/** @addtogroup FMC_Macros Macros
@{
*/
/** Macros description */
/** Values for APM32 Low and Medium density devices */
#define FLASH_WRP_PAGE_0_3 ((uint32_t)BIT0) //!< Write protection of page 0 to 3
#define FLASH_WRP_PAGE_4_7 ((uint32_t)BIT1) //!< Write protection of page 4 to 7
#define FLASH_WRP_PAGE_8_11 ((uint32_t)BIT2) //!< Write protection of page 8 to 11
#define FLASH_WRP_PAGE_12_15 ((uint32_t)BIT3) //!< Write protection of page 12 to 15
#define FLASH_WRP_PAGE_16_19 ((uint32_t)BIT4) //!< Write protection of page 16 to 19
#define FLASH_WRP_PAGE_20_23 ((uint32_t)BIT5) //!< Write protection of page 20 to 23
#define FLASH_WRP_PAGE_24_27 ((uint32_t)BIT6) //!< Write protection of page 24 to 27
#define FLASH_WRP_PAGE_28_31 ((uint32_t)BIT7) //!< Write protection of page 28 to 31
/** Values for APM32 Medium-density devices */
#define FLASH_WRP_PAGE_32_35 ((uint32_t)BIT8) //!< Write protection of page 32 to 35
#define FLASH_WRP_PAGE_36_39 ((uint32_t)BIT9) //!< Write protection of page 36 to 39
#define FLASH_WRP_PAGE_40_43 ((uint32_t)BIT10) //!< Write protection of page 40 to 43
#define FLASH_WRP_PAGE_44_47 ((uint32_t)BIT11) //!< Write protection of page 44 to 47
#define FLASH_WRP_PAGE_48_51 ((uint32_t)BIT12) //!< Write protection of page 48 to 51
#define FLASH_WRP_PAGE_52_55 ((uint32_t)BIT13) //!< Write protection of page 52 to 55
#define FLASH_WRP_PAGE_56_59 ((uint32_t)BIT14) //!< Write protection of page 56 to 59
#define FLASH_WRP_PAGE_60_63 ((uint32_t)BIT15) //!< Write protection of page 60 to 63
#define FLASH_WRP_PAGE_64_67 ((uint32_t)BIT16) //!< Write protection of page 64 to 67
#define FLASH_WRP_PAGE_68_71 ((uint32_t)BIT17) //!< Write protection of page 68 to 71
#define FLASH_WRP_PAGE_72_75 ((uint32_t)BIT18) //!< Write protection of page 72 to 75
#define FLASH_WRP_PAGE_76_79 ((uint32_t)BIT19) //!< Write protection of page 76 to 79
#define FLASH_WRP_PAGE_80_83 ((uint32_t)BIT20) //!< Write protection of page 80 to 83
#define FLASH_WRP_PAGE_84_87 ((uint32_t)BIT21) //!< Write protection of page 84 to 87
#define FLASH_WRP_PAGE_88_91 ((uint32_t)BIT22) //!< Write protection of page 88 to 91
#define FLASH_WRP_PAGE_92_95 ((uint32_t)BIT23) //!< Write protection of page 92 to 95
#define FLASH_WRP_PAGE_96_99 ((uint32_t)BIT24) //!< Write protection of page 96 to 99
#define FLASH_WRP_PAGE_100_103 ((uint32_t)BIT25) //!< Write protection of page 100 to 103
#define FLASH_WRP_PAGE_104_107 ((uint32_t)BIT26) //!< Write protection of page 104 to 107
#define FLASH_WRP_PAGE_108_111 ((uint32_t)BIT27) //!< Write protection of page 108 to 111
#define FLASH_WRP_PAGE_112_115 ((uint32_t)BIT28) //!< Write protection of page 112 to 115
#define FLASH_WRP_PAGE_116_119 ((uint32_t)BIT29) //!< Write protection of page 116 to 119
#define FLASH_WRP_PAGE_120_123 ((uint32_t)BIT30) //!< Write protection of page 120 to 123
#define FLASH_WRP_PAGE_124_127 ((uint32_t)BIT31) //!< Write protection of page 124 to 127
/** Values only for APM32 High-density devices */
#define FLASH_WRP_PAGE_0_1 ((uint32_t)BIT0) //!< Write protection of page 0 to 1
#define FLASH_WRP_PAGE_2_3 ((uint32_t)BIT1) //!< Write protection of page 2 to 3
#define FLASH_WRP_PAGE_4_5 ((uint32_t)BIT2) //!< Write protection of page 4 to 5
#define FLASH_WRP_PAGE_6_7 ((uint32_t)BIT3) //!< Write protection of page 6 to 7
#define FLASH_WRP_PAGE_8_9 ((uint32_t)BIT4) //!< Write protection of page 8 to 9
#define FLASH_WRP_PAGE_10_11 ((uint32_t)BIT5) //!< Write protection of page 10 to 11
#define FLASH_WRP_PAGE_12_13 ((uint32_t)BIT6) //!< Write protection of page 12 to 13
#define FLASH_WRP_PAGE_14_15 ((uint32_t)BIT7) //!< Write protection of page 14 to 15
#define FLASH_WRP_PAGE_16_17 ((uint32_t)BIT8) //!< Write protection of page 16 to 17
#define FLASH_WRP_PAGE_18_19 ((uint32_t)BIT9) //!< Write protection of page 18 to 19
#define FLASH_WRP_PAGE_20_21 ((uint32_t)BIT10) //!< Write protection of page 20 to 21
#define FLASH_WRP_PAGE_22_23 ((uint32_t)BIT11) //!< Write protection of page 22 to 23
#define FLASH_WRP_PAGE_24_25 ((uint32_t)BIT12) //!< Write protection of page 24 to 25
#define FLASH_WRP_PAGE_26_27 ((uint32_t)BIT13) //!< Write protection of page 26 to 27
#define FLASH_WRP_PAGE_28_29 ((uint32_t)BIT14) //!< Write protection of page 28 to 29
#define FLASH_WRP_PAGE_30_31 ((uint32_t)BIT15) //!< Write protection of page 30 to 31
#define FLASH_WRP_PAGE_32_33 ((uint32_t)BIT16) //!< Write protection of page 32 to 33
#define FLASH_WRP_PAGE_34_35 ((uint32_t)BIT17) //!< Write protection of page 34 to 35
#define FLASH_WRP_PAGE_36_37 ((uint32_t)BIT18) //!< Write protection of page 36 to 37
#define FLASH_WRP_PAGE_38_39 ((uint32_t)BIT19) //!< Write protection of page 38 to 39
#define FLASH_WRP_PAGE_40_41 ((uint32_t)BIT20) //!< Write protection of page 40 to 41
#define FLASH_WRP_PAGE_42_43 ((uint32_t)BIT21) //!< Write protection of page 42 to 43
#define FLASH_WRP_PAGE_44_45 ((uint32_t)BIT22) //!< Write protection of page 44 to 45
#define FLASH_WRP_PAGE_46_47 ((uint32_t)BIT23) //!< Write protection of page 46 to 47
#define FLASH_WRP_PAGE_48_49 ((uint32_t)BIT24) //!< Write protection of page 48 to 49
#define FLASH_WRP_PAGE_50_51 ((uint32_t)BIT25) //!< Write protection of page 50 to 51
#define FLASH_WRP_PAGE_52_53 ((uint32_t)BIT26) //!< Write protection of page 52 to 53
#define FLASH_WRP_PAGE_54_55 ((uint32_t)BIT27) //!< Write protection of page 54 to 55
#define FLASH_WRP_PAGE_56_57 ((uint32_t)BIT28) //!< Write protection of page 56 to 57
#define FLASH_WRP_PAGE_58_59 ((uint32_t)BIT29) //!< Write protection of page 58 to 59
#define FLASH_WRP_PAGE_60_61 ((uint32_t)BIT30) //!< Write protection of page 60 to 61
#define FLASH_WRP_PAGE_62_127 ((uint32_t)BIT31) //!< Write protection of page 62 to 127
#define FMC_WRP_PAGE_ALL ((uint32_t)0xFFFFFFFF) //!< Write protection of page all */
/**@} end of group FMC_Macros*/
/** @addtogroup FMC_Structure Data Structure
@{
*/
/**
* @brief User Option byte config struct definition
*/
typedef struct
{
OB_IWDT_T iwdtSet;
OB_STOP_T stopSet;
OB_STDBY_T stdbySet;
} FMC_UserConfig_T;
/**@} end of group FMC_Structure*/
/** @addtogroup FMC_Fuctions Fuctions
@{
*/
/** Initialization and Configuration */
void FMC_ConfigLatency(FMC_LATENCY_T latency);
void FMC_EnableHalfCycleAccess(void);
void FMC_DisableHalfCycleAccess(void);
void FMC_EnablePrefetchBuffer(void);
void FMC_DisablePrefetchBuffer(void);
/** Lock management */
void FMC_Unlock(void);
void FMC_Lock(void);
/** Erase management */
FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr);
FMC_STATUS_T FMC_EraseAllPage(void);
FMC_STATUS_T FMC_EraseOptionBytes(void);
/** Read Write management */
FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data);
FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data);
FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data);
FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page);
FMC_STATUS_T FMC_EnableReadOutProtection(void);
FMC_STATUS_T FMC_DisableReadOutProtection(void);
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig);
uint32_t FMC_ReadUserOptionByte(void);
uint32_t FMC_ReadOptionByteWriteProtection(void);
uint8_t FMC_GetReadProtectionStatus(void);
uint8_t FMC_ReadPrefetchBufferStatus(void);
/** Interrupts and flags */
void FMC_EnableInterrupt(FMC_INT_T interrupt);
void FMC_DisableInterrupt(FMC_INT_T interrupt);
uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag);
void FMC_ClearStatusFlag(uint32_t flag);
/** Status management */
FMC_STATUS_T FMC_ReadStatus(void);
FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut);
/**@} end of group FMC_Fuctions*/
/**@} end of group FMC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_FMC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h
+261
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@@ -0,0 +1,261 @@
/*!
* @file apm32f10x_gpio.h
*
* @brief This file contains all the functions prototypes for the GPIO firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_GPIO_H
#define __APM32F10X_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup GPIO_Enumerations Enumerations
@{
*/
/**
* @brief GPIO Output Maximum frequency selection
*/
typedef enum
{
GPIO_SPEED_10MHz = 1,
GPIO_SPEED_20MHz,
GPIO_SPEED_50MHz
}GPIO_SPEED_T;
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_MODE_ANALOG = 0x0, //!< Analog mode
GPIO_MODE_IN_FLOATING = 0x04, //!< Floating input
GPIO_MODE_IN_PD = 0x28, //!< Input with pull-down
GPIO_MODE_IN_PU = 0x48, //!< Input with pull-up
GPIO_MODE_OUT_PP = 0x80, //!< General purpose output push-pull
GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain
GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull
GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain
}GPIO_MODE_T;
/**
* @brief Definition of the GPIO pins
*/
typedef enum
{
GPIO_PIN_0 = ((uint16_t)BIT0),
GPIO_PIN_1 = ((uint16_t)BIT1),
GPIO_PIN_2 = ((uint16_t)BIT2),
GPIO_PIN_3 = ((uint16_t)BIT3),
GPIO_PIN_4 = ((uint16_t)BIT4),
GPIO_PIN_5 = ((uint16_t)BIT5),
GPIO_PIN_6 = ((uint16_t)BIT6),
GPIO_PIN_7 = ((uint16_t)BIT7),
GPIO_PIN_8 = ((uint16_t)BIT8),
GPIO_PIN_9 = ((uint16_t)BIT9),
GPIO_PIN_10 = ((uint16_t)BIT10),
GPIO_PIN_11 = ((uint16_t)BIT11),
GPIO_PIN_12 = ((uint16_t)BIT12),
GPIO_PIN_13 = ((uint16_t)BIT13),
GPIO_PIN_14 = ((uint16_t)BIT14),
GPIO_PIN_15 = ((uint16_t)BIT15),
GPIO_PIN_ALL = ((uint32_t)0XFFFF),
} GPIO_PIN_T;
/**
* @brief GPIO remap type define
*/
typedef enum
{
GPIO_NO_REMAP_SPI1 = 0x00000010,
GPIO_REMAP_SPI1 = 0x00000011,
GPIO_NO_REMAP_I2C1 = 0x00000110,
GPIO_REMAP_I2C1 = 0x00000111,
GPIO_NO_REMAP_USART1 = 0x00000210,
GPIO_REMAP_USART1 = 0x00000211,
GPIO_NO_REMAP_USART2 = 0x00000310,
GPIO_REMAP_USART2 = 0x00000311,
GPIO_NO_REMAP_USART3 = 0x00000430,
GPIO_PARTIAL_REMAP_USART3 = 0x00000431,
GPIO_FULL_REMAP_USART3 = 0x00000433,
GPIO_NO_REMAP_TMR1 = 0x00000630,
GPIO_PARTIAL_REMAP_TMR1 = 0x00000631,
GPIO_FULL_REMAP_TMR1 = 0x00000633,
GPIO_NO_REMAP_TMR2 = 0x00000830,
GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831,
GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832,
GPIO_FULL_REMAP_TMR2 = 0x00000833,
GPIO_NO_REMAP_TMR3 = 0x00000A30,
GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32,
GPIO_FULL_REMAP_TMR3 = 0x00000A33,
GPIO_NO_REMAP_TMR4 = 0x00000C10,
GPIO_REMAP_TMR4 = 0x00000C11,
GPIO_NO_REMAP_CAN1 = 0x00000D30,
GPIO_REMAP1_CAN1 = 0x00000D32,
GPIO_REMAP2_CAN1 = 0x00000D33,
GPIO_NO_REMAP_PD01 = 0x00000F10,
GPIO_REMAP_PD01 = 0x00000F11,
GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010,
GPIO_REMAP_TMR5CH4_LSI = 0x00001011,
GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110,
GPIO_REMAP_ADC1_ETRGINJ = 0x00001111,
GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210,
GPIO_REMAP_ADC1_ETRGREG = 0x00001211,
GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310,
GPIO_REMAP_ADC2_ETRGINJ = 0x00001311,
GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410,
GPIO_REMAP_ADC2_ETRGREG = 0x00001411,
GPIO_NO_REMAP_CAN2 = 0x00001610,
GPIO_REMAP_CAN2 = 0x00001611,
GPIO_NO_REMAP_SWJ = 0x00001870,
GPIO_REMAP_SWJ_NOJTRST = 0x00001871,
GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872,
GPIO_REMAP_SWJ_DISABLE = 0x00001874,
GPIO_NO_REMAP_EMMC_NADV = 0x00010A10,
GPIO_REMAP_EMMC_NADV = 0x00010A11,
}GPIO_REMAP_T;
/**
* @brief gpio port source define
*/
typedef enum
{
GPIO_PORT_SOURCE_A,
GPIO_PORT_SOURCE_B,
GPIO_PORT_SOURCE_C,
GPIO_PORT_SOURCE_D,
GPIO_PORT_SOURCE_E,
GPIO_PORT_SOURCE_F,
GPIO_PORT_SOURCE_G,
}GPIO_PORT_SOURCE_T;
/**
* @brief gpio pin source define
*/
typedef enum
{
GPIO_PIN_SOURCE_0,
GPIO_PIN_SOURCE_1,
GPIO_PIN_SOURCE_2,
GPIO_PIN_SOURCE_3,
GPIO_PIN_SOURCE_4,
GPIO_PIN_SOURCE_5,
GPIO_PIN_SOURCE_6,
GPIO_PIN_SOURCE_7,
GPIO_PIN_SOURCE_8,
GPIO_PIN_SOURCE_9,
GPIO_PIN_SOURCE_10,
GPIO_PIN_SOURCE_11,
GPIO_PIN_SOURCE_12,
GPIO_PIN_SOURCE_13,
GPIO_PIN_SOURCE_14,
GPIO_PIN_SOURCE_15,
}GPIO_PIN_SOURCE_T;
/**@} end of group GPIO_Enumerations*/
/** @addtogroup GPIO_Structure Data Structure
@{
*/
/**
* @brief GPIO Config structure definition
*/
typedef struct
{
uint16_t pin;
GPIO_SPEED_T speed;
GPIO_MODE_T mode;
}GPIO_Config_T;
/**@} end of group GPIO_Structure*/
/** @addtogroup GPIO_Fuctions Fuctions
@{
*/
/** Reset and common Configuration */
void GPIO_Reset(GPIO_T* port);
void GPIO_AFIOReset(void);
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig);
/** Read */
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
uint16_t GPIO_ReadInputPort(GPIO_T* port);
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
uint16_t GPIO_ReadOutputPort(GPIO_T* port);
/** Write */
void GPIO_SetBit(GPIO_T* port, uint16_t pin);
void GPIO_ResetBit(GPIO_T* port, uint16_t pin);
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal);
/** GPIO Configuration */
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
void GPIO_EnableEventOutput(void);
void GPIO_DisableEventOutput(void);
void GPIO_ConfigPinRemap(GPIO_REMAP_T remap);
void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
/**@} end of group GPIO_Fuctions*/
/**@} end of group GPIO_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_GPIO_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h
+348
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/*!
* @file apm32f10x_i2c.h
*
* @brief This file contains all the functions prototypes for the I2C firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_I2C_H
#define __APM32F10X_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup I2C_Driver I2C Driver
@{
*/
/** @addtogroup I2C_Enumerations Enumerations
@{
*/
/**
* @brief I2C Mode
*/
typedef enum
{
I2C_MODE_I2C = 0x0000,
I2C_MODE_SMBUUSDEVICE = 0x0002,
I2C_MODE_SMBUSHOST = 0x000A
} I2C_MODE_T;
/**
* @brief I2C duty cycle in fast mode
*/
typedef enum
{
I2C_DUTYCYCLE_16_9 = 0x4000,
I2C_DUTYCYCLE_2 = 0xBFFF
} I2C_DUTYCYCLE_T;
/**
* @brief I2C acknowledgement
*/
typedef enum
{
I2C_ACK_DISABLE,
I2C_ACK_ENABLE
} I2C_ACK_T;
/**
* @brief I2C acknowledged address
*/
typedef enum
{
I2C_ACK_ADDRESS_7BIT = 0x4000,
I2C_ACK_ADDRESS_10BIT = 0xC000
} I2C_ACK_ADDRESS_T;
/**
* @brief I2C interrupts definition
*/
typedef enum
{
I2C_INT_BUF = 0x0400,
I2C_INT_EVT = 0x0200,
I2C_INT_ERR = 0x0100
} I2C_INT_T;
/**
* @brief I2C transfer direction
*/
typedef enum
{
I2C_DIRECTION_TX,
I2C_DIRECTION_RX
} I2C_DIRECTION_T;
/**
* @brief I2C Register
*/
typedef enum
{
I2C_REGISTER_CTRL1,
I2C_REGISTER_CTRL2,
I2C_REGISTER_SADDR1,
I2C_REGISTER_SADDR2,
I2C_REGISTER_DATA,
I2C_REGISTER_STS1,
I2C_REGISTER_STS2,
I2C_REGISTER_CLKCTRL,
I2C_REGISTER_RISETMAX,
I2C_REGISTER_SWITCH
} I2C_REGISTER_T;
/**
* @brief I2C NCAK position
*/
typedef enum
{
I2C_NACK_POSITION_NEXT,
I2C_NACK_POSITION_CURRENT
} I2C_NACK_POSITION_T;
/**
* @brief I2C SMBus alert pin level
*/
typedef enum
{
I2C_SMBUSALER_LOW,
I2C_SMBUSALER_HIGH
} I2C_SMBUSALER_T;
/**
* @brief I2C PEC position
*/
typedef enum
{
I2C_PEC_POSITION_NEXT,
I2C_PEC_POSITION_CURRENT
} I2C_PEC_POSITION_T;
/**
* @brief I2C Events
*/
typedef enum
{
/** I2C Master Events */
/** Event 5: Communication start event */
I2C_EVENT_MASTER_MODE_SELECT = 0x00030001, //!< BUSBSYFLG, MSFLG and STARTFLG flag
/**
* Event 6: 7-bit Address Acknowledge
* in case of master receiver
*/
I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = 0x00070082, //!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */
I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = 0x00030002, //!< BUSBSYFLG, MSFLG and ADDRFLG flags */
/**
* Event 9: Master has sent the first byte
* in 10-bit address mode
*/
I2C_EVENT_MASTER_MODE_ADDRESS10 = 0x00030008, //!< BUSBSYFLG, MSFLG and ADDR10FLG flags */
/** Master RECEIVER mode */
/** Event 7 */
I2C_EVENT_MASTER_BYTE_RECEIVED = 0x00030040, //!< BUSBSYFLG, MSFLG and RXBNEFLG flags */
/** Master TRANSMITTER mode */
/** Event 8 */
I2C_EVENT_MASTER_BYTE_TRANSMITTING = 0x00070080, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */
/** Event 8_2 */
I2C_EVENT_MASTER_BYTE_TRANSMITTED = 0x00070084, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */
/** EV1 (all the events below are variants of EV1) */
/** 1, Case of One Single Address managed by the slave */
I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = 0x00020002, //!< BUSBSYFLG and ADDRFLG flags */
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = 0x00060082, //!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */
/** 2, Case of Dual address managed by the slave */
I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = 0x00820000, //!< DUALF and BUSBSYFLG flags */
I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = 0x00860080, //!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */
/** 3, Case of General Call enabled for the slave */
I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = 0x00120000, //!< GENCALL and BUSBSYFLG flags */
/** Slave RECEIVER mode */
/** EV2 */
I2C_EVENT_SLAVE_BYTE_RECEIVED = 0x00020040, //!< BUSBSYFLG and RXBNEFLG flags */
/** EV4 */
I2C_EVENT_SLAVE_STOP_DETECTED = 0x00000010, //!< STOPFLG flag */
/** Slave TRANSMITTER mode */
/** EV3 */
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = 0x00060084, //!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */
I2C_EVENT_SLAVE_BYTE_TRANSMITTING = 0x00060080, //!< TRFLG, BUSBSYFLG and TXBEFLG flags */
/** EV3_2 */
I2C_EVENT_SLAVE_ACK_FAILURE = 0x00000400, //!< AEFLG flag */
} I2C_EVENT_T;
/**
* @brief I2C flags
*/
typedef enum
{
/** STS2 register flags */
I2C_FLAG_DUALADDR,
I2C_FLAG_SMMHADDR,
I2C_FLAG_SMBDADDR,
I2C_FLAG_GENCALL,
I2C_FLAG_TR,
I2C_FLAG_BUSBSY,
I2C_FLAG_MS,
/** STS1 register flags */
I2C_FLAG_SMBALT,
I2C_FLAG_TTE,
I2C_FLAG_PECE,
I2C_FLAG_OVRUR,
I2C_FLAG_AE,
I2C_FLAG_AL,
I2C_FLAG_BERR,
I2C_FLAG_TXBE,
I2C_FLAG_RXBNE,
I2C_FLAG_STOP,
I2C_FLAG_ADDR10,
I2C_FLAG_BTC,
I2C_FLAG_ADDR,
I2C_FLAG_START,
} I2C_FLAG_T;
/**
* @brief I2C interrupt
*/
typedef enum
{
I2C_INT_FLAG_SMBALT = 0x01008000,
I2C_INT_FLAG_TTE = 0x01004000,
I2C_INT_FLAG_PECE = 0x01001000,
I2C_INT_FLAG_OVRUR = 0x01000800,
I2C_INT_FLAG_AE = 0x01000400,
I2C_INT_FLAG_AL = 0x01000200,
I2C_INT_FLAG_BERR = 0x01000100,
I2C_INT_FLAG_TXBE = 0x06000080,
I2C_INT_FLAG_RXBNE = 0x06000040,
I2C_INT_FLAG_STOP = 0x02000010,
I2C_INT_FLAG_ADDR10 = 0x02000008,
I2C_INT_FLAG_BTC = 0x02000004,
I2C_INT_FLAG_ADDR = 0x02000002,
I2C_INT_FLAG_START = 0x02000001,
} I2C_INT_FLAG_T;
/**@} end of group I2C_Enumerations*/
/** @addtogroup I2C_Structure Data Structure
@{
*/
/**
* @brief I2C Config structure definition
*/
typedef struct
{
uint32_t clockSpeed;
I2C_MODE_T mode;
I2C_DUTYCYCLE_T dutyCycle;
uint16_t ownAddress1;
I2C_ACK_T ack;
I2C_ACK_ADDRESS_T ackAddress;
} I2C_Config_T;
/**@} end of group I2C_Structure*/
/** @addtogroup I2C_Fuctions Fuctions
@{
*/
/** I2C reset and configuration */
void I2C_Reset(I2C_T* i2c);
void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig);
void I2C_ConfigStructInit(I2C_Config_T* i2cConfig);
void I2C_Enable(I2C_T* i2c);
void I2C_Disable(I2C_T* i2c);
void I2C_EnableGenerateStart(I2C_T* i2c);
void I2C_DisableGenerateStart(I2C_T* i2c);
void I2C_EnableGenerateStop(I2C_T* i2c);
void I2C_DisableGenerateStop(I2C_T* i2c);
void I2C_EnableAcknowledge(I2C_T* i2c);
void I2C_DisableAcknowledge(I2C_T* i2c);
void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address);
void I2C_EnableDualAddress(I2C_T* i2c);
void I2C_DisableDualAddress(I2C_T* i2c);
void I2C_EnableGeneralCall(I2C_T* i2c);
void I2C_DisableGeneralCall(I2C_T* i2c);
/** Transmit Configuration */
void I2C_TxData(I2C_T* i2c, uint8_t data);
uint8_t I2C_RxData(I2C_T* i2c);
void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction);
uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister);
void I2C_EnableSoftwareReset(I2C_T* i2c);
void I2C_DisableSoftwareReset(I2C_T* i2c);
void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition);
void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState);
void I2C_EnablePECTransmit(I2C_T* i2c);
void I2C_DisablePECTransmit(I2C_T* i2c);
void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition);
void I2C_EnablePEC(I2C_T* i2c);
void I2C_DisablePEC(I2C_T* i2c);
uint8_t I2C_ReadPEC(I2C_T* i2c);
void I2C_EnableARP(I2C_T* i2c);
void I2C_DisableARP(I2C_T* i2c);
void I2C_EnableStretchClock(I2C_T* i2c);
void I2C_DisableStretchClock(I2C_T* i2c);
void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle);
/** DMA */
void I2C_EnableDMA(I2C_T* i2c);
void I2C_DisableDMA(I2C_T* i2c);
void I2C_EnableDMALastTransfer(I2C_T* i2c);
void I2C_DisableDMALastTransfer(I2C_T* i2c);
/** Interrupts and flags */
void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt);
void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt);
uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent);
uint32_t I2C_ReadLastEvent(I2C_T* i2c);
uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag);
/**@} end of group I2C_Fuctions*/
/**@} end of group I2C_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_I2C_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h
+122
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/*!
* @file apm32f10x_iwdt.h
*
* @brief This file contains all the functions prototypes for the IWDT firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_IWDT_H
#define __APM32F10X_IWDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup IWDT_Driver IWDT Driver
@{
*/
/** @addtogroup IWDT_Enumerations Enumerations
@{
*/
/**
* @brief IWDT KEYWORD define
*/
typedef enum
{
IWDT_KEYWORD_RELOAD = 0xAAAA,
IWDT_KEYWORD_ENABLE = 0xCCCC
}IWDT_KEYWORD_T;
/**
* @brief IWDT Write Access define
*/
typedef enum
{
IWDT_WRITEACCESS_ENABLE = 0x5555,
IWDT_WRITEACCESS_DISABLE = 0x0000
}IWDT_WRITEACCESS_T;
/**
* @brief IWDT Divider
*/
typedef enum
{
IWDT_DIVIDER_4 = 0x00,
IWDT_DIVIDER_8 = 0x01,
IWDT_DIVIDER_16 = 0x02,
IWDT_DIVIDER_32 = 0x03,
IWDT_DIVIDER_64 = 0x04,
IWDT_DIVIDER_128 = 0x05,
IWDT_DIVIDER_256 = 0x06
}IWDT_DIVIDER_T;
/**
* @brief IWDT Flag
*/
typedef enum
{
IWDT_FLAG_PSCU = BIT0,
IWDT_FLAG_CNTU = BIT1
}IWDT_FLAG_T;
/**@} end of group IWDT_Enumerations*/
/** @addtogroup IWDT_Fuctions Fuctions
@{
*/
/** Enable IWDT */
void IWDT_Enable(void);
/** Refresh IWDT */
void IWDT_Refresh(void);
/** Counter reload */
void IWDT_ConfigReload(uint16_t reload);
/** Divider */
void IWDT_ConfigDivider(uint8_t div);
/** Write Access */
void IWDT_EnableWriteAccess(void);
void IWDT_DisableWriteAccess(void);
/** flag */
uint8_t IWDT_ReadStatusFlag(uint16_t flag);
/**@} end of group IWDT_Fuctions*/
/**@} end of group IWDT_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_IWDT_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h
+118
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/*!
* @file apm32f10x_misc.h
*
* @brief This file provides all the miscellaneous firmware functions.
* Include NVIC,SystemTick and Power management.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_MISC_H
#define __APM32F10X_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup MISC_Driver MISC Driver
@{
*/
/** @addtogroup MISC_Enumerations Enumerations
@{
*/
/**
* @brief NVIC Vect table
*/
typedef enum
{
NVIC_VECT_TAB_RAM = 0x20000000,
NVIC_VECT_TAB_FLASH = 0x08000000,
}NVIC_VECT_TAB_T;
/**
* @brief system low power mode
*/
typedef enum
{
NVIC_LOWPOWER_SEVONPEND = 0x10,
NVIC_LOWPOWER_SLEEPDEEP = 0x04,
NVIC_LOWPOWER_SLEEPONEXIT = 0x02
}NVIC_LOWPOWER_T;
/**
* @brief nvic priority group
*/
typedef enum
{
NVIC_PRIORITY_GROUP_0 = 0x700, //!< 0 bits for pre-emption priority,4 bits for subpriority
NVIC_PRIORITY_GROUP_1 = 0x600, //!< 1 bits for pre-emption priority,3 bits for subpriority
NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority
NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority
NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority
}NVIC_PRIORITY_GROUP_T;
/**
* @brief SysTick Clock source
*/
typedef enum
{
SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
SYSTICK_CLK_SOURCE_HCLK = 0x01
}SYSTICK_CLK_SOURCE_T;
/**@} end of group MISC_Enumerations*/
/** @addtogroup MISC_Fuctions Fuctions
@{
*/
/** NVIC */
void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup);
void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority);
void NVIC_DisableIRQRequest(IRQn_Type irq);
/** Vector Table */
void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset);
/** Power */
void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
/** Systick */
void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource);
/**@} end of group MISC_Fuctions*/
/**@} end of group MISC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_MISC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h
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/*!
* @file apm32f10x_pmu.h
*
* @brief This file contains all the functions prototypes for the PMU firmware library.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_PMU_H
#define __APM32F10X_PMU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup PMU_Driver PMU Driver
@{
*/
/** @addtogroup PMU_Enumerations Enumerations
@{
*/
/**
* @brief PMU PVD detection level
*/
typedef enum
{
PMU_PVD_LEVEL_2V2 = 0x00, //!< PVD detection level set to 2.2V
PMU_PVD_LEVEL_2V3 = 0x01, //!< PVD detection level set to 2.3V
PMU_PVD_LEVEL_2V4 = 0x02, //!< PVD detection level set to 2.4V
PMU_PVD_LEVEL_2V5 = 0x03, //!< PVD detection level set to 2.5V
PMU_PVD_LEVEL_2V6 = 0x04, //!< PVD detection level set to 2.6V
PMU_PVD_LEVEL_2V7 = 0x05, //!< PVD detection level set to 2.7V
PMU_PVD_LEVEL_2V8 = 0x06, //!< PVD detection level set to 2.8V
PMU_PVD_LEVEL_2V9 = 0x07, //!< PVD detection level set to 2.9V
} PMU_PVD_LEVEL_T;
/**
* @brief PMU Regulator state in STOP mode
*/
typedef enum
{
PMU_REGULATOR_ON = 0x00,
PMU_REGULATOR_LOWPOWER = 0x01
} PMU_REGULATOR_T;
/**
* @brief PMU STOP mode entry
*/
typedef enum
{
PMU_STOP_ENTRY_WFI = 0x01,
PMU_STOP_ENTRY_WFE = 0x02
} PMU_STOP_ENTRY_T;
/**
* @brief PMU Flag
*/
typedef enum
{
PMU_FLAG_WUE,
PMU_FLAG_SB,
PMU_FLAG_PVDO
} PMU_FLAG_T;
/**@} end of group PMU_Enumerations*/
/** @addtogroup PMU_Fuctions Fuctions
@{
*/
/** PMU Reset */
void PMU_Reset(void);
/** Configuration and Operation modes */
void PMU_EnableBackupAccess(void);
void PMU_DisableBackupAccess(void);
void PMU_EnablePVD(void);
void PMU_DisablePVD(void);
void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level);
void PMU_EnableWakeUpPin(void);
void PMU_DisableWakeUpPin(void);
void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry);
void PMU_EnterSTANDBYMode(void);
/** flags */
uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag);
void PMU_ClearStatusFlag(PMU_FLAG_T flag);
/**@} end of group PMU_Fuctions*/
/**@} end of group PMU_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_PMU_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h
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/*!
* @file apm32f10x_qspi.h
*
* @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_QSPI_H
#define __APM32F10X_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup QSPI_Driver QSPI Driver
@{
*/
/** @addtogroup QSPI_Enumerations Enumerations
@{
*/
/**
* @brief Frame format
*/
typedef enum
{
QSPI_FRF_STANDARD, //!< Standard mode
QSPI_FRF_DUAL, //!< Dual SPI
QSPI_FRF_QUAD //!< QUAD SPI
}QSPI_FRF_T;
/**
* @brief Transmission mode
*/
typedef enum
{
QSPI_TRANS_MODE_TX_RX, //!< TX and RX mode
QSPI_TRANS_MODE_TX, //!< TX mode only
QSPI_TRANS_MODE_RX, //!< RX mode only
QSPI_TRANS_MODE_EEPROM_READ //!< EEPROM read mode
}QSPI_TRANS_MODE_T;
/**
* @brief Clock polarity
*/
typedef enum
{
QSPI_CLKPOL_LOW,
QSPI_CLKPOL_HIGH
}QSPI_CLKPOL_T;
/**
* @brief Clock phase
*/
typedef enum
{
QSPI_CLKPHA_1EDGE,
QSPI_CLKPHA_2EDGE
}QSPI_CLKPHA_T;
/**
* @brief Data format size
*/
typedef enum
{
QSPI_DFS_4BIT = 3,
QSPI_DFS_5BIT,
QSPI_DFS_6BIT,
QSPI_DFS_7BIT,
QSPI_DFS_8BIT,
QSPI_DFS_9BIT,
QSPI_DFS_10BIT,
QSPI_DFS_11BIT,
QSPI_DFS_12BIT,
QSPI_DFS_13BIT,
QSPI_DFS_14BIT,
QSPI_DFS_15BIT,
QSPI_DFS_16BIT,
QSPI_DFS_17BIT,
QSPI_DFS_18BIT,
QSPI_DFS_19BIT,
QSPI_DFS_20BIT,
QSPI_DFS_21BIT,
QSPI_DFS_22BIT,
QSPI_DFS_23BIT,
QSPI_DFS_24BIT,
QSPI_DFS_25BIT,
QSPI_DFS_26BIT,
QSPI_DFS_27BIT,
QSPI_DFS_28BIT,
QSPI_DFS_29BIT,
QSPI_DFS_30BIT,
QSPI_DFS_31BIT,
QSPI_DFS_32BIT
}QSPI_DFS_T;
/**
* @brief QSPI flag
*/
typedef enum
{
QSPI_FLAG_BUSY = BIT0, //!< Busy flag
QSPI_FLAG_TFNF = BIT1, //!< TX FIFO not full flag
QSPI_FLAG_TFE = BIT2, //!< TX FIFO empty flag
QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag
QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag
QSPI_FLAG_DCE = BIT6 //!< Data collision error
}QSPI_FLAG_T;
/**
* @brief QSPI interrupt source
*/
typedef enum
{
QSPI_INT_TFE = BIT0, //!< TX FIFO empty interrupt
QSPI_INT_TFO = BIT1, //!< TX FIFO overflow interrupt
QSPI_INT_RFU = BIT2, //!< RX FIFO underflow interrupt
QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt
QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt
QSPI_INT_MST = BIT5 //!< Master interrupt
}QSPI_INT_T;
/**
* @brief QSPI interrupt flag
*/
typedef enum
{
QSPI_INT_FLAG_TFE = BIT0, //!< TX FIFO empty interrupt flag
QSPI_INT_FLAG_TFO = BIT1, //!< TX FIFO overflow interrupt flag
QSPI_INT_FLAG_RFU = BIT2, //!< RX FIFO underflow interrupt flag
QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag
QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag
QSPI_INT_FLAG_MST = BIT5 //!< Master interrupt flag
}QSPI_INT_FLAG_T;
/**
* @brief Reception sample edge
*/
typedef enum
{
QSPI_RSE_RISING,
QSPI_RSE_FALLING
}QSPI_RSE_T;
/**
* @brief Instruction length
*/
typedef enum
{
QSPI_INST_LEN_0,
QSPI_INST_LEN_4BIT,
QSPI_INST_LEN_8BIT,
QSPI_INST_LEN_16BIT
}QSPI_INST_LEN_T;
/**
* @brief QSPI address length
*/
typedef enum
{
QSPI_ADDR_LEN_0,
QSPI_ADDR_LEN_4BIT,
QSPI_ADDR_LEN_8BIT,
QSPI_ADDR_LEN_12BIT,
QSPI_ADDR_LEN_16BIT,
QSPI_ADDR_LEN_20BIT,
QSPI_ADDR_LEN_24BIT,
QSPI_ADDR_LEN_28BIT,
QSPI_ADDR_LEN_32BIT,
QSPI_ADDR_LEN_36BIT,
QSPI_ADDR_LEN_40BIT,
QSPI_ADDR_LEN_44BIT,
QSPI_ADDR_LEN_48BIT,
QSPI_ADDR_LEN_52BIT,
QSPI_ADDR_LEN_56BIT,
QSPI_ADDR_LEN_60BIT
}QSPI_ADDR_LEN_T;
/**
* @brief Instruction and address transmission mode
*/
typedef enum
{
QSPI_INST_ADDR_TYPE_STANDARD,
QSPI_INST_TYPE_STANDARD,
QSPI_INST_ADDR_TYPE_FRF
}QSPI_INST_ADDR_TYPE_T;
/**
* @brief Slave Select Toggle
*/
typedef enum
{
QSPI_SST_DISABLE,
QSPI_SST_ENABLE
}QSPI_SST_T;
/**@} end of group QSPI_Enumerations*/
/** @addtogroup QSPI_Macros Macros
@{
*/
/** CTRL1 register reset value */
#define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007)
/** CTRL2 register reset value */
#define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00)
/** SSIEN register reset value */
#define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00)
/** SLAEN register reset value */
#define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00)
/** BR register reset value */
#define QSPI_BR_RESET_VALUE ((uint32_t)0x00)
/** TFTL register reset value */
#define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00)
/** RFTL register reset value */
#define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00)
/** TFL register reset value */
#define QSPI_TFL_RESET_VALUE ((uint32_t)0x00)
/** RFL register reset value */
#define QSPI_RFL_RESET_VALUE ((uint32_t)0x00)
/** STS register reset value */
#define QSPI_STS_RESET_VALUE ((uint32_t)0x06)
/** INTEN register reset value */
#define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F)
/** RSD register reset value */
#define QSPI_RSD_RESET_VALUE ((uint32_t)0x00)
/** CTRL3 register reset value */
#define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200)
/** IOSW register reset value */
#define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00)
/**@} end of group QSPI_Macros*/
/** @addtogroup QSPI_Structure Data Structure
@{
*/
typedef struct
{
QSPI_SST_T selectSlaveToggle; //!< Slave Select Toggle
QSPI_FRF_T frameFormat; //!< Frame format
uint16_t clockDiv; //!< Clock divider
QSPI_CLKPOL_T clockPolarity; //!< Clock polarity
QSPI_CLKPHA_T clockPhase; //!< Clock phase
QSPI_DFS_T dataFrameSize; //!< Data frame size
}QSPI_Config_T;
/**@} end of group QSPI_Structure*/
/** @addtogroup QSPI_Fuctions Fuctions
@{
*/
/** Reset */
void QSPI_Reset(void);
/** Configuration */
void QSPI_Config(QSPI_Config_T *qspiConfig);
void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig);
/** Data frame size, frame number, frame format */
void QSPI_ConfigFrameNum(uint16_t num);
void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs);
void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat);
/** Disable or Enable */
void QSPI_Enable(void);
void QSPI_Disable(void);
/** TX and RX FIFO */
uint8_t QSPI_ReadTxFifoDataNum(void);
uint8_t QSPI_ReadRxFifoDataNum(void);
void QSPI_ConfigRxFifoThreshold(uint8_t threshold);
void QSPI_ConfigTxFifoThreshold(uint8_t threshold);
void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold);
/** RX Sample */
void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse);
void QSPI_ConfigRxSampleDelay(uint8_t delay);
/** Clock stretch */
void QSPI_EnableClockStretch(void);
void QSPI_DisableClockStretch(void);
/** Instruction, address, Wait cycle */
void QSPI_ConfigInstLen(QSPI_INST_LEN_T len);
void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len);
void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type);
void QSPI_ConfigWaitCycle(uint8_t cycle);
/** IO */
void QSPI_OpenIO(void);
void QSPI_CloseIO(void);
/** Transmission mode */
void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode);
/** Rx and Tx data */
uint32_t QSPI_RxData(void);
void QSPI_TxData(uint32_t data);
/** Slave */
void QSPI_EnableSlave(void);
void QSPI_DisableSlave(void);
/** Interrupt */
void QSPI_EnableInterrupt(uint32_t interrupt);
void QSPI_DisableInterrupt(uint32_t interrupt);
/** Flag */
uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag);
void QSPI_ClearStatusFlag(void);
uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag);
void QSPI_ClearIntFlag(uint32_t flag);
/**@} end of group QSPI_Fuctions*/
/**@} end of group QSPI_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_QSPI_H_ */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h
+379
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/*!
* @file apm32f10x_rcm.h
*
* @brief This file contains all the functions prototypes for the RCM firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_RCM_H
#define __APM32F10X_RCM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup RCM_Driver RCM Driver
@{
*/
/** @addtogroup RCM_Enumerations Enumerations
@{
*/
/**
* @brief HSE state
*/
typedef enum
{
RCM_HSE_CLOSE,
RCM_HSE_OPEN,
RCM_HSE_BYPASS
} RCM_HSE_T;
/**
* @brief PLL multiplication factor
*/
typedef enum
{
RCM_PLLMF_2,
RCM_PLLMF_3,
RCM_PLLMF_4,
RCM_PLLMF_5,
RCM_PLLMF_6,
RCM_PLLMF_7,
RCM_PLLMF_8,
RCM_PLLMF_9,
RCM_PLLMF_10,
RCM_PLLMF_11,
RCM_PLLMF_12,
RCM_PLLMF_13,
RCM_PLLMF_14,
RCM_PLLMF_15,
RCM_PLLMF_16
} RCM_PLLMF_T;
/**
* @brief System clock select
*/
typedef enum
{
RCM_SYSCLK_SEL_HSI,
RCM_SYSCLK_SEL_HSE,
RCM_SYSCLK_SEL_PLL
} RCM_SYSCLK_SEL_T;
/**
* @brief AHB divider Number
*/
typedef enum
{
RCM_AHB_DIV_1 = 7,
RCM_AHB_DIV_2,
RCM_AHB_DIV_4,
RCM_AHB_DIV_8,
RCM_AHB_DIV_16,
RCM_AHB_DIV_64,
RCM_AHB_DIV_128,
RCM_AHB_DIV_256,
RCM_AHB_DIV_512
} RCM_AHB_DIV_T;
/**
* @brief APB divider Number
*/
typedef enum
{
RCM_APB_DIV_1 = 3,
RCM_APB_DIV_2,
RCM_APB_DIV_4,
RCM_APB_DIV_8,
RCM_APB_DIV_16
} RCM_APB_DIV_T;
/**
* @brief USB divider Number
*/
typedef enum
{
RCM_USB_DIV_1_5,
RCM_USB_DIV_1,
RCM_USB_DIV_2,
RCM_USB_DIV_2_5 //!< (Only for High-density devices for APM32F103xx)
} RCM_USB_DIV_T;
/**
* @brief FPU divider Number
*/
typedef enum
{
RCM_FPU_DIV_1,
RCM_FPU_DIV_2
} RCM_FPU_DIV_T;
/**
* @brief ADC divider Number
*/
typedef enum
{
RCM_PCLK2_DIV_2,
RCM_PCLK2_DIV_4,
RCM_PCLK2_DIV_6,
RCM_PCLK2_DIV_8
} RCM_PCLK2_DIV_T;
/**
* @brief LSE State
*/
typedef enum
{
RCM_LSE_CLOSE,
RCM_LSE_OPEN,
RCM_LSE_BYPASS
} RCM_LSE_T;
/**
* @brief RTC clock select
*/
typedef enum
{
RCM_RTCCLK_LSE = 1,
RCM_RTCCLK_LSI,
RCM_RTCCLK_HSE_DIV_128
} RCM_RTCCLK_T;
/**
* @brief Clock output control
*/
typedef enum
{
RCM_MCOCLK_NO_CLOCK = 3,
RCM_MCOCLK_SYSCLK,
RCM_MCOCLK_HSI,
RCM_MCOCLK_HSE,
RCM_MCOCLK_PLLCLK_DIV_2
} RCM_MCOCLK_T;
/**
* @brief PLL entry clock select
*/
typedef enum
{
RCM_PLLSEL_HSI_DIV_2 = 0,
RCM_PLLSEL_HSE = 1,
RCM_PLLSEL_HSE_DIV2 = 3,
} RCM_PLLSEL_T;
/**
* @brief RCM Interrupt Source
*/
typedef enum
{
RCM_INT_LSIRDY = BIT0, //!< LSI ready interrupt
RCM_INT_LSERDY = BIT1, //!< LSE ready interrupt
RCM_INT_HSIRDY = BIT2, //!< HSI ready interrupt
RCM_INT_HSERDY = BIT3, //!< HSE ready interrupt
RCM_INT_PLLRDY = BIT4, //!< PLL ready interrupt
RCM_INT_CSS = BIT7 //!< Clock security system interrupt
} RCM_INT_T;
/**
* @brief AHB peripheral
*/
typedef enum
{
RCM_AHB_PERIPH_DMA1 = BIT0,
RCM_AHB_PERIPH_DMA2 = BIT1,
RCM_AHB_PERIPH_SRAM = BIT2,
RCM_AHB_PERIPH_FPU = BIT3,
RCM_AHB_PERIPH_FMC = BIT4,
RCM_AHB_PERIPH_QSPI = BIT5,
RCM_AHB_PERIPH_CRC = BIT6,
RCM_AHB_PERIPH_EMMC = BIT8,
RCM_AHB_PERIPH_SDIO = BIT10
} RCM_AHB_PERIPH_T;
/**
* @brief AHB2 peripheral
*/
typedef enum
{
RCM_APB2_PERIPH_AFIO = BIT0,
RCM_APB2_PERIPH_GPIOA = BIT2,
RCM_APB2_PERIPH_GPIOB = BIT3,
RCM_APB2_PERIPH_GPIOC = BIT4,
RCM_APB2_PERIPH_GPIOD = BIT5,
RCM_APB2_PERIPH_GPIOE = BIT6,
RCM_APB2_PERIPH_GPIOF = BIT7,
RCM_APB2_PERIPH_GPIOG = BIT8,
RCM_APB2_PERIPH_ADC1 = BIT9,
RCM_APB2_PERIPH_ADC2 = BIT10,
RCM_APB2_PERIPH_TMR1 = BIT11,
RCM_APB2_PERIPH_SPI1 = BIT12,
RCM_APB2_PERIPH_TMR8 = BIT13,
RCM_APB2_PERIPH_USART1 = BIT14,
RCM_APB2_PERIPH_ADC3 = BIT15
} RCM_APB2_PERIPH_T;
/**
* @brief AHB1 peripheral
*/
typedef enum
{
RCM_APB1_PERIPH_TMR2 = BIT0,
RCM_APB1_PERIPH_TMR3 = BIT1,
RCM_APB1_PERIPH_TMR4 = BIT2,
RCM_APB1_PERIPH_TMR5 = BIT3,
RCM_APB1_PERIPH_TMR6 = BIT4,
RCM_APB1_PERIPH_TMR7 = BIT5,
RCM_APB1_PERIPH_WWDT = BIT11,
RCM_APB1_PERIPH_SPI2 = BIT14,
RCM_APB1_PERIPH_SPI3 = BIT15,
RCM_APB1_PERIPH_USART2 = BIT17,
RCM_APB1_PERIPH_USART3 = BIT18,
RCM_APB1_PERIPH_UART4 = BIT19,
RCM_APB1_PERIPH_UART5 = BIT20,
RCM_APB1_PERIPH_I2C1 = BIT21,
RCM_APB1_PERIPH_I2C2 = BIT22,
RCM_APB1_PERIPH_USB = BIT23,
RCM_APB1_PERIPH_CAN1 = BIT25,
RCM_APB1_PERIPH_CAN2 = BIT26,
RCM_APB1_PERIPH_BAKR = BIT27,
RCM_APB1_PERIPH_PMU = BIT28,
RCM_APB1_PERIPH_DAC = BIT29
} RCM_APB1_PERIPH_T;
/**
* @brief RCM FLAG define
*/
typedef enum
{
RCM_FLAG_HSIRDY = 0x001, //!< HSI Ready Flag
RCM_FLAG_HSERDY = 0x011, //!< HSE Ready Flag
RCM_FLAG_PLLRDY = 0x019, //!< PLL Ready Flag
RCM_FLAG_LSERDY = 0x101, //!< LSE Ready Flag
RCM_FLAG_LSIRDY = 0x201, //!< LSI Ready Flag
RCM_FLAG_PINRST = 0x21A, //!< PIN reset flag
RCM_FLAG_PORRST = 0x21B, //!< POR/PDR reset flag
RCM_FLAG_SWRST = 0x21C, //!< Software reset flag
RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag
RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag
RCM_FLAG_LPRRST = 0x21F //!< Low-power reset flag
} RCM_FLAG_T;
/**@} end of group RCM_Enumerations*/
/** @addtogroup RCM_Fuctions Fuctions
@{
*/
/** Function description */
/** RCM Reset */
void RCM_Reset(void);
/** HSE clock */
void RCM_ConfigHSE(RCM_HSE_T state);
uint8_t RCM_WaitHSEReady(void);
/** HSI clock */
void RCM_ConfigHSITrim(uint8_t HSITrim);
void RCM_EnableHSI(void);
void RCM_DisableHSI(void);
/** LSE and LSI clock */
void RCM_ConfigLSE(RCM_LSE_T state);
void RCM_EnableLSI(void);
void RCM_DisableLSI(void);
/** PLL clock */
void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf);
void RCM_EnablePLL(void);
void RCM_DisablePLL(void);
/** Clock Security System */
void RCM_EnableCSS(void);
void RCM_DisableCSS(void);
void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock);
void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect);
RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void);
/** Config clock prescaler of AHB, APB1, APB2, USB and ADC */
void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv);
void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div);
void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div);
void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv);
void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv);
void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv);
/** RTC clock */
void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect);
void RCM_EnableRTCCLK(void);
void RCM_DisableRTCCLK(void);
/** Reads the clock frequency */
uint32_t RCM_ReadSYSCLKFreq(void);
uint32_t RCM_ReadHCLKFreq(void);
void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
uint32_t RCM_ReadADCCLKFreq(void);
/** Enable or disable Periph Clock */
void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph);
void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph);
void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph);
void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph);
void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph);
void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph);
/** Enable or disable Periph Reset */
void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph);
void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph);
void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph);
void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph);
/** Backup domain reset */
void RCM_EnableBackupReset(void);
void RCM_DisableBackupReset(void);
/** Interrupts and flags */
void RCM_EnableInterrupt(uint32_t interrupt);
void RCM_DisableInterrupt(uint32_t interrupt);
uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag);
void RCM_ClearStatusFlag(void);
uint8_t RCM_ReadIntFlag(RCM_INT_T flag);
void RCM_ClearIntFlag(uint32_t flag);
/**@} end of group RCM_Fuctions*/
/**@} end of group RCM_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_RCM_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h
+99
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/*!
* @file apm32f10x_rtc.h
*
* @brief This file contains all the functions prototypes for the RTC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_RTC_H
#define __APM32F10X_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup RTC_Driver RTC Driver
@{
*/
/** @addtogroup RTC_Enumerations Enumerations
@{
*/
typedef enum
{
RTC_FLAG_OC = 0x0020, //!< RTC Operation Complete flag
RTC_FLAG_RSYNC = 0x0008, //!< Registers Synchronized flag
RTC_FLAG_OVR = 0x0004, //!< Overflow flag
RTC_FLAG_ALR = 0x0002, //!< Alarm flag
RTC_FLAG_SEC = 0x0001 //!< Second flag
} RTC_FLAG_T;
typedef enum
{
RTC_INT_OVR = 0x0004, //!< Overflow interrupt
RTC_INT_ALR = 0x0002, //!< Alarm interrupt
RTC_INT_SEC = 0x0001 //!< Second interrupt
} RTC_INT_T;
/**@} end of group RTC_Enumerations*/
/** @addtogroup RTC_Fuctions Fuctions
@{
*/
/** Operation modes */
void RTC_EnableConfigMode(void);
void RTC_DisableConfigMode(void);
/** Configuration */
uint32_t RTC_ReadCounter(void);
void RTC_ConfigCounter(uint32_t value);
void RTC_ConfigPrescaler(uint32_t value);
void RTC_ConfigAlarm(uint32_t value);
uint32_t RTC_ReadDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchor(void);
/** Interrupts and flags */
void RTC_EnableInterrupt(uint16_t interrupt);
void RTC_DisableInterrupt(uint16_t interrupt);
uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag);
void RTC_ClearStatusFlag(uint16_t flag);
uint8_t RTC_ReadIntFlag(RTC_INT_T flag);
void RTC_ClearIntFlag(uint16_t flag);
/**@} end of group RTC_Fuctions*/
/**@} end of group RTC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_RTC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h
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/*!
* @file apm32f10x_sci2c.h
*
* @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_SCI2C_H
#define __APM32F10X_SCI2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SCI2C_Driver SCI2C Driver
@{
*/
/** @addtogroup SCI2C_Enumerations Enumerations
@{
*/
/**
* @brief SCI2C speed enumeration
*/
typedef enum
{
SCI2C_SPEED_STANDARD = 1,
SCI2C_SPEED_FAST,
SCI2C_SPEED_HIGH
}SCI2C_SPEED_T;
/**
* @brief Address mode
*/
typedef enum
{
SCI2C_ADDR_MODE_7BIT,
SCI2C_ADDR_MODE_10BIT
}SCI2C_ADDR_MODE_T;
/**
* @brief SCI2C mode enumeration
*/
typedef enum
{
SCI2C_MODE_MASTER,
SCI2C_MODE_SLAVE
}SCI2C_MODE_T;
/**
* @brief Restart enable or disable
*/
typedef enum
{
SCI2C_RESTART_DISABLE,
SCI2C_RESTART_ENABLE
}SCI2C_RESTART_T;
/**
* @brief Enable or disable generate stop condition
*/
typedef enum
{
SCI2C_STOP_DISABLE,
SCI2C_STOP_ENABLE
}SCI2C_STOP_T;
/**
* @brief Data direction
*/
typedef enum
{
SCI2C_DATA_DIR_WRITE,
SCI2C_DATA_DIR_READ,
}SCI2C_DATA_DIR_T;
/**
* @brief SCI2C interrupt
*/
typedef enum
{
SCI2C_INT_RFU = BIT0, //!< Rx FIFO underflow interrupt
SCI2C_INT_RFO = BIT1, //!< Rx FIFO onverflow interrupt
SCI2C_INT_RFF = BIT2, //!< Rx FIFO full interrupt
SCI2C_INT_TFO = BIT3, //!< Tx FIFO onverflow interrupt
SCI2C_INT_TFE = BIT4, //!< Tx FIFO empty interrupt
SCI2C_INT_RR = BIT5, //!< Read request interrupt
SCI2C_INT_TA = BIT6, //!< Tx abort interrupt
SCI2C_INT_RD = BIT7, //!< Read done interrupt
SCI2C_INT_ACT = BIT8, //!< Activity interrupt
SCI2C_INT_STPD = BIT9, //!< Stop detect interrupt
SCI2C_INT_STAD = BIT10, //!< Start detect interrupt
SCI2C_INT_GC = BIT11, //!< Gernal call interrupt
SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt
SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt
SCI2C_INT_ALL = BIT15 //!< All interrupt
}SCI2C_INT_T;
/**
* @brief Flag enumeration
*/
typedef enum
{
SCI2C_FLAG_ACT = BIT0, //!< Activity flag
SCI2C_FLAG_TFNF = BIT1, //!< Tx FIFO not full flag
SCI2C_FLAG_TFE = BIT2, //!< Tx FIFO empty flag
SCI2C_FLAG_RFNE = BIT3, //!< Rx FIFO not empty flag
SCI2C_FLAG_RFF = BIT4, //!< Rx FIFO full flag
SCI2C_FLAG_MA = BIT5, //!< Master activity flag
SCI2C_FLAG_SA = BIT6, //!< Slave activity flag
SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag
SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag
SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag
}SCI2C_FLAG_T;
/**
* @brief Tx abort source
*/
typedef enum
{
SCI2C_TAS_AD7NA = BIT0, //!< 7 bit address mode NACK
SCI2C_TAS_AD10FBNA = BIT1, //!< 10 bit address mode first byte NACK
SCI2C_TAS_AD10SBNA = BIT2, //!< 10 bit address mode second byte NACK
SCI2C_TAS_TDNA = BIT3, //!< Tx data NACK
SCI2C_TAS_GCNA = BIT4, //!< Gernal call NACK
SCI2C_TAS_GCR = BIT5, //!< Gernal call read
SCI2C_TAS_HSAD = BIT6, //!< High speed ack detected
SCI2C_TAS_SNR = BIT7, //!< Start byte no restart
SCI2C_TAS_RNR10B = BIT8, //!< Read 10bit address mode when restart disable
SCI2C_TAS_MSTDIS = BIT9, //!< Master disable
SCI2C_TAS_ARBLOST = BIT10, //!< Arbitration lost
SCI2C_TAS_LFTF = BIT11, //!< Slave flush tx FIFO
SCI2C_TAS_SAL = BIT12, //!< Slave arbitration lost
SCI2C_TAS_SRI = BIT13, //!< Slave read done
SCI2C_TAS_USRARB = BIT14, //!< User abort
SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter
}SCI2C_TAS_T;
/**
* @brief DMA Enable
*/
typedef enum
{
SCI2C_DMA_RX = BIT0,
SCI2C_DMA_TX = BIT1,
}SCI2C_DMA_T;
/**@} end of group SCI2C_Enumerations*/
/** @addtogroup SCI2C_Macros Macros
@{
*/
/** Macros description */
#define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E)
#define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055)
#define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55)
#define SCI2C_HSMC_RESET_VALUE ((uint32_t)0x07)
#define SCI2C_DATA_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_SSCHC_RESET_VALUE ((uint32_t)0x190)
#define SCI2C_SSCLC_RESET_VALUE ((uint32_t)0x1D6)
#define SCI2C_FSCHC_RESET_VALUE ((uint32_t)0x3C)
#define SCI2C_FSCLC_RESET_VALUE ((uint32_t)0x82)
#define SCI2C_HSCHC_RESET_VALUE ((uint32_t)0x06)
#define SCI2C_HSCLC_RESET_VALUE ((uint32_t)0x10)
#define SCI2C_INTEN_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_RFT_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_TFT_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_CTRL2_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_TFL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_RFL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_SDAHOLD_RESET_VALUE ((uint32_t)0x01)
#define SCI2C_SDNO_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_DMACTRL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_DTDL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_DRDL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_SDADLY_RESET_VALUE ((uint32_t)0x64)
#define SCI2C_GCA_RESET_VALUE ((uint32_t)0x01)
#define SCI2C_LSSSL_RESET_VALUE ((uint32_t)0x05)
#define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01)
#define SCI2C_FIFO_DEPTH (0X08)
/**@} end of group SCI2C_Macros*/
/** @addtogroup SCI2C_Structure Data Structure
@{
*/
/**
* @brief Struct description
*/
typedef struct
{
uint16_t slaveAddr; //!< Slave address.
SCI2C_MODE_T mode; //!< Specifies mode, master mode or slave mode
SCI2C_SPEED_T speed; //!< Specifies speed. Standard speed, fast speed or high speed.
uint16_t clkLowPeriod; //!< SCL high period
uint16_t clkHighPeriod; //!< SCL low period
uint8_t rxFifoThreshold; //!< Rx FIFO threshold
uint8_t txFifoThreshold; //!< Tx FIFO threshold
SCI2C_RESTART_T restart; //!< Enable or disable restart
SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode.
}SCI2C_Config_T;
/**@} end of group SCI2C_Structure*/
/** @addtogroup SCI2C_Fuctions Fuctions
@{
*/
/** Reset */
void SCI2C_Reset(SCI2C_T *i2c);
/** Configuration */
void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig);
void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig);
/** Stop detect */
void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c);
void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c);
void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c);
void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c);
/** Restart */
void SCI2C_EnableRestart(SCI2C_T *i2c);
void SCI2C_DisableRestart(SCI2C_T *i2c);
/** Speed */
void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed);
/** Address */
void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
/** Master mode and slave mode */
void SCI2C_EnableMasterMode(SCI2C_T *i2c);
void SCI2C_DisableMasterMode(SCI2C_T *i2c);
void SCI2C_EnableSlaveMode(SCI2C_T *i2c);
void SCI2C_DisableSlaveMode(SCI2C_T *i2c);
void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code);
/** Data */
void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir);
void SCI2C_TxData(SCI2C_T *i2c, uint8_t data);
uint8_t SCI2C_RxData(SCI2C_T *i2c);
void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data);
/** Rx and Tx FIFO */
uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c);
uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c);
void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
/** I2C Enable, disable, abort, block */
void SCI2C_Enable(SCI2C_T *i2c);
void SCI2C_Disable(SCI2C_T *i2c);
void SCI2C_Abort(SCI2C_T *i2c);
void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable);
/** SCL and SDA */
void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod);
void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold);
void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay);
/** ACK and NACK */
void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable);
void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable);
/** Abort */
uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c);
/** DMA */
void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt);
void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt);
/** Spike suppression limit */
void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit);
/** Ingerrupt and flag */
uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag);
void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
/**@} end of group SCI2C_Fuctions*/
/**@} end of group SCI2C_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_SCI2C_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h
+432
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/*!
* @file apm32f10x_sdio.h
*
* @brief This file contains all the functions prototypes for the SDIO firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_SDIO_H
#define __APM32F10X_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SDIO_Driver SDIO Driver
@{
*/
/** @addtogroup SDIO_Enumerations Enumerations
@{
*/
/**
* @brief SDIO clock edge
*/
typedef enum
{
SDIO_CLOCK_EDGE_RISING = 0x00000000,
SDIO_CLOCK_EDGE_FALLING = 0x00002000
}SDIO_CLOCK_EDGE_T;
/**
* @brief SDIO clock bypass
*/
typedef enum
{
SDIO_CLOCK_BYPASS_DISABLE = 0x00000000,
SDIO_CLOCK_BYPASS_ENABLE = 0x00000400
}SDIO_CLOCK_BYPASS_T;
/**
* @brief SDIO clock power save
*/
typedef enum
{
SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000,
SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200
}SDIO_CLOCK_POWER_SAVE_T;
/**
* @brief SDIO bus wide
*/
typedef enum
{
SDIO_BUS_WIDE_1B = 0x00000000,
SDIO_BUS_WIDE_4B = 0x00000800,
SDIO_BUS_WIDE_8B = 0x00001000
}SDIO_BUS_WIDE_T;
/**
* @brief SDIO hardware flow control
*/
typedef enum
{
SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000,
SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000
}SDIO_HARDWARE_FLOW_CONTROL_T;
/**
* @brief SDIO power state
*/
typedef enum
{
SDIO_POWER_STATE_OFF = 0x00000000,
SDIO_POWER_STATE_ON = 0x00000003
}SDIO_POWER_STATE_T;
/**
* @brief SDIO interrupt sources
*/
typedef enum
{
SDIO_INT_COMRESP = 0x00000001,
SDIO_INT_DBDR = 0x00000002,
SDIO_INT_CMDRESTO = 0x00000004,
SDIO_INT_DATATO = 0x00000008,
SDIO_INT_TXUDRER = 0x00000010,
SDIO_INT_RXOVRER = 0x00000020,
SDIO_INT_CMDRES = 0x00000040,
SDIO_INT_CMDSENT = 0x00000080,
SDIO_INT_DATAEND = 0x00000100,
SDIO_INT_SBE = 0x00000200,
SDIO_INT_DBCP = 0x00000400,
SDIO_INT_CMDACT = 0x00000800,
SDIO_INT_TXACT = 0x00001000,
SDIO_INT_RXACT = 0x00002000,
SDIO_INT_TXFHF = 0x00004000,
SDIO_INT_RXFHF = 0x00008000,
SDIO_INT_TXFF = 0x00010000,
SDIO_INT_RXFF = 0x00020000,
SDIO_INT_TXFE = 0x00040000,
SDIO_INT_RXFE = 0x00080000,
SDIO_INT_TXDA = 0x00100000,
SDIO_INT_RXDA = 0x00200000,
SDIO_INT_SDIOINT = 0x00400000,
SDIO_INT_ATAEND = 0x00800000
}SDIO_INT_T;
/**
* @brief SDIO response
*/
typedef enum
{
SDIO_RESPONSE_NO = 0x00000000,
SDIO_RESPONSE_SHORT = 0x00000040,
SDIO_RESPONSE_LONG = 0x000000C0
}SDIO_RESPONSE_T;
/**
* @brief SDIO wait interrupt state
*/
typedef enum
{
SDIO_WAIT_NO = 0x00000000,
SDIO_WAIT_INT = 0x00000100,
SDIO_WAIT_PEND = 0x00000200
}SDIO_WAIT_T;
/**
* @brief SDIO CPSM state
*/
typedef enum
{
SDIO_CPSM_DISABLE = 0x00000000,
SDIO_CPSM_ENABLE = 0x00000400
}SDIO_CPSM_T;
/**
* @brief SDIO response registers
*/
typedef enum
{
SDIO_RES1 = 0x00000000,
SDIO_RES2 = 0x00000004,
SDIO_RES3 = 0x00000008,
SDIO_RES4 = 0x0000000C
}SDIO_RES_T;
/**
* @brief SDIO data block size
*/
typedef enum
{
SDIO_DATA_BLOCKSIZE_1B = 0x00000000,
SDIO_DATA_BLOCKSIZE_2B = 0x00000010,
SDIO_DATA_BLOCKSIZE_4B = 0x00000020,
SDIO_DATA_BLOCKSIZE_8B = 0x00000030,
SDIO_DATA_BLOCKSIZE_16B = 0x00000040,
SDIO_DATA_BLOCKSIZE_32B = 0x00000050,
SDIO_DATA_BLOCKSIZE_64B = 0x00000060,
SDIO_DATA_BLOCKSIZE_128B = 0x00000070,
SDIO_DATA_BLOCKSIZE_256B = 0x00000080,
SDIO_DATA_BLOCKSIZE_512B = 0x00000090,
SDIO_DATA_BLOCKSIZE_1024B = 0x000000A0,
SDIO_DATA_BLOCKSIZE_2048B = 0x000000B0,
SDIO_DATA_BLOCKSIZE_496B = 0x000000C0,
SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0,
SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0
}SDIO_DATA_BLOCKSIZE_T;
/**
* @brief SDIO transfer direction
*/
typedef enum
{
SDIO_TRANSFER_DIR_TO_CARD = 0x00000000,
SDIO_TRANSFER_DIR_TO_SDIO = 0x00000002
}SDIO_TRANSFER_DIR_T;
/**
* @brief SDIO transfer type
*/
typedef enum
{
SDIO_TRANSFER_MODE_BLOCK = 0x00000000,
SDIO_TRANSFER_MODE_STREAM = 0x00000004
}SDIO_TRANSFER_MODE_T;
/**
* @brief SDIO DPSM state
*/
typedef enum
{
SDIO_DPSM_DISABLE = 0x00000000,
SDIO_DPSM_ENABLE = 0x00000001
}SDIO_DPSM_T;
/**
* @brief SDIO flag
*/
typedef enum
{
SDIO_FLAG_COMRESP = 0x00000001,
SDIO_FLAG_DBDR = 0x00000002,
SDIO_FLAG_CMDRESTO = 0x00000004,
SDIO_FLAG_DATATO = 0x00000008,
SDIO_FLAG_TXUDRER = 0x00000010,
SDIO_FLAG_RXOVRER = 0x00000020,
SDIO_FLAG_CMDRES = 0x00000040,
SDIO_FLAG_CMDSENT = 0x00000080,
SDIO_FLAG_DATAEND = 0x00000100,
SDIO_FLAG_SBE = 0x00000200,
SDIO_FLAG_DBCP = 0x00000400,
SDIO_FLAG_CMDACT = 0x00000800,
SDIO_FLAG_TXACT = 0x00001000,
SDIO_FLAG_RXACT = 0x00002000,
SDIO_FLAG_TXFHF = 0x00004000,
SDIO_FLAG_RXFHF = 0x00008000,
SDIO_FLAG_TXFF = 0x00010000,
SDIO_FLAG_RXFF = 0x00020000,
SDIO_FLAG_TXFE = 0x00040000,
SDIO_FLAG_RXFE = 0x00080000,
SDIO_FLAG_TXDA = 0x00100000,
SDIO_FLAG_RXDA = 0x00200000,
SDIO_FLAG_SDIOINT = 0x00400000,
SDIO_FLAG_ATAEND = 0x00800000
}SDIO_FLAG_T;
/**
* @brief SDIO read wait mode
*/
typedef enum
{
SDIO_READ_WAIT_MODE_CLK = 0x00000001,
SDIO_READ_WAIT_MODE_DATA2 = 0x00000000
}SDIO_READ_WAIT_MODE_T;
/**@} end of group SDIO_Enumerations*/
/** @addtogroup SDIO_Macros Macros
@{
*/
/** ------------ SDIO registers bit address in the alias region ----------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/** --- CLKCTRL Register ---*/
/** Alias word address of CLKEN bit */
#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04)
#define CLKEN_BitNumber 0x08
#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4))
/** --- CMD Register ---*/
/** Alias word address of SDIOSC bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define SDIOSC_BitNumber 0x0B
#define CMD_SDIOSC_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4))
/** Alias word address of CMDCPEN bit */
#define CMDCPEN_BitNumber 0x0C
#define CMD_CMDCPEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4))
/** Alias word address of INTEN bit */
#define INTEN_BitNumber 0x0D
#define CMD_INTEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4))
/** Alias word address of ATACMD bit */
#define ATACMD_BitNumber 0x0E
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
/** --- DCTRL Register ---*/
/** Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define DMAEN_BitNumber 0x03
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
/** Alias word address of RWSTR bit */
#define RWSTR_BitNumber 0x08
#define DCTRL_RWSTR_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4))
/** Alias word address of RWSTOP bit */
#define RWSTOP_BitNumber 0x09
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
/** Alias word address of RDWAIT bit */
#define RDWAIT_BitNumber 0x0A
#define DCTRL_RDWAIT_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4))
/** Alias word address of SDIOF bit */
#define SDIOF_BitNumber 0x0B
#define DCTRL_SDIOF_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4))
/**@} end of group SDIO_Macros*/
/** @addtogroup SDIO_Structure Data Structure
@{
*/
/**
* @brief SDIO Config structure definition
*/
typedef struct
{
SDIO_CLOCK_EDGE_T clockEdge;
SDIO_CLOCK_BYPASS_T clockBypass;
SDIO_CLOCK_POWER_SAVE_T clockPowerSave;
SDIO_BUS_WIDE_T busWide;
SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl;
uint8_t clockDiv;
}SDIO_Config_T;
/**
* @brief SDIO CMD Config structure definition
*/
typedef struct
{
uint32_t argument;
uint32_t cmdIndex;
SDIO_RESPONSE_T response;
SDIO_WAIT_T wait;
SDIO_CPSM_T CPSM;
}SDIO_CmdConfig_T;
/**
* @brief SDIO Data Config structure definition
*/
typedef struct
{
uint32_t dataTimeOut;
uint32_t dataLength;
SDIO_DATA_BLOCKSIZE_T dataBlockSize;
SDIO_TRANSFER_DIR_T transferDir;
SDIO_TRANSFER_MODE_T transferMode;
SDIO_DPSM_T DPSM;
}SDIO_DataConfig_T;
/**@} end of group SDIO_Structure*/
/** @addtogroup SDIO_Fuctions Fuctions
@{
*/
/** SDIO reset and configuration */
void SDIO_Reset(void);
void SDIO_Config(SDIO_Config_T* sdioConfig);
void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig);
void SDIO_EnableClock(void);
void SDIO_DisableClock(void);
void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState);
uint32_t SDIO_ReadPowerState(void);
/** DMA */
void SDIO_EnableDMA(void);
void SDIO_DisableDMA(void);
/** Command */
void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig);
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdconfig);
uint8_t SDIO_ReadCommandResponse(void);
uint32_t SDIO_ReadResponse(SDIO_RES_T res);
/** SDIO data configuration */
void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig);
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig);
uint32_t SDIO_ReadDataCounter(void);
void SDIO_WriteData(uint32_t data);
uint32_t SDIO_ReadData(void);
uint32_t SDIO_ReadFIFOCount(void);
/** SDIO mode */
void SDIO_EnableStartReadWait(void);
void SDIO_DisableStartReadWait(void);
void SDIO_EnableStopReadWait(void);
void SDIO_DisableStopReadWait(void);
void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode);
void SDIO_EnableSDIO(void);
void SDIO_DisableSDIO(void);
void SDIO_EnableTxSDIOSuspend(void);
void SDIO_DisableTxSDIOSuspend(void);
void SDIO_EnableCommandCompletion(void);
void SDIO_DisableCommandCompletion(void);
void SDIO_EnableCEATAInterrupt(void);
void SDIO_DisableCEATAInterrupt(void);
void SDIO_EnableTxCEATA(void);
void SDIO_DisableTxCEATA(void);
/** Interrupt and flags */
void SDIO_EnableInterrupt(uint32_t interrupt);
void SDIO_DisableInterrupt(uint32_t interrupt);
uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag);
void SDIO_ClearStatusFlag(uint32_t flag);
uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag);
void SDIO_ClearIntFlag(uint32_t flag);
/**@} end of group SDIO_Fuctions*/
/**@} end of group SDIO_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_SDIO_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h
+333
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@@ -0,0 +1,333 @@
/*!
* @file apm32f10x_spi.h
*
* @brief This file contains all the functions prototypes for the SPI firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_SPI_H
#define __APM32F10X_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SPI_Driver SPI Driver
@{
*/
/** @addtogroup SPI_Enumerations Enumerations
@{
*/
/**
* @brief SPI data direction mode
*/
typedef enum
{
SPI_DIRECTION_2LINES_FULLDUPLEX = 0x0000,
SPI_DIRECTION_2LINES_RXONLY = 0x0400,
SPI_DIRECTION_1LINE_RX = 0x8000,
SPI_DIRECTION_1LINE_TX = 0xC000
}SPI_DIRECTION_T;
/**
* @brief SPI mode
*/
typedef enum
{
SPI_MODE_MASTER = 0x0104,
SPI_MODE_SLAVE = 0x0000
}SPI_MODE_T;
/**
* @brief SPI Data length
*/
typedef enum
{
SPI_DATA_LENGTH_16B = 0x0800,
SPI_DATA_LENGTH_8B = 0x0000
}SPI_DATA_LENGTH_T;
/**
* @brief SPI Clock Polarity
*/
typedef enum
{
SPI_CLKPOL_LOW = 0x0000,
SPI_CLKPOL_HIGH = 0x0002
}SPI_CLKPOL_T;
/**
* @brief SPI Clock Phase
*/
typedef enum
{
SPI_CLKPHA_1EDGE = 0x0000,
SPI_CLKPHA_2EDGE = 0x0001
}SPI_CLKPHA_T;
/**
* @brief SPI Slave Select management
*/
typedef enum
{
SPI_NSS_SOFT = 0x0200,
SPI_NSS_HARD = 0x0000
}SPI_NSS_T;
/**
* @brief SPI BaudRate Prescaler
*/
typedef enum
{
SPI_BAUDRATE_DIV_2 = 0x0000,
SPI_BAUDRATE_DIV_4 = 0x0008,
SPI_BAUDRATE_DIV_8 = 0x0010,
SPI_BAUDRATE_DIV_16 = 0x0018,
SPI_BAUDRATE_DIV_32 = 0x0020,
SPI_BAUDRATE_DIV_64 = 0x0028,
SPI_BAUDRATE_DIV_128 = 0x0030,
SPI_BAUDRATE_DIV_256 = 0x0038,
}SPI_BAUDRATE_DIV_T;
/**
* @brief SPI MSB LSB transmission
*/
typedef enum
{
SPI_FIRSTBIT_MSB = 0x0000,
SPI_FIRSTBIT_LSB = 0x0080
}SPI_FIRSTBIT_T;
/**
* @brief I2S Mode
*/
typedef enum
{
I2S_MODE_SLAVE_TX = 0x0000,
I2S_MODE_SLAVE_RX = 0x0100,
I2S_MODE_MASTER_TX = 0x0200,
I2S_MODE_MASTER_RX = 0x0300
}I2S_MODE_T;
/**
* @brief I2S Standard
*/
typedef enum
{
I2S_STANDARD_PHILLIPS = 0x0000,
I2S_STANDARD_MSB = 0x0010,
I2S_STANDARD_LSB = 0x0020,
I2S_STANDARD_PCMSHORT = 0x0030,
I2S_STANDARD_PCMLONG = 0x00B0
}I2S_STANDARD_T;
/**
* @brief I2S data length
*/
typedef enum
{
I2S_DATA_LENGHT_16B = 0x0000,
I2S_DATA_LENGHT_16BEX = 0x0001,
I2S_DATA_LENGHT_24B = 0x0003,
I2S_DATA_LENGHT_32B = 0x0005,
} I2S_DATA_LENGTH_T;
/**
* @brief I2S_MCLK_Output
*/
typedef enum
{
I2S_MCLK_OUTPUT_DISABLE = 0x0000,
I2S_MCLK_OUTPUT_ENABLE = 0x0200,
}I2S_MCLK_OUTPUT_T;
/**
* @brief I2S Audio divider
*/
typedef enum
{
I2S_AUDIO_DIV_192K = 192000,
I2S_AUDIO_DIV_96K = 96000,
I2S_AUDIO_DIV_48K = 48000,
I2S_AUDIO_DIV_44K = 44100,
I2S_AUDIO_DIV_32K = 32000,
I2S_AUDIO_DIV_22K = 22050,
I2S_AUDIO_DIV_16K = 16000,
I2S_AUDIO_DIV_11K = 11025,
I2S_AUDIO_DIV_8K = 8000,
I2S_AUDIO_DIV_DEFAULT = 2
}I2S_AUDIO_DIV_T;
/**
* @brief I2S Clock Polarity
*/
typedef enum
{
I2S_CLKPOL_LOW = 0x0000,
I2S_CLKPOL_HIGH = 0x0008
}I2S_CLKPOL_T;
/**
* @brief SPI Direction select
*/
typedef enum
{
SPI_DIRECTION_RX = 0xBFFF,
SPI_DIRECTION_TX = 0x4000
}SPI_DIRECTION_SELECT_T;
/**
* @brief SPI interrupts definition
*/
typedef enum
{
SPI_I2S_INT_TXBE = 0x8002,
SPI_I2S_INT_RXBNE = 0x4001,
SPI_I2S_INT_ERR = 0x2000,
SPI_I2S_INT_OVR = 0x2040,
SPI_INT_CRCE = 0x2010,
SPI_INT_ME = 0x2020,
I2S_INT_UDR = 0x2008
}SPI_I2S_INT_T;
/**
* @brief SPI flags definition
*/
typedef enum
{
SPI_FLAG_RXBNE = 0x0001,
SPI_FLAG_TXBE = 0x0002,
I2S_FLAG_SCHDIR = 0x0004,
I2S_FLAG_UDR = 0x0008,
SPI_FLAG_CRCE = 0x0010,
SPI_FLAG_ME = 0x0020,
SPI_FLAG_OVR = 0x0040,
SPI_FLAG_BSY = 0x0080
}SPI_FLAG_T;
/**
* @brief SPI I2S DMA requests
*/
typedef enum
{
SPI_I2S_DMA_REQ_TX = 0x0002,
SPI_I2S_DMA_REQ_RX = 0x0001
}SPI_I2S_DMA_REQ_T;
/**@} end of group SPI_Enumerations*/
/** @addtogroup SPI_Structure Data Structure
@{
*/
/**
* @brief SPI Config structure definition
*/
typedef struct
{
SPI_MODE_T mode;
SPI_DATA_LENGTH_T length;
SPI_CLKPHA_T phase;
SPI_CLKPOL_T polarity;
SPI_NSS_T nss;
SPI_FIRSTBIT_T firstBit;
SPI_DIRECTION_T direction;
SPI_BAUDRATE_DIV_T baudrateDiv;
uint16_t crcPolynomial;
}SPI_Config_T;
/**
* @brief I2S Config structure definition
*/
typedef struct
{
I2S_MODE_T mode;
I2S_STANDARD_T standard;
I2S_DATA_LENGTH_T length;
I2S_MCLK_OUTPUT_T MCLKOutput;
I2S_AUDIO_DIV_T audioDiv;
I2S_CLKPOL_T polarity;
}I2S_Config_T;
/**@} end of group SPI_Structure*/
/** @addtogroup SPI_Fuctions Fuctions
@{
*/
/** Reset and Configuration */
void SPI_I2S_Reset(SPI_T* spi);
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig);
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig);
void SPI_ConfigStructInit(SPI_Config_T* spiConfig);
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig);
void SPI_Enable(SPI_T* spi);
void SPI_Disable(SPI_T* spi);
void I2S_Enable(SPI_T* spi);
void I2S_Disable(SPI_T* spi);
void SPI_I2S_TxData(SPI_T* spi, uint16_t data);
uint16_t SPI_I2S_RxData(SPI_T* spi);
void SPI_SetSoftwareNSS(SPI_T* spi);
void SPI_ResetSoftwareNSS(SPI_T* spi);
void SPI_EnableSSOutput(SPI_T* spi);
void SPI_DisableSSOutput(SPI_T* spi);
void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length);
/** DMA */
void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
/** CRC */
void SPI_TxCRC(SPI_T* spi);
void SPI_EnableCRC(SPI_T* spi);
void SPI_DisableCRC(SPI_T* spi);
uint16_t SPI_ReadTxCRC(SPI_T* spi);
uint16_t SPI_ReadRxCRC(SPI_T* spi);
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi);
void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction);
/** Interrupts and flag */
void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
/**@} end of group SPI_Fuctions*/
/**@} end of group SPI_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_SPI_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h
+673
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@@ -0,0 +1,673 @@
/*!
* @file apm32f10x_tmr.h
*
* @brief This file contains all the functions prototypes for the TMR firmware library.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_TMR_H
#define __APM32F10X_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup TMR_Driver TMR Driver
@{
*/
/** @addtogroup TMR_Enumerations Enumerations
@{
*/
/**
* @brief TMR Counter Mode
*/
typedef enum
{
TMR_COUNTER_MODE_UP = 0x0000,
TMR_COUNTER_MODE_DOWN = 0x0010,
TMR_COUNTER_MODE_CENTERALIGNED1 = 0x0020,
TMR_COUNTER_MODE_CENTERALIGNED2 = 0x0040,
TMR_COUNTER_MODE_CENTERALIGNED3 = 0x0060
} TMR_COUNTER_MODE_T;
/**
* @brief TMR Clock division
*/
typedef enum
{
TMR_CLOCK_DIV_1,
TMR_CLOCK_DIV_2,
TMR_CLOCK_DIV_4
} TMR_CLOCK_DIV_T;
/**
* @brief TMR Output Compare and PWM modes
*/
typedef enum
{
TMR_OC_MODE_TMRING = 0x00,
TMR_OC_MODE_ACTIVE = 0x01,
TMR_OC_MODE_INACTIVE = 0x02,
TMR_OC_MODE_TOGGEL = 0x03,
TMR_OC_MODE_LOWLEVEL = 0x04,
TMR_OC_MODE_HIGHLEVEL = 0x05,
TMR_OC_MODE_PWM1 = 0x06,
TMR_OC_MODE_PWM2 = 0x07
} TMR_OC_MODE_T;
/**
* @brief TMR Output Compare state
*/
typedef enum
{
TMR_OC_STATE_DISABLE,
TMR_OC_STATE_ENABLE
} TMR_OC_STATE_T;
/**
* @brief TMR Output Compare N state
*/
typedef enum
{
TMR_OC_NSTATE_DISABLE,
TMR_OC_NSTATE_ENABLE
} TMR_OC_NSTATE_T;
/**
* @brief TMR Output Compare Polarity
*/
typedef enum
{
TMR_OC_POLARITY_HIGH,
TMR_OC_POLARITY_LOW
} TMR_OC_POLARITY_T;
/**
* @brief TMR Output Compare N Polarity
*/
typedef enum
{
TMR_OC_NPOLARITY_HIGH,
TMR_OC_NPOLARITY_LOW
} TMR_OC_NPOLARITY_T;
/**
* @brief TMR Output Compare Idle State
*/
typedef enum
{
TMR_OC_IDLE_STATE_RESET,
TMR_OC_IDLE_STATE_SET
} TMR_OC_IDLE_STATE_T;
/**
* @brief TMR Output Compare N Idle State
*/
typedef enum
{
TMR_OC_NIDLE_STATE_RESET,
TMR_OC_NIDLE_STATE_SET
} TMR_OC_NIDLE_STATE_T;
/**
* @brief TMR Input Capture Init structure definition
*/
typedef enum
{
TMR_CHANNEL_1 = 0x0000,
TMR_CHANNEL_2 = 0x0004,
TMR_CHANNEL_3 = 0x0008,
TMR_CHANNEL_4 = 0x000C
} TMR_CHANNEL_T;
/**
* @brief TMR Input Capture Polarity
*/
typedef enum
{
TMR_IC_POLARITY_RISING = 0x00,
TMR_IC_POLARITY_FALLING = 0x02,
TMR_IC_POLARITY_BOTHEDGE = 0x0A
} TMR_IC_POLARITY_T;
/**
* @brief TMR Input Capture Selection
*/
typedef enum
{
TMR_IC_SELECTION_DIRECT_TI = 0x01,
TMR_IC_SELECTION_INDIRECT_TI = 0x02,
TMR_IC_SELECTION_TRC = 0x03
} TMR_IC_SELECTION_T;
/**
* @brief TMR Input Capture Prescaler
*/
typedef enum
{
TMR_IC_PSC_1,
TMR_IC_PSC_2,
TMR_IC_PSC_4,
TMR_IC_PSC_8
} TMR_IC_PSC_T;
/**
* @brief TMR Specifies the Off-State selection used in Run mode
*/
typedef enum
{
TMR_RMOS_STATE_DISABLE,
TMR_RMOS_STATE_ENABLE
} TMR_RMOS_STATE_T;
/**
* @brief TMR Closed state configuration in idle mode
*/
typedef enum
{
TMR_IMOS_STATE_DISABLE,
TMR_IMOS_STATE_ENABLE
} TMR_IMOS_STATE_T;
/**
* @brief TMR Protect mode configuration values
*/
typedef enum
{
TMR_LOCK_LEVEL_OFF,
TMR_LOCK_LEVEL_1,
TMR_LOCK_LEVEL_2,
TMR_LOCK_LEVEL_3
} TMR_LOCK_LEVEL_T;
/**
* @brief TMR BRK state
*/
typedef enum
{
TMR_BRK_STATE_DISABLE,
TMR_BRK_STATE_ENABLE
} TMR_BRK_STATE_T;
/**
* @brief TMR Specifies the Break Input pin polarity.
*/
typedef enum
{
TMR_BRK_POLARITY_LOW,
TMR_BRK_POLARITY_HIGH
} TMR_BRK_POLARITY_T;
/**
* @brief TMR Specifies the Break Input pin polarity.
*/
typedef enum
{
TMR_AUTOMATIC_OUTPUT_DISABLE,
TMR_AUTOMATIC_OUTPUT_ENABLE
} TMR_AUTOMATIC_OUTPUT_T;
/**
* @brief TMR_interrupt_sources
*/
typedef enum
{
TMR_INT_UPDATE = 0x0001,
TMR_INT_CC1 = 0x0002,
TMR_INT_CC2 = 0x0004,
TMR_INT_CC3 = 0x0008,
TMR_INT_CC4 = 0x0010,
TMR_INT_COM = 0x0020,
TMR_INT_TRG = 0x0040,
TMR_INT_BRK = 0x0080
} TMR_INT_T;
/**
* @brief TMR event sources
*/
typedef enum
{
TMR_EVENT_UPDATE = 0x001,
TMR_EVENT_CC1 = 0x002,
TMR_EVENT_CC2 = 0x004,
TMR_EVENT_CC3 = 0x008,
TMR_EVENT_CC4 = 0x010,
TMR_EVENT_COM = 0x020,
TMR_EVENT_TRG = 0x040,
TMR_EVENT_BRK = 0x080
} TMR_EVENT_T;
/**
* @brief TMR DMA Base Address
*/
typedef enum
{
TMR_DMA_BASE_CTRL1 = 0x0000,
TMR_DMA_BASE_CTRL2 = 0x0001,
TMR_DMA_BASE_SMCTRL = 0x0002,
TMR_DMA_BASE_DIEN = 0x0003,
TMR_DMA_BASE_STS = 0x0004,
TMR_DMA_BASE_CEG = 0x0005,
TMR_DMA_BASE_CCM1 = 0x0006,
TMR_DMA_BASE_CCM2 = 0x0007,
TMR_DMA_BASE_CCEN = 0x0008,
TMR_DMA_BASE_CNT = 0x0009,
TMR_DMA_BASE_PSC = 0x000A,
TMR_DMA_BASE_AUTORLD = 0x000B,
TMR_DMA_BASE_REPCNT = 0x000C,
TMR_DMA_BASE_CC1 = 0x000D,
TMR_DMA_BASE_CC2 = 0x000E,
TMR_DMA_BASE_CC3 = 0x000F,
TMR_DMA_BASE_CC4 = 0x0010,
TMR_DMA_BASE_BDT = 0x0011,
TMR_DMA_BASE_DCTRL = 0x0012
} TMR_DMA_BASE_T;
/**
* @brief TMR DMA Burst Length
*/
typedef enum
{
TMR_DMA_BURSTLENGTH_1TRANSFER = 0x0000,
TMR_DMA_BURSTLENGTH_2TRANSFERS = 0x0100,
TMR_DMA_BURSTLENGTH_3TRANSFERS = 0x0200,
TMR_DMA_BURSTLENGTH_4TRANSFERS = 0x0300,
TMR_DMA_BURSTLENGTH_5TRANSFERS = 0x0400,
TMR_DMA_BURSTLENGTH_6TRANSFERS = 0x0500,
TMR_DMA_BURSTLENGTH_7TRANSFERS = 0x0600,
TMR_DMA_BURSTLENGTH_8TRANSFERS = 0x0700,
TMR_DMA_BURSTLENGTH_9TRANSFERS = 0x0800,
TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900,
TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00,
TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00,
TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00,
TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00,
TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00,
TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00,
TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000,
TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100,
} TMR_DMA_BURSTLENGTH_T;
/**
* @brief TMR DMA Soueces
*/
typedef enum
{
TMR_DMA_SOURCE_UPDATE = 0x0100,
TMR_DMA_SOURCE_CC1 = 0x0200,
TMR_DMA_SOURCE_CC2 = 0x0400,
TMR_DMA_SOURCE_CC3 = 0x0800,
TMR_DMA_SOURCE_CC4 = 0x1000,
TMR_DMA_SOURCE_COM = 0x2000,
TMR_DMA_SOURCE_TRG = 0x4000
} TMR_DMA_SOURCE_T;
/**
* @brief TMR Internal Trigger Selection
*/
typedef enum
{
TMR_TRIGGER_SOURCE_ITR0 = 0x00,
TMR_TRIGGER_SOURCE_ITR1 = 0x01,
TMR_TRIGGER_SOURCE_ITR2 = 0x02,
TMR_TRIGGER_SOURCE_ITR3 = 0x03,
TMR_TRIGGER_SOURCE_TI1F_ED = 0x04,
TMR_TRIGGER_SOURCE_TI1FP1 = 0x05,
TMR_TRIGGER_SOURCE_TI2FP2 = 0x06,
TMR_TRIGGER_SOURCE_ETRF = 0x07
} TMR_TRIGGER_SOURCE_T;
/**
* @brief TMR The external Trigger Prescaler.
*/
typedef enum
{
TMR_EXTTRG_PSC_OFF = 0x00,
TMR_EXTTRG_PSC_DIV2 = 0x01,
TMR_EXTTRG_PSC_DIV4 = 0x02,
TMR_EXTTRG_PSC_DIV8 = 0x03
} TMR_EXTTRG_PSC_T;
/**
* @brief TMR External Trigger Polarity
*/
typedef enum
{
TMR_EXTTGR_POL_NONINVERTED,
TMR_EXTTRG_POL_INVERTED
} TMR_EXTTRG_POL_T;
/**
* @brief TMR Prescaler Reload Mode
*/
typedef enum
{
TMR_PSC_RELOAD_UPDATE,
TMR_PSC_RELOAD_IMMEDIATE
} TMR_PSC_RELOAD_T;
/**
* @brief TMR Encoder Mode
*/
typedef enum
{
TMR_ENCODER_MODE_TI1 = 0x01,
TMR_ENCODER_MODE_TI2 = 0x02,
TMR_ENCODER_MODE_TI12 = 0x03
} TMR_ENCODER_MODE_T;
/**
* @brief TMR Forced Action
*/
typedef enum
{
TMR_FORCED_ACTION_INACTIVE = 0x04,
TMR_FORCED_ACTION_ACTIVE = 0x05
} TMR_FORCED_ACTION_T;
/**
* @brief TMR Output Compare Preload State
*/
typedef enum
{
TMR_OC_PRELOAD_DISABLE,
TMR_OC_PRELOAD_ENABLE
} TMR_OC_PRELOAD_T;
/**
* @brief TMR Output Compare Preload State
*/
typedef enum
{
TMR_OC_FAST_DISABLE,
TMR_OC_FAST_ENABLE
} TMR_OC_FAST_T;
/**
* @brief TMR Output Compare Preload State
*/
typedef enum
{
TMR_OC_CLEAR_DISABLE,
TMR_OC_CLEAR_ENABLE
} TMR_OC_CLEAR_T;
/**
* @brief TMR UpdateSource
*/
typedef enum
{
TMR_UPDATE_SOURCE_GLOBAL,
TMR_UPDATE_SOURCE_REGULAR,
} TMR_UPDATE_SOURCE_T;
/**
* @brief TMR Single Pulse Mode
*/
typedef enum
{
TMR_SPM_REPETITIVE,
TMR_SPM_SINGLE,
} TMR_SPM_T;
/**
* @brief TMR Trigger Output Source
*/
typedef enum
{
TMR_TRGO_SOURCE_RESET,
TMR_TRGO_SOURCE_ENABLE,
TMR_TRGO_SOURCE_UPDATE,
TMR_TRGO_SOURCE_OC1,
TMR_TRGO_SOURCE_OC1REF,
TMR_TRGO_SOURCE_OC2REF,
TMR_TRGO_SOURCE_OC3REF,
TMR_TRGO_SOURCE_OC4REF
} TMR_TRGO_SOURCE_T;
/**
* @brief TMR Slave Mode
*/
typedef enum
{
TMR_SLAVE_MODE_RESET = 0x04,
TMR_SLAVE_MODE_GATED = 0x05,
TMR_SLAVE_MODE_TRIGGER = 0x06,
TMR_SLAVE_MODE_EXTERNAL1 = 0x07
} TMR_SLAVE_MODE_T;
/**
* @brief TMR Flag
*/
typedef enum
{
TMR_FLAG_UPDATE = 0x0001,
TMR_FLAG_CC1 = 0x0002,
TMR_FLAG_CC2 = 0x0004,
TMR_FLAG_CC3 = 0x0008,
TMR_FLAG_CC4 = 0x0010,
TMR_FLAG_COM = 0x0020,
TMR_FLAG_TRG = 0x0040,
TMR_FLAG_BRK = 0x0080,
TMR_FLAG_CC1RC = 0x0200,
TMR_FLAG_CC2RC = 0x0400,
TMR_FLAG_CC3RC = 0x0800,
TMR_FLAG_CC4RC = 0x1000
} TMR_FLAG_T;
/**@} end of group TMR_Enumerations*/
/** @addtogroup TMR_Structure Data Structure
@{
*/
/**
* @brief TMR Config struct definition
*/
typedef struct
{
TMR_COUNTER_MODE_T countMode;
TMR_CLOCK_DIV_T clockDivision;
uint16_t period; //!< This must between 0x0000 and 0xFFFF
uint16_t division; //!< This must between 0x0000 and 0xFFFF
uint8_t repetitionCounter; //!< This must between 0x00 and 0xFF, only for TMR1 and TMR8.
} TMR_BaseConfig_T; ;
/**
* @brief TMR Config struct definition
*/
typedef struct
{
TMR_OC_MODE_T mode;
TMR_OC_STATE_T outputState;
TMR_OC_NSTATE_T outputNState;
TMR_OC_POLARITY_T polarity;
TMR_OC_NPOLARITY_T nPolarity;
TMR_OC_IDLE_STATE_T idleState;
TMR_OC_NIDLE_STATE_T nIdleState;
uint16_t pulse; //!< This must between 0x0000 and 0xFFFF
} TMR_OCConfig_T;
/**
* @brief TMR BDT structure definition
*/
typedef struct
{
TMR_RMOS_STATE_T RMOS;
TMR_IMOS_STATE_T IMOS;
TMR_LOCK_LEVEL_T lockLevel;
uint16_t deadTime;
TMR_BRK_STATE_T BRKState;
TMR_BRK_POLARITY_T BRKPolarity;
TMR_AUTOMATIC_OUTPUT_T automaticOutput;
} TMR_BDTConfig_T;
/**
* @brief TMR Input Capture Config struct definition
*/
typedef struct
{
TMR_CHANNEL_T channel;
TMR_IC_POLARITY_T polarity;
TMR_IC_SELECTION_T selection;
TMR_IC_PSC_T prescaler;
uint16_t filter; //!< This must between 0x00 and 0x0F
} TMR_ICConfig_T;
/**@} end of group TMR_Structure*/
/** @addtogroup TMR_Fuctions Fuctions
@{
*/
/** Reset and Configuration */
void TMR_Reset(TMR_T* tmr);
void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig);
void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig);
void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig);
void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig);
void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
void TMR_Enable(TMR_T* tmr);
void TMR_Disable(TMR_T* tmr);
/** PWM Configuration */
void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig);
void TMR_EnablePWMOutputs(TMR_T* tmr);
void TMR_DisablePWMOutputs(TMR_T* tmr);
/** DMA */
void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
/** Configuration */
void TMR_ConfigInternalClock(TMR_T* tmr);
void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
TMR_IC_POLARITY_T IC2Polarity);
void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_EnableAutoReload(TMR_T* tmr);
void TMR_DisableAutoReload(TMR_T* tmr);
void TMR_EnableSelectCOM(TMR_T* tmr);
void TMR_DisableSelectCOM(TMR_T* tmr);
void TMR_EnableCCDMA(TMR_T* tmr);
void TMR_DisableCCDMA(TMR_T* tmr);
void TMR_EnableCCPreload(TMR_T* tmr);
void TMR_DisableCCPreload(TMR_T* tmr);
void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
void TMR_EnableUpdate(TMR_T* tmr);
void TMR_DisableUpdate(TMR_T* tmr);
void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
void TMR_EnableHallSensor(TMR_T* tmr);
void TMR_DisableHallSensor(TMR_T* tmr);
void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
void TMR_EnableMasterSlaveMode(TMR_T* tmr);
void TMR_DisableMasterSlaveMode(TMR_T* tmr);
void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
uint16_t TMR_ReadCaputer1(TMR_T* tmr);
uint16_t TMR_ReadCaputer2(TMR_T* tmr);
uint16_t TMR_ReadCaputer3(TMR_T* tmr);
uint16_t TMR_ReadCaputer4(TMR_T* tmr);
uint16_t TMR_ReadCounter(TMR_T* tmr);
uint16_t TMR_ReadPrescaler(TMR_T* tmr);
/** Interrupts and Event */
void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources);
/** flags */
uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag);
/**@} end of group TMR_Fuctions*/
/**@} end of group TMR_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_TMR_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h
+310
View File
@@ -0,0 +1,310 @@
/*!
* @file apm32f10x_usart.h
*
* @brief This file contains all the functions prototypes for the USART firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_USART_H
#define __APM32F10X_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup USART_Driver USART Driver
@{
*/
/** @addtogroup USART_Enumerations Enumerations
@{
*/
/**
* @brief USART Word Length define
*/
typedef enum
{
USART_WORD_LEN_8B = 0,
USART_WORD_LEN_9B = BIT12
} USART_WORD_LEN_T;
/**
* @brief USART Stop bits define
*/
typedef enum
{
USART_STOP_BIT_1 = 0,
USART_STOP_BIT_0_5 = BIT12,
USART_STOP_BIT_2 = BIT13,
USART_STOP_BIT_1_5 = BIT12 | BIT13
} USART_STOP_BIT_T;
/**
* @brief USART Parity define
*/
typedef enum
{
USART_PARITY_NONE = 0,
USART_PARITY_EVEN = BIT10,
USART_PARITY_ODD = BIT10 | BIT9
} USART_PARITY_T;
/**
* @brief USART mode define
*/
typedef enum
{
USART_MODE_RX = BIT2,
USART_MODE_TX = BIT3,
USART_MODE_TX_RX = BIT2 | BIT3
} USART_MODE_T;
/**
* @brief USART hardware flow control define
*/
typedef enum
{
USART_HARDWARE_FLOW_NONE = 0,
USART_HARDWARE_FLOW_RTS = BIT8,
USART_HARDWARE_FLOW_CTS = BIT9,
USART_HARDWARE_FLOW_RTS_CTS = BIT8 | BIT9
} USART_HARDWARE_FLOW_T;
/**
* @brief USART Clock enable
*/
typedef enum
{
USART_CLKEN_DISABLE,
USART_CLKEN_ENABLE
} USART_CLKEN_T;
/**
* @brief USART Clock polarity define
*/
typedef enum
{
USART_CLKPOL_LOW,
USART_CLKPOL_HIGH
} USART_CLKPOL_T;
/**
* @brief USART Clock phase define
*/
typedef enum
{
USART_CLKPHA_1EDGE,
USART_CLKPHA_2EDGE
} USART_CLKPHA_T;
/**
* @brief USART Last bit clock pulse enable
*/
typedef enum
{
USART_LBCP_DISABLE,
USART_LBCP_ENABLE,
} USART_LBCP_T;
/**
* @brief USART Interrupt Source
*/
typedef enum
{
USART_INT_PE = 0x0010100,
USART_INT_TXBE = 0x7010080,
USART_INT_TXC = 0x6010040,
USART_INT_RXBNE = 0x5010020,
USART_INT_IDLE = 0x4010010,
USART_INT_LBD = 0x8020040,
USART_INT_CTS = 0x9040400,
USART_INT_ERR = 0x0040001,
USART_INT_OVRE = 0x3040001,
USART_INT_NE = 0x2040001,
USART_INT_FE = 0x1040001
} USART_INT_T;
/**
* @brief USART DMA enable
*/
typedef enum
{
USART_DMA_TX = BIT7,
USART_DMA_RX = BIT6,
USART_DMA_TX_RX = BIT6 | BIT7
} USART_DMA_T;
/**
* @brief USART Wakeup method
*/
typedef enum
{
USART_WAKEUP_IDLE_LINE,
USART_WAKEUP_ADDRESS_MARK
} USART_WAKEUP_T;
/**
* @brief USART LIN break detection length
*/
typedef enum
{
USART_LBDL_10B,
USART_LBDL_11B
} USART_LBDL_T;
/**
* @brief USART IrDA low-power
*/
typedef enum
{
USART_IRDALP_NORMAL,
USART_IRDALP_LOWPOWER
} USART_IRDALP_T;
/**
* @brief USART flag define
*/
typedef enum
{
USART_FLAG_CTS = 0x0200,
USART_FLAG_LBD = 0x0100,
USART_FLAG_TXBE = 0x0080,
USART_FLAG_TXC = 0x0040,
USART_FLAG_RXBNE = 0x0020,
USART_FLAG_IDLE = 0x0010,
USART_FLAG_OVRE = 0x0008,
USART_FLAG_NE = 0x0004,
USART_FLAG_FE = 0x0002,
USART_FLAG_PE = 0x0001
} USART_FLAG_T;
/**@} end of group USART_Enumerations*/
/** @addtogroup USART_Structure Data Structure
@{
*/
/**
* @brief USART Config struct definition
*/
typedef struct
{
uint32_t baudRate; //!< Specifies the baud rate
USART_WORD_LEN_T wordLength; //!< Specifies the word length
USART_STOP_BIT_T stopBits; //!< Specifies the stop bits
USART_PARITY_T parity; //!< Specifies the parity
USART_MODE_T mode; //!< Specifies the mode
USART_HARDWARE_FLOW_T hardwareFlow; //!< Specifies the hardware flow control
} USART_Config_T;
/**
* @brief USART synchronous communication clock config struct definition
*/
typedef struct
{
USART_CLKEN_T clock; //!< Enable or Disable Clock
USART_CLKPOL_T polarity; //!< Specifies the clock polarity
USART_CLKPHA_T phase; //!< Specifies the clock phase
USART_LBCP_T lastBit; //!< Enable or Disable last bit clock
} USART_ClockConfig_T;
/**@} end of group USART_Structure*/
/** @addtogroup USART_Fuctions Fuctions
@{
*/
/** USART Reset and Configuration */
void USART_Reset(USART_T* usart);
void USART_Config(USART_T* uart, USART_Config_T* usartConfig);
void USART_ConfigStructInit(USART_Config_T* usartConfig);
void USART_Address(USART_T* usart, uint8_t address);
void USART_Enable(USART_T* usart);
void USART_Disable(USART_T* usart);
/** Clock communication */
void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig);
void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig);
/** DMA mode */
void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq);
void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq);
/** Mute mode */
void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup);
void USART_EnableMuteMode(USART_T* usart);
void USART_DisableMuteMode(USART_T* usart);
/** LIN mode */
void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length);
void USART_EnableLIN(USART_T* usart);
void USART_DisableLIN(USART_T* usart);
/** Transmit and receive */
void USART_EnableTx(USART_T* usart);
void USART_DisableTx(USART_T* usart);
void USART_EnableRx(USART_T* usart);
void USART_DisableRx(USART_T* usart);
void USART_TxData(USART_T* usart, uint16_t data);
uint16_t USART_RxData(USART_T* usart);
void USART_TxBreak(USART_T* usart);
/** Smartcard mode */
void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime);
void USART_ConfigPrescaler(USART_T* usart, uint8_t div);
void USART_EnableSmartCard(USART_T* usart);
void USART_DisableSmartCard(USART_T* usart);
void USART_EnableSmartCardNACK(USART_T* usart);
void USART_DisableSmartCardNACK(USART_T* usart);
/** Half-duplex mode */
void USART_EnableHalfDuplex(USART_T* usart);
void USART_DisableHalfDuplex(USART_T* usart);
/** IrDA mode */
void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode);
void USART_EnableIrDA(USART_T* usart);
void USART_DisableIrDA(USART_T* usart);
/** Interrupt and flag */
void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt);
void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt);
uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag);
void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag);
uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag);
void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag);
/**@} end of group USART_Fuctions*/
/**@} end of group USART_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_USART_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h
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/*!
* @file apm32f10x_wwdt.h
*
* @brief This file contains all the functions prototypes for the WWDT firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_WWDT_H
#define __APM32F10X_WWDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup WWDT_Enumerations Enumerations
@{
*/
/**
* @brief WWDT Timebase(Prescaler) define
*/
typedef enum
{
WWDT_TIME_BASE_1 = 0x00000000,
WWDT_TIME_BASE_2 = 0x00000080,
WWDT_TIME_BASE_4 = 0x00000100,
WWDT_TIME_BASE_8 = 0x00000180
}WWDT_TIME_BASE_T;
/**@} end of group WWDT_Enumerations*/
/** @addtogroup WWDT_Fuctions Fuctions
@{
*/
/** WWDT reset */
void WWDT_Reset(void);
/** Config WWDT Timebase */
void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase);
/** Config Window Data */
void WWDT_ConfigWindowData(uint8_t windowData);
/** Config Couter */
void WWDT_ConfigCounter(uint8_t counter);
/** Enable WWDT and Early Wakeup interrupt */
void WWDT_EnableEWI(void);
void WWDT_Enable(uint8_t count);
/** Read Flag and Clear Flag */
uint8_t WWDT_ReadFlag(void);
void WWDT_ClearFlag(void);
/**@} end of group WWDT_Fuctions*/
/**@} end of group WWDT_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_WWDT_H */