Foreign-Mirrors/WeActStudio.EpaperModule
1
0
Fork 0
mirror of https://github.com/WeActStudio/WeActStudio.EpaperModule.git synced 2026-08-16 13:13:45 +02:00
Code Issues Packages Projects Releases Wiki Activity

first commit

Browse Source
This commit is contained in:
YXZhu
2022-08-06 13:35:32 +08:00
commit 2240710d39
1025 changed files with 472118 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h
+346
View File
@@ -0,0 +1,346 @@
/*!
* @file apm32f10x_adc.h
*
* @brief This file contains all the functions prototypes for the ADC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_ADC_H
#define __APM32F10X_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup ADC_Driver ADC Driver
@{
*/
/** @addtogroup ADC_Enumerations Enumerations
@{
*/
/**
* @brief ADC configuration Mode
*/
typedef enum
{
ADC_MODE_INDEPENDENT = ((uint32_t)0x00000000), //!< Independent mode
ADC_MODE_REG_INJEC_SIMULT = ((uint32_t)0x00010000), //!< Combined regular simultaneous and injected simultaneous mode
ADC_MODE_REG_SIMULT_ALTER_TRIG = ((uint32_t)0x00020000), //!< Combined regular simultaneous and alternate trigger mode
ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), //!< Combined injected simultaneous and fast interleaved mode
ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), //!< Combined injected simultaneous and slow interleaved mode
ADC_MODE_INJEC_SIMULT = ((uint32_t)0x00050000), //!< Injected simultaneous mode
ADC_MODE_REG_SIMULT = ((uint32_t)0x00060000), //!< Regular simultaneous mode
ADC_MODE_FAST_INTERL = ((uint32_t)0x00070000), //!< Fast interleaved mode
ADC_MODE_SLOW_INTERL = ((uint32_t)0x00080000), //!< Slow interleaved mode
ADC_MODE_ALTER_TRIG = ((uint32_t)0x00090000) //!< Alternate trigger mode
} ADC_MODE_T;
/**
* @brief ADC external trigger sources for regular channels conversion enumeration
*/
typedef enum
{
ADC_EXT_TRIG_CONV_TMR1_CC1 = ((uint32_t)0x00000000),
ADC_EXT_TRIG_CONV_TMR1_CC2 = ((uint32_t)0x00020000),
ADC_EXT_TRIG_CONV_TMR2_CC2 = ((uint32_t)0x00060000),
ADC_EXT_TRIG_CONV_TMR3_TRGO = ((uint32_t)0x00080000),
ADC_EXT_TRIG_CONV_TMR4_CC4 = ((uint32_t)0x000A0000),
ADC_EXT_TRIG_CONV_EINT9_T8_TRGO = ((uint32_t)0x000C0000),
ADC_EXT_TRIG_CONV_TMR1_CC3 = ((uint32_t)0x00040000),
ADC_EXT_TRIG_CONV_None = ((uint32_t)0x000E0000),
ADC_EXT_TRIG_CONV_TMR3_CC1 = ((uint32_t)0x00000000),
ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00020000),
ADC_EXT_TRIG_CONV_TMR8_CC1 = ((uint32_t)0x00060000),
ADC_EXT_TRIG_CONV_TMR8_TRGO = ((uint32_t)0x00080000),
ADC_EXT_TRIG_CONV_TMR5_CC1 = ((uint32_t)0x000A0000),
ADC_EXT_TRIG_CONV_TMR5_CC3 = ((uint32_t)0x000C0000)
} ADC_EXT_TRIG_CONV_T;
/**
* @brief ADC Data Align
*/
typedef enum
{
ADC_DATA_ALIGN_RIGHT = 0x00000000,
ADC_DATA_ALIGN_LEFT = 0x00000800
} ADC_DATA_ALIGN_T;
/**
* @brief ADC Channels
*/
typedef enum
{
ADC_CHANNEL_0 = ((uint8_t)0x00),
ADC_CHANNEL_1 = ((uint8_t)0x01),
ADC_CHANNEL_2 = ((uint8_t)0x02),
ADC_CHANNEL_3 = ((uint8_t)0x03),
ADC_CHANNEL_4 = ((uint8_t)0x04),
ADC_CHANNEL_5 = ((uint8_t)0x05),
ADC_CHANNEL_6 = ((uint8_t)0x06),
ADC_CHANNEL_7 = ((uint8_t)0x07),
ADC_CHANNEL_8 = ((uint8_t)0x08),
ADC_CHANNEL_9 = ((uint8_t)0x09),
ADC_CHANNEL_10 = ((uint8_t)0x0A),
ADC_CHANNEL_11 = ((uint8_t)0x0B),
ADC_CHANNEL_12 = ((uint8_t)0x0C),
ADC_CHANNEL_13 = ((uint8_t)0x0D),
ADC_CHANNEL_14 = ((uint8_t)0x0E),
ADC_CHANNEL_15 = ((uint8_t)0x0F),
ADC_CHANNEL_16 = ((uint8_t)0x10),
ADC_CHANNEL_TEMP_SENSOR = ((uint8_t)0x10),
ADC_CHANNEL_17 = ((uint8_t)0x11),
ADC_CHANNEL_V_REFINT = ((uint8_t)0x11)
} ADC_CHANNEL_T;
/**
* @brief ADC Sampling Time
*/
typedef enum
{
ADC_SAMPLETIME_1CYCLES5 = ((uint8_t)0x00),
ADC_SAMPLETIME_7CYCLES5 = ((uint8_t)0x01),
ADC_SAMPLETIME_13CYCLES5 = ((uint8_t)0x02),
ADC_SAMPLETIME_28CYCLES5 = ((uint8_t)0x03),
ADC_SAMPLETIME_41CYCLES5 = ((uint8_t)0x04),
ADC_SAMPLETIME_55CYCLES5 = ((uint8_t)0x05),
ADC_SAMPLETIME_71CYCLES5 = ((uint8_t)0x06),
ADC_SAMPLETIME_239CYCLES5 = ((uint8_t)0x07)
} ADC_SAMPLETIME_T;
/**
* @brief ADC external trigger sources for injected channels conversion
*/
typedef enum
{
/** for ADC1 and ADC2 */
ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO = ((uint8_t)0x02),
ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1 = ((uint8_t)0x03),
ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4 = ((uint8_t)0x04),
ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO = ((uint8_t)0x05),
ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4 = ((uint8_t)0x06),
/** for ADC1, ADC2 and ADC3 */
ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO = ((uint8_t)0x00),
ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4 = ((uint8_t)0x01),
ADC_EXT_TRIG_INJEC_CONV_NONE = ((uint8_t)0x07),
/** for ADC3 only */
ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3 = ((uint8_t)0x02),
ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2 = ((uint8_t)0x03),
ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4 = ((uint8_t)0x04),
ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO = ((uint8_t)0x05),
ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4 = ((uint8_t)0x06)
} ADC_EXT_TRIG_INJEC_CONV_T;
/**
* @brief ADC Injected channels
*/
typedef enum
{
ADC_INJEC_CHANNEL_1 = ((uint8_t)0x14),
ADC_INJEC_CHANNEL_2 = ((uint8_t)0x18),
ADC_INJEC_CHANNEL_3 = ((uint8_t)0x1C),
ADC_INJEC_CHANNEL_4 = ((uint8_t)0x20)
} ADC_INJEC_CHANNEL_T;
/**
* @brief ADC Analog Watchdog Selection
*/
typedef enum
{
ADC_ANALOG_WATCHDOG_SINGLE_REG = ((uint32_t)0x00800200),
ADC_ANALOG_WATCHDOG_SINGLE_INJEC = ((uint32_t)0x00400200),
ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC = ((uint32_t)0x00C00200),
ADC_ANALOG_WATCHDOG_ALL_REG = ((uint32_t)0x00800000),
ADC_ANALOG_WATCHDOG_ALL_INJEC = ((uint32_t)0x00400000),
ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC = ((uint32_t)0x00C00000),
ADC_ANALOG_WATCHDOG_NONE = ((uint32_t)0x00000000)
} ADC_ANALOG_WATCHDOG_T;
/**
* @brief ADC Interrupt definition
*/
typedef enum
{
ADC_INT_AWD = ((uint16_t)0x0140), //!< Analog Watchdog interrupt
ADC_INT_EOC = ((uint16_t)0x0220), //!< End Of Conversion interrupt
ADC_INT_INJEOC = ((uint16_t)0x0480) //!< Injected Channel End Of Conversion interrupt
} ADC_INT_T;
/**
* @brief ADC Flag
*/
typedef enum
{
ADC_FLAG_AWD = ((uint8_t)0x01), //!< Analog Watchdog event occur flag
ADC_FLAG_EOC = ((uint8_t)0x02), //!< End Of Conversion flag
ADC_FLAG_INJEOC = ((uint8_t)0x04), //!< Injected Channel End Of Conversion flag
ADC_FLAG_INJCS = ((uint8_t)0x08), //!< Injected Channel Conversion Start flag
ADC_FLAG_REGCS = ((uint8_t)0x10) //!< Regular Channel Conversion Start flag
} ADC_FLAG_T;
/**@} end of group ADC_Enumerations*/
/** @addtogroup ADC_Macros Macros
@{
*/
/** ADC_IJD Offset */
#define INJDATA_OFFSET ((uint8_t)0x28)
/** ADC_RDG register address */
#define RDG_ADDRESS ((uint32_t)0x4001244C)
/** INJSEQ register config */
#define INJSEQ_SET_INJSEQC ((uint32_t)0x0000001F)
#define INJSEQ_SET_INJSEQLEN ((uint32_t)0x00300000)
/** SMPTIM register SET */
#define SMPCYCCFG_SET_SMPTIM1 ((uint32_t)0x00000007)
#define SMPCYCCFG_SET_SMPTIM2 ((uint32_t)0x00000007)
/** REGSEQ register SET */
#define REGSEQC_SET_REGSEQ3 ((uint32_t)0x0000001F)
#define REGSEQC_SET_REGSEQ2 ((uint32_t)0x0000001F)
#define REGSEQC_SET_REGSEQ1 ((uint32_t)0x0000001F)
/**@} end of group ADC_Macros*/
/** @addtogroup ADC_Structure Data Structure
@{
*/
/**
* @brief ADC Config structure definition
*/
typedef struct
{
ADC_MODE_T mode;
uint8_t scanConvMode; //!< This parameter can be ENABLE or DISABLE.
uint8_t continuosConvMode; //!< This parameter can be ENABLE or DISABLE.
ADC_EXT_TRIG_CONV_T externalTrigConv;
ADC_DATA_ALIGN_T dataAlign;
uint8_t nbrOfChannel; //!< This parameter must range from 1 to 16.
} ADC_Config_T;
/**@} end of group ADC_Structure*/
/** @addtogroup ADC_Fuctions Fuctions
@{
*/
/** ADC reset and common configuration */
void ADC_Reset(ADC_T* adc);
void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig);
void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime);
void ADC_Enable(ADC_T* adc);
void ADC_Disable(ADC_T* adc);
/** ADC for DMA */
void ADC_EnableDMA(ADC_T* adc);
void ADC_DisableDMA(ADC_T* adc);
/** ADC Calibration */
void ADC_ResetCalibration(ADC_T* adc);
uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc);
void ADC_StartCalibration(ADC_T* adc);
uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc);
/** ADC software start conversion */
void ADC_EnableSoftwareStartConv(ADC_T* adc);
void ADC_DisableSoftwareStartConv(ADC_T* adc);
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc);
/** ADC Discontinuous mode */
void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number);
void ADC_EnableDiscMode(ADC_T* adc);
void ADC_DisableDiscMode(ADC_T* adc);
/** ADC External trigger conversion */
void ADC_EnableExternalTrigConv(ADC_T* adc);
void ADC_DisableExternalTrigConv(ADC_T* adc);
/** ADC Conversion result */
uint16_t ADC_ReadConversionValue(ADC_T* adc);
uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc);
/** ADC Automatic injected group */
void ADC_EnableAutoInjectedConv(ADC_T* adc);
void ADC_DisableAutoInjectedConv(ADC_T* adc);
void ADC_EnableInjectedDiscMode(ADC_T* adc);
void ADC_DisableInjectedDiscMode(ADC_T* adc);
/** ADC External trigger for injected channels conversion */
void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
void ADC_EnableExternalTrigInjectedConv(ADC_T* adc);
void ADC_DisableExternalTrigInjectedConv(ADC_T* adc);
/** ADC Start of the injected channels conversion */
void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc);
void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc);
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc);
/** ADC injected channel */
void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length);
void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel);
/** ADC analog watchdog */
void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog);
void ADC_DisableAnalogWatchdog(ADC_T* adc);
void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold);
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel);
/** ADC temperature sensor */
void ADC_EnableTempSensorVrefint(ADC_T* adc);
void ADC_DisableTempSensorVrefint(ADC_T* adc);
/** Interrupt and flag */
void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt);
void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt);
uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag);
void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag);
uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag);
void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag);
/**@} end of group ADC_Fuctions*/
/**@} end of group ADC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /** __APM32F10X_ADC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h
+149
View File
@@ -0,0 +1,149 @@
/*!
* @file apm32f10x_bakr.h
*
* @brief This file contains all the functions prototypes for the BAKPR firmware library.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_BAKPR_H
#define __APM32F10X_BAKPR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup BAKPR_Driver BAKPR Driver
@{
*/
/** @addtogroup BAKPR_Enumerations Enumerations
@{
*/
/**
* @brief BAKPR TAMPER Pin Active Level
*/
typedef enum
{
BAKPR_TAMPER_PIN_LEVEL_HIGH,
BAKPR_TAMPER_PIN_LEVEL_LOW
} BAKPR_TAMPER_PIN_LEVEL_T;
/**
* @brief BAKPR RTC output source
*/
typedef enum
{
BAKPR_RTC_OUTPUT_SOURCE_NONE,
BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK,
BAKPR_RTC_OUTPUT_SOURCE_ALARM,
BAKPR_RTC_OUTPUT_SOURCE_SECOND
} BAKPR_RTC_OUTPUT_SOURCE_T;
/**
* @brief BAKPR DATA register Addr
*/
typedef enum
{
BAKPR_DATA1 = ((uint16_t)0x0004),
BAKPR_DATA2 = ((uint16_t)0x0008),
BAKPR_DATA3 = ((uint16_t)0x000C),
BAKPR_DATA4 = ((uint16_t)0x0010),
BAKPR_DATA5 = ((uint16_t)0x0014),
BAKPR_DATA6 = ((uint16_t)0x0018),
BAKPR_DATA7 = ((uint16_t)0x001C),
BAKPR_DATA8 = ((uint16_t)0x0020),
BAKPR_DATA9 = ((uint16_t)0x0024),
BAKPR_DATA10 = ((uint16_t)0x0028),
BAKPR_DATA11 = ((uint16_t)0x0040),
BAKPR_DATA12 = ((uint16_t)0x0044),
BAKPR_DATA13 = ((uint16_t)0x0048),
BAKPR_DATA14 = ((uint16_t)0x004C),
BAKPR_DATA15 = ((uint16_t)0x0050),
BAKPR_DATA16 = ((uint16_t)0x0054),
BAKPR_DATA17 = ((uint16_t)0x0058),
BAKPR_DATA18 = ((uint16_t)0x005C),
BAKPR_DATA19 = ((uint16_t)0x0060),
BAKPR_DATA20 = ((uint16_t)0x0064),
BAKPR_DATA21 = ((uint16_t)0x0068),
BAKPR_DATA22 = ((uint16_t)0x006C),
BAKPR_DATA23 = ((uint16_t)0x0070),
BAKPR_DATA24 = ((uint16_t)0x0074),
BAKPR_DATA25 = ((uint16_t)0x0078),
BAKPR_DATA26 = ((uint16_t)0x007C),
BAKPR_DATA27 = ((uint16_t)0x0080),
BAKPR_DATA28 = ((uint16_t)0x0084),
BAKPR_DATA29 = ((uint16_t)0x0088),
BAKPR_DATA30 = ((uint16_t)0x008C),
BAKPR_DATA31 = ((uint16_t)0x0090),
BAKPR_DATA32 = ((uint16_t)0x0094),
BAKPR_DATA33 = ((uint16_t)0x0098),
BAKPR_DATA34 = ((uint16_t)0x009C),
BAKPR_DATA35 = ((uint16_t)0x00A0),
BAKPR_DATA36 = ((uint16_t)0x00A4),
BAKPR_DATA37 = ((uint16_t)0x00A8),
BAKPR_DATA38 = ((uint16_t)0x00AC),
BAKPR_DATA39 = ((uint16_t)0x00B0),
BAKPR_DATA40 = ((uint16_t)0x00B4),
BAKPR_DATA41 = ((uint16_t)0x00B8),
BAKPR_DATA42 = ((uint16_t)0x00BC)
} BAKPR_DATA_T;
/**@} end of group BAKPR_Enumerations*/
/** @addtogroup BAKPR_Fuctions Fuctions
@{
*/
/** BAKPR reset and configuration */
void BAKPR_Reset(void);
void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value);
void BAKPR_EnableTamperPin(void);
void BAKPR_DisableTamperPin(void);
void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure);
void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue);
void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data);
uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData);
/** Interrupts and flags */
void BAKPR_EnableInterrupt(void);
void BAKPR_DisableInterrupt(void);
uint8_t BAKPR_ReadStatusFlag(void);
void BAKPR_ClearStatusFlag(void);
uint8_t BAKPR_ReadIntFlag(void);
void BAKPR_ClearIntFlag(void);
/**@} end of group BAKPR_Fuctions*/
/**@} end of group BAKPR_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_BAKPR_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h
+349
View File
@@ -0,0 +1,349 @@
/*!
* @file apm32f10x_can.h
*
* @brief This file contains all the functions prototypes for the CAN firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_CAN_H
#define __APM32F10X_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup CAN_Driver CAN Driver
@{
*/
/** @addtogroup CAN_Enumerations Enumerations
@{
*/
/**
* @brief CAN mode
*/
typedef enum
{
CAN_MODE_NORMAL = ((uint8_t)0x00), //!< normal mode
CAN_MODE_LOOPBACK = ((uint8_t)0x01), //!< loopback mode
CAN_MODE_SILENT = ((uint8_t)0x02), //!< silent mode
CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03) //!< loopback combined with silent mode
} CAN_MODE_T;
/**
* @brief CAN synchronisation jump width
*/
typedef enum
{
CAN_SJW_1 = ((uint8_t)0x00), //!< 1 time quantum
CAN_SJW_2 = ((uint8_t)0x01), //!< 2 time quantum
CAN_SJW_3 = ((uint8_t)0x02), //!< 3 time quantum
CAN_SJW_4 = ((uint8_t)0x03) //!< 4 time quantum
} CAN_SJW_T;
/**
* @brief CAN time quantum in bit segment 1
*/
typedef enum
{
CAN_TIME_SEGMENT1_1 = ((uint8_t)0x00), //!< 1 time quanta
CAN_TIME_SEGMENT1_2 = ((uint8_t)0x01), //!< 2 time quanta
CAN_TIME_SEGMENT1_3 = ((uint8_t)0x02), //!< 3 time quanta
CAN_TIME_SEGMENT1_4 = ((uint8_t)0x03), //!< 4 time quanta
CAN_TIME_SEGMENT1_5 = ((uint8_t)0x04), //!< 5 time quanta
CAN_TIME_SEGMENT1_6 = ((uint8_t)0x05), //!< 6 time quanta
CAN_TIME_SEGMENT1_7 = ((uint8_t)0x06), //!< 7 time quanta
CAN_TIME_SEGMENT1_8 = ((uint8_t)0x07), //!< 8 time quanta
CAN_TIME_SEGMENT1_9 = ((uint8_t)0x08), //!< 9 time quanta
CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09), //!< 10 time quanta
CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A), //!< 11 time quanta
CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B), //!< 12 time quanta
CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C), //!< 13 time quanta
CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D), //!< 14 time quanta
CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E), //!< 15 time quanta
CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F) //!< 16 time quanta
} CAN_TIME_SEGMENT1_T;
/**
* @brief CAN time quantum in bit segment 2
*/
typedef enum
{
CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, //!< 1 time quanta
CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, //!< 2 time quanta
CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, //!< 3 time quanta
CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, //!< 4 time quanta
CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, //!< 5 time quanta
CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, //!< 6 time quanta
CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, //!< 7 time quanta
CAN_TIME_SEGMENT2_8 = (uint8_t)0x07 //!< 8 time quanta
} CAN_TIME_SEGMENT2_T;
/**
* @brief CAN filter FIFO
*/
typedef enum
{
CAN_FILTER_FIFO_0 = ((uint8_t)0x00), //!< filter FIFO 0
CAN_FILTER_FIFO_1 = ((uint8_t)0x01) //!< filter FIFO 1
} CAN_FILTER_FIFO_T;
/**
* @brief CAN filter mode
*/
typedef enum
{
CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),//!< identifier/mask mode
CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) //!< identifier list mode
} CAN_FILTER_MODE_T;
/**
* @brief CAN filter scale
*/
typedef enum
{
CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters
CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01) //!< One 32-bit filter
} CAN_FILTER_SCALE_T;
/**
* @brief CAN identifier type
*/
typedef enum
{
CAN_TYPEID_STD = ((uint32_t)0x00000000), //!< Standard Id
CAN_TYPEID_EXT = ((uint32_t)0x00000004) //!< Extended Id
} CAN_TYPEID_T;
/**
* @brief CAN_remote_transmission_request
*/
typedef enum
{
CAN_RTXR_DATA = ((uint32_t)0x00000000), //!< Data frame
CAN_RTXR_REMOTE = ((uint32_t)0x00000002) //!< Remote frame
} CAN_RTXR_T;
/**
* @brief Mailboxes definition
*/
typedef enum
{
CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0
CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1
CAN_TX_MAILBIX_2 = ((uint8_t)0x02) //!< Tx mailbox2
} CAN_TX_MAILBIX_T;
/**
* @brief CAN receive FIFO number constants
*/
typedef enum
{
CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0
CAN_RX_FIFO_1 = ((uint8_t)0x01) //!< receive FIFO 1
} CAN_RX_FIFO_T;
/**
* @brief CAN Operating Mode
*/
typedef enum
{
CAN_OPERATING_MODE_INIT = ((uint8_t)0x00), //!< Initialization mode
CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), //!< Normal mode
CAN_OPERATING_MODE_SLEEP = ((uint8_t)0x02) //!< sleep mode
} CAN_OPERATING_MODE_T;
/**
* @brief CAN Interrupts
*/
typedef enum
{
CAN_INT_TXME = ((uint32_t)0x00000001), //!< Transmit mailbox empty Interrupt
CAN_INT_F0MP = ((uint32_t)0x00000002), //!< FIFO 0 message pending Interrupt
CAN_INT_F0FULL = ((uint32_t)0x00000004), //!< FIFO 0 full Interrupt
CAN_INT_F0OVR = ((uint32_t)0x00000008), //!< FIFO 0 overrun Interrupt
CAN_INT_F1MP = ((uint32_t)0x00000010), //!< FIFO 1 message pending Interrupt
CAN_INT_F1FULL = ((uint32_t)0x00000020), //!< FIFO 1 full Interrupt
CAN_INT_F1OVR = ((uint32_t)0x00000040), //!< FIFO 1 overrun Interrupt
CAN_INT_ERRW = ((uint32_t)0x00000100), //!< Error warning Interrupt
CAN_INT_ERRP = ((uint32_t)0x00000200), //!< Error passive Interrupt
CAN_INT_BOF = ((uint32_t)0x00000400), //!< Bus-off Interrupt
CAN_INT_LEC = ((uint32_t)0x00000800), //!< Last error record code Interrupt
CAN_INT_ERR = ((uint32_t)0x00008000), //!< Error Interrupt
CAN_INT_WUP = ((uint32_t)0x00010000), //!< Wake-up Interrupt
CAN_INT_SLEEP = ((uint32_t)0x00020000) //!< Sleep acknowledge Interrupt
} CAN_INT_T;
/**
* @brief CAN Flags
*/
typedef enum
{
/** Error flag*/
CAN_FLAG_ERRW = ((uint32_t)0x10F00001), //!< Error Warning Flag
CAN_FLAG_ERRP = ((uint32_t)0x10F00002), //!< Error Passive Flag
CAN_FLAG_BOF = ((uint32_t)0x10F00004), //!< Bus-Off Flag
CAN_FLAG_LERRC = ((uint32_t)0x30F00070), //!< Last error record code Flag
/** Operating Mode Flags */
CAN_FLAG_WUPI = ((uint32_t)0x31000008), //!< Wake up Flag
CAN_FLAG_SLEEP = ((uint32_t)0x31000012), //!< Sleep acknowledge Flag
/** Receive Flags */
CAN_FLAG_F0MP = ((uint32_t)0x12000003), //!< FIFO 0 Message Pending Flag
CAN_FLAG_F0FULL = ((uint32_t)0x32000008), //!< FIFO 0 Full Flag
CAN_FLAG_F0OVR = ((uint32_t)0x32000010), //!< FIFO 0 Overrun Flag
CAN_FLAG_F1MP = ((uint32_t)0x14000003), //!< FIFO 1 Message Pending Flag
CAN_FLAG_F1FULL = ((uint32_t)0x34000008), //!< FIFO 1 Full Flag
CAN_FLAG_F1OVR = ((uint32_t)0x34000010), //!< FIFO 1 Overrun Flag
/** Transmit Flags */
CAN_FLAG_REQC0 = ((uint32_t)0x38000001), //!< Request MailBox0 Flag
CAN_FLAG_REQC1 = ((uint32_t)0x38000100), //!< Request MailBox1 Flag
CAN_FLAG_REQC2 = ((uint32_t)0x38010000) //!< Request MailBox2 Flag
} CAN_FLAG_T;
/**@} end of group CAN_Enumerations*/
/**
* @brief CAN Config structure definition
*/
/**
* @brief CAN config structure definition
*/
typedef struct
{
uint8_t autoBusOffManage; //!< Enable or disable the automatic bus-off management.
uint8_t autoWakeUpMode; //!< Enable or disable the automatic wake-up mode.
uint8_t nonAutoRetran; //!< Enable or disable the non-automatic retransmission mode.
uint8_t rxFIFOLockMode; //!< Enable or disable the Receive FIFO Locked mode.
uint8_t txFIFOPriority; //!< Enable or disable the transmit FIFO priority.
CAN_MODE_T mode; //!< Specifies the CAN operating mode.
CAN_SJW_T syncJumpWidth; /** Specifies the maximum number of time quanta the CAN hardware
* is allowed to lengthen or shorten a bit to perform resynchronization.
*/
CAN_TIME_SEGMENT1_T timeSegment1; //!< Specifies the number of time quanta in Bit Segment 1.
CAN_TIME_SEGMENT2_T timeSegment2; //!< Specifies the number of time quanta in Bit Segment 2.
uint16_t prescaler; //!< Specifies the length of a time quantum. It can be 1 to 1024.
} CAN_Config_T;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF.
uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
CAN_TYPEID_T typeID;
CAN_RTXR_T remoteTxReq;
uint8_t dataLengthCode;//!< Specifies the data length code. It can be 0 to 8.
uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
} CAN_TxMessage_T;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF.
uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
uint32_t typeID;
uint32_t remoteTxReq;
uint8_t dataLengthCode; //!< Specifies the data length code. It can be 0 to 8.
uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
uint8_t filterMatchIndex;//!< Specifies the filter match index. It can be 0 to 0xFF.
} CAN_RxMessage_T;
/**
* @brief CAN filter config structure definition
*/
typedef struct
{
uint8_t filterNumber; //!< Specifies the filter number. It can be 0 to 13.
uint16_t filterIdHigh; //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
uint16_t filterIdLow; //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
uint16_t filterMaskIdHigh; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF.
uint16_t filterMaskIdLow; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF.
uint16_t filterActivation; //!< Specifies the filter Activation. It can be ENABLE or DISABLE.
CAN_FILTER_FIFO_T filterFIFO;
CAN_FILTER_MODE_T filterMode;
CAN_FILTER_SCALE_T filterScale;
} CAN_FilterConfig_T;
/**@} end of group CAN_Structure*/
/** @addtogroup CAN_Fuctions Fuctions
@{
*/
/** CAN reset and configuration */
void CAN_Reset(CAN_T* can);
uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig);
void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig);
void CAN_ConfigStructInit(CAN_Config_T* canConfig);
void CAN_EnableDBGFreeze(CAN_T* can);
void CAN_DisableDBGFreeze(CAN_T* can);
void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum);
/** CAN frames transmit */
uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage);
uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
/** CAN frames receive */
void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage);
void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
/** CAN operation modes */
uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode);
uint8_t CAN_SleepMode(CAN_T* can);
uint8_t CAN_WakeUpMode(CAN_T* can);
/** CAN bus error management */
uint8_t CAN_ReadLastErrorCode(CAN_T* can);
uint8_t CAN_ReadRxErrorCounter(CAN_T* can);
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can);
/** CAN interrupt and flag */
void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt);
void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt);
uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag);
void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag);
uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag);
void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag);
/**@} end of group CAN_Fuctions*/
/**@} end of group CAN_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_CAN_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h
+66
View File
@@ -0,0 +1,66 @@
/*!
* @file apm32f10x_crc.h
*
* @brief This file contains all the functions prototypes for the CRC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_CRC_H
#define __APM32F10X_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup CRC_Driver CRC Driver
@{
*/
/** @addtogroup CRC_Fuctions Fuctions
@{
*/
/** Reset DATA */
void CRC_ResetDATA(void);
/** Operation functions */
uint32_t CRC_CalculateCRC(uint32_t data);
uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen);
uint32_t CRC_ReadCRC(void);
void CRC_WriteIDRegister(uint8_t inData);
uint8_t CRC_ReadIDRegister(void);
/**@} end of group CRC_Fuctions*/
/**@} end of group CRC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_CRC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h
+195
View File
@@ -0,0 +1,195 @@
/*!
* @file apm32f10x_dac.h
*
* @brief This file contains all the functions prototypes for the DAC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DAC_H
#define __APM32F10X_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DAC_Driver DAC Driver
@{
*/
/** @addtogroup DAC_Enumerations Enumerations
@{
*/
/**
* @brief DAC Channel selection
*/
typedef enum
{
DAC_CHANNEL_1 = 0x00000000,
DAC_CHANNEL_2 = 0x00000010
}DAC_CHANNEL_T;
/**
* @brief DAC trigger selection
*/
typedef enum
{
DAC_TRIGGER_NONE = 0x00000000,
DAC_TRIGGER_TMR6_TRGO = 0x00000004,
DAC_TRIGGER_TMR8_TRGO = 0x0000000C,
DAC_TRIGGER_TMR7_TRGO = 0x00000014,
DAC_TRIGGER_TMR5_TRGO = 0x0000001C,
DAC_TRIGGER_TMR2_TRGO = 0x00000024,
DAC_TRIGGER_TMR4_TRGO = 0x0000002C,
DAC_TRIGGER_EINT9 = 0x00000034,
DAC_TRIGGER_SOFT = 0x0000003C
}DAC_TRIGGER_T;
/**
* @brief DAC wave generation
*/
typedef enum
{
DAC_WAVE_GENERATION_NONE = 0x00000000,
DAC_WAVE_GENERATION_NOISE = 0x00000040,
DAC_WAVE_GENERATION_TRIANGLE = 0x00000080
}DAC_WAVE_GENERATION_T;
/**
* @brief DAC channelx mask/amplitude selector
*/
typedef enum
{
DAC_LFSR_MASK_BIT11_1 = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_2 = 0x00000100, //!< Mask bit[11:2] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_3 = 0x00000200, //!< Mask bit[11:3] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_4 = 0x00000300, //!< Mask bit[11:4] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_5 = 0x00000400, //!< Mask bit[11:5] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_6 = 0x00000500, //!< Mask bit[11:6] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_7 = 0x00000600, //!< Mask bit[11:7] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_8 = 0x00000700, //!< Mask bit[11:8] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_9 = 0x00000800, //!< Mask bit[11:9] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11_10 = 0x00000900, //!< Mask bit[11:10] of LFSR for noise wave generation
DAC_LFSR_MASK_BIT11 = 0x00000A00, //!< Mask bit11 of LFSR for noise wave generation
DAC_LFSR_MASK_NONE = 0x00000B00, //!< Mask none bit of LFSR for noise wave generation
DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, //!< Triangle amplitude equal to 1
DAC_TRIANGLE_AMPLITUDE_3 = 0x00000100, //!< Triangle amplitude equal to 3
DAC_TRIANGLE_AMPLITUDE_7 = 0x00000200, //!< Triangle amplitude equal to 7
DAC_TRIANGLE_AMPLITUDE_15 = 0x00000300, //!< Triangle amplitude equal to 15
DAC_TRIANGLE_AMPLITUDE_31 = 0x00000400, //!< Triangle amplitude equal to 31
DAC_TRIANGLE_AMPLITUDE_63 = 0x00000500, //!< Triangle amplitude equal to 63
DAC_TRIANGLE_AMPLITUDE_127 = 0x00000600, //!< Triangle amplitude equal to 127
DAC_TRIANGLE_AMPLITUDE_255 = 0x00000700, //!< Triangle amplitude equal to 255
DAC_TRIANGLE_AMPLITUDE_511 = 0x00000800, //!< Triangle amplitude equal to 511
DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023
DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047
DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00 //!< Triangle amplitude equal to 4095
}DAC_MASK_AMPLITUDE_SEL_T;
/**
* @brief DAC output buffer
*/
typedef enum
{
DAC_OUTPUT_BUFFER_ENBALE = 0x00000000,
DAC_OUTPUT_BUFFER_DISABLE = 0x00000002
}DAC_OUTPUT_BUFFER_T;
/**
* @brief DAC data align
*/
typedef enum
{
DAC_ALIGN_12BIT_R = 0x00000000,
DAC_ALIGN_12BIT_L = 0x00000004,
DAC_ALIGN_8BIT_R = 0x00000008
}DAC_ALIGN_T;
/**@} end of group DAC_Enumerations*/
/** @addtogroup DAC_Structure Data Structure
@{
*/
/**
* @brief DAC Config structure definition
*/
typedef struct
{
DAC_TRIGGER_T trigger;
DAC_OUTPUT_BUFFER_T outputBuffer;
DAC_WAVE_GENERATION_T waveGeneration;
DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect;
}DAC_Config_T;
/**@} end of group DAC_Structure*/
/** @addtogroup DAC_Fuctions Fuctions
@{
*/
/** DAC Reset and Configuration */
void DAC_Reset(void);
void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig);
void DAC_ConfigStructInit(DAC_Config_T* dacConfig);
void DAC_Enable(DAC_CHANNEL_T channel);
void DAC_Disable(DAC_CHANNEL_T channel);
/** DAC channel for DAM */
void DAC_DMA_Enable(DAC_CHANNEL_T channel);
void DAC_DMA_Disable(DAC_CHANNEL_T channel);
/** DAC channel software trigger */
void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel);
void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel);
void DAC_EnableDualSoftwareTrigger(void);
void DAC_DisableDualSoftwareTrigger(void);
/** DAC channel wave generation */
void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
/** DAC set channel data */
void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data);
void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data);
void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1);
/** DAC read data output value */
uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel);
/**@} end of group DAC_Fuctions*/
/**@} end of group DAC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DAC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h
+97
View File
@@ -0,0 +1,97 @@
/*!
* @file apm32f10x_dbgmcu.h
*
* @brief This file contains all the functions prototypes for the DBUGMCU firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DBGMCU_H
#define __APM32F10X_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DBGMCU_Driver DBGMCU Driver
@{
*/
/** @addtogroup DBGMCU_Enumerations Enumerations
@{
*/
enum
{
DBGMCU_SLEEP = ((uint32_t)0x00000001),
DBGMCU_STOP = ((uint32_t)0x00000002),
DBGMCU_STANDBY = ((uint32_t)0x00000004),
DBGMCU_IWDT_STOP = ((uint32_t)0x00000100),
DBGMCU_WWDT_STOP = ((uint32_t)0x00000200),
DBGMCU_TMR1_STOP = ((uint32_t)0x00000400),
DBGMCU_TMR2_STOP = ((uint32_t)0x00000800),
DBGMCU_TMR3_STOP = ((uint32_t)0x00001000),
DBGMCU_TMR4_STOP = ((uint32_t)0x00002000),
DBGMCU_CAN1_STOP = ((uint32_t)0x00004000),
DBGMCU_I2C1_SMBUS_TIMEOUT = ((uint32_t)0x00008000),
DBGMCU_I2C2_SMBUS_TIMEOUT = ((uint32_t)0x00010000),
DBGMCU_TMR8_STOP = ((uint32_t)0x00020000),
DBGMCU_TMR5_STOP = ((uint32_t)0x00040000),
DBGMCU_TMR6_STOP = ((uint32_t)0x00080000),
DBGMCU_TMR7_STOP = ((uint32_t)0x00100000),
DBGMCU_CAN2_STOP = ((uint32_t)0x00200000),
DBGMCU_TMR15_STOP = ((uint32_t)0x00400000),
DBGMCU_TMR16_STOP = ((uint32_t)0x00800000),
DBGMCU_TMR17_STOP = ((uint32_t)0x01000000),
DBGMCU_TMR12_STOP = ((uint32_t)0x02000000),
DBGMCU_TMR13_STOP = ((uint32_t)0x04000000),
DBGMCU_TMR14_STOP = ((uint32_t)0x08000000),
DBGMCU_TMR9_STOP = ((uint32_t)0x10000000),
DBGMCU_TMR10_STOP = ((uint32_t)0x20000000),
DBGMCU_TMR11_STOP = ((uint32_t)0x40000000),
};
/**@} end of group DBGMCU_Enumerations*/
/** @addtogroup DBGMCU_Fuctions Fuctions
@{
*/
uint32_t DBGMCU_ReadDEVID(void);
uint32_t DBGMCU_ReadREVID(void);
void DBGMCU_Enable(uint32_t periph);
void DBGMCU_Disable(uint32_t periph);
/**@} end of group DBGMCU_Fuctions*/
/**@} end of group DBGMCU_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DBGMCU_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h
+304
View File
@@ -0,0 +1,304 @@
/*!
* @file apm32f10x_dma.h
*
* @brief This file contains all the functions prototypes for the DMA firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DMA_H
#define __APM32F10X_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DMA_Driver DMA Driver
@{
*/
/** @addtogroup DMA_Enumerations Enumerations
@{
*/
/**
* @brief DMA Transmission direction
*/
typedef enum
{
DMA_DIR_PERIPHERAL_SRC,
DMA_DIR_PERIPHERAL_DST
} DMA_DIR_T;
/**
* @brief DMA Peripheral address increment
*/
typedef enum
{
DMA_PERIPHERAL_INC_DISABLE,
DMA_PERIPHERAL_INC_ENABLE
} DMA_PERIPHERAL_INC_T;
/**
* @brief DMA Memory address increment
*/
typedef enum
{
DMA_MEMORY_INC_DISABLE,
DMA_MEMORY_INC_ENABLE
} DMA_MEMORY_INC_T;
/**
* @brief DMA Peripheral Data Size
*/
typedef enum
{
DMA_PERIPHERAL_DATA_SIZE_BYTE,
DMA_PERIPHERAL_DATA_SIZE_HALFWORD,
DMA_PERIPHERAL_DATA_SIZE_WOED
} DMA_PERIPHERAL_DATA_SIZE_T;
/**
* @brief DMA Memory Data Size
*/
typedef enum
{
DMA_MEMORY_DATA_SIZE_BYTE,
DMA_MEMORY_DATA_SIZE_HALFWORD,
DMA_MEMORY_DATA_SIZE_WOED
} DMA_MEMORY_DATA_SIZE_T;
/**
* @brief DMA Mode
*/
typedef enum
{
DMA_MODE_NORMAL,
DMA_MODE_CIRCULAR
} DMA_LOOP_MODE_T;
/**
* @brief DMA priority level
*/
typedef enum
{
DMA_PRIORITY_LOW,
DMA_PRIORITY_MEDIUM,
DMA_PRIORITY_HIGH,
DMA_PRIORITY_VERYHIGH
} DMA_PRIORITY_T;
/**
* @brief DMA Memory to Memory
*/
typedef enum
{
DMA_M2MEN_DISABLE,
DMA_M2MEN_ENABLE
} DMA_M2MEN_T;
/**
* @brief DMA interrupt
*/
typedef enum
{
DMA_INT_TC = 0x00000002,
DMA_INT_HT = 0x00000004,
DMA_INT_TERR = 0x00000008
} DMA_INT_T;
/**
* @brief DMA Flag
*/
typedef enum
{
DMA1_FLAG_GINT1 = 0x00000001,
DMA1_FLAG_TC1 = 0x00000002,
DMA1_FLAG_HT1 = 0x00000004,
DMA1_FLAG_TERR1 = 0x00000008,
DMA1_FLAG_GINT2 = 0x00000010,
DMA1_FLAG_TC2 = 0x00000020,
DMA1_FLAG_HT2 = 0x00000040,
DMA1_FLAG_TERR2 = 0x00000080,
DMA1_FLAG_GINT3 = 0x00000100,
DMA1_FLAG_TC3 = 0x00000200,
DMA1_FLAG_HT3 = 0x00000400,
DMA1_FLAG_TERR3 = 0x00000800,
DMA1_FLAG_GINT4 = 0x00001000,
DMA1_FLAG_TC4 = 0x00002000,
DMA1_FLAG_HT4 = 0x00004000,
DMA1_FLAG_TERR4 = 0x00008000,
DMA1_FLAG_GINT5 = 0x00010000,
DMA1_FLAG_TC5 = 0x00020000,
DMA1_FLAG_HT5 = 0x00040000,
DMA1_FLAG_TERR5 = 0x00080000,
DMA1_FLAG_GINT6 = 0x00100000,
DMA1_FLAG_TC6 = 0x00200000,
DMA1_FLAG_HT6 = 0x00400000,
DMA1_FLAG_TERR6 = 0x00800000,
DMA1_FLAG_GINT7 = 0x01000000,
DMA1_FLAG_TC7 = 0x02000000,
DMA1_FLAG_HT7 = 0x04000000,
DMA1_FLAG_TERR7 = 0x08000000,
DMA2_FLAG_GINT1 = 0x10000001,
DMA2_FLAG_TC1 = 0x10000002,
DMA2_FLAG_HT1 = 0x10000004,
DMA2_FLAG_TERR1 = 0x10000008,
DMA2_FLAG_GINT2 = 0x10000010,
DMA2_FLAG_TC2 = 0x10000020,
DMA2_FLAG_HT2 = 0x10000040,
DMA2_FLAG_TERR2 = 0x10000080,
DMA2_FLAG_GINT3 = 0x10000100,
DMA2_FLAG_TC3 = 0x10000200,
DMA2_FLAG_HT3 = 0x10000400,
DMA2_FLAG_TERR3 = 0x10000800,
DMA2_FLAG_GINT4 = 0x10001000,
DMA2_FLAG_TC4 = 0x10002000,
DMA2_FLAG_HT4 = 0x10004000,
DMA2_FLAG_TERR4 = 0x10008000,
DMA2_FLAG_GINT5 = 0x10010000,
DMA2_FLAG_TC5 = 0x10020000,
DMA2_FLAG_HT5 = 0x10040000,
DMA2_FLAG_TERR5 = 0x10080000
} DMA_FLAG_T;
/**
* @brief DMA Interrupt Flag
*/
typedef enum
{
DMA1_INT_FLAG_GINT1 = 0x00000001,
DMA1_INT_FLAG_TC1 = 0x00000002,
DMA1_INT_FLAG_HT1 = 0x00000004,
DMA1_INT_FLAG_TERR1 = 0x00000008,
DMA1_INT_FLAG_GINT2 = 0x00000010,
DMA1_INT_FLAG_TC2 = 0x00000020,
DMA1_INT_FLAG_HT2 = 0x00000040,
DMA1_INT_FLAG_TERR2 = 0x00000080,
DMA1_INT_FLAG_GINT3 = 0x00000100,
DMA1_INT_FLAG_TC3 = 0x00000200,
DMA1_INT_FLAG_HT3 = 0x00000400,
DMA1_INT_FLAG_TERR3 = 0x00000800,
DMA1_INT_FLAG_GINT4 = 0x00001000,
DMA1_INT_FLAG_TC4 = 0x00002000,
DMA1_INT_FLAG_HT4 = 0x00004000,
DMA1_INT_FLAG_TERR4 = 0x00008000,
DMA1_INT_FLAG_GINT5 = 0x00010000,
DMA1_INT_FLAG_TC5 = 0x00020000,
DMA1_INT_FLAG_HT5 = 0x00040000,
DMA1_INT_FLAG_TERR5 = 0x00080000,
DMA1_INT_FLAG_GINT6 = 0x00100000,
DMA1_INT_FLAG_TC6 = 0x00200000,
DMA1_INT_FLAG_HT6 = 0x00400000,
DMA1_INT_FLAG_TERR6 = 0x00800000,
DMA1_INT_FLAG_GINT7 = 0x01000000,
DMA1_INT_FLAG_TC7 = 0x02000000,
DMA1_INT_FLAG_HT7 = 0x04000000,
DMA1_INT_FLAG_TERR7 = 0x08000000,
DMA2_INT_FLAG_GINT1 = 0x10000001,
DMA2_INT_FLAG_TC1 = 0x10000002,
DMA2_INT_FLAG_HT1 = 0x10000004,
DMA2_INT_FLAG_TERR1 = 0x10000008,
DMA2_INT_FLAG_GINT2 = 0x10000010,
DMA2_INT_FLAG_TC2 = 0x10000020,
DMA2_INT_FLAG_HT2 = 0x10000040,
DMA2_INT_FLAG_TERR2 = 0x10000080,
DMA2_INT_FLAG_GINT3 = 0x10000100,
DMA2_INT_FLAG_TC3 = 0x10000200,
DMA2_INT_FLAG_HT3 = 0x10000400,
DMA2_INT_FLAG_TERR3 = 0x10000800,
DMA2_INT_FLAG_GINT4 = 0x10001000,
DMA2_INT_FLAG_TC4 = 0x10002000,
DMA2_INT_FLAG_HT4 = 0x10004000,
DMA2_INT_FLAG_TERR4 = 0x10008000,
DMA2_INT_FLAG_GINT5 = 0x10010000,
DMA2_INT_FLAG_TC5 = 0x10020000,
DMA2_INT_FLAG_HT5 = 0x10040000,
DMA2_INT_FLAG_TERR5 = 0x10080000
} DMA_INT_FLAG_T;
/**@} end of group DMA_Enumerations*/
/** @addtogroup DMA_Structure Data Structure
@{
*/
/**
* @brief DMA Config struct definition
*/
typedef struct
{
uint32_t peripheralBaseAddr;
uint32_t memoryBaseAddr;
DMA_DIR_T dir;
uint32_t bufferSize;
DMA_PERIPHERAL_INC_T peripheralInc;
DMA_MEMORY_INC_T memoryInc;
DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize;
DMA_MEMORY_DATA_SIZE_T memoryDataSize;
DMA_LOOP_MODE_T loopMode;
DMA_PRIORITY_T priority;
DMA_M2MEN_T M2M;
} DMA_Config_T;
/**@} end of group DMA_Structure*/
/** @addtogroup DMA_Fuctions Fuctions
@{
*/
/** Reset and configuration */
void DMA_Reset(DMA_Channel_T *channel);
void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
void DMA_ConfigStructInit( DMA_Config_T* dmaConfig);
void DMA_Enable(DMA_Channel_T *channel);
void DMA_Disable(DMA_Channel_T *channel);
/** Data number */
void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber);
uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel);
/** Interrupt and flag */
void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
void DMA_ClearStatusFlag(uint32_t flag);
uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
void DMA_ClearIntFlag(uint32_t flag);
/**@} end of group DMA_Fuctions*/
/**@} end of group DMA_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DMA_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h
+379
View File
@@ -0,0 +1,379 @@
/*!
* @file apm32f10x_dmc.h
*
* @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_DMC_H
#define __APM32F10X_DMC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DMC_Driver DMC Driver
@{
*/
/** @addtogroup DMC_Enumerations Enumerations
@{
*/
/**
* @brief Bank Address Width
*/
typedef enum
{
DMC_BANK_WIDTH_1,
DMC_BANK_WIDTH_2
}DMC_BANK_WIDTH_T;
/**
* @brief Row Address Width
*/
typedef enum
{
DMC_ROW_WIDTH_11 = 0x0A,
DMC_ROW_WIDTH_12,
DMC_ROW_WIDTH_13,
DMC_ROW_WIDTH_14,
DMC_ROW_WIDTH_15,
DMC_ROW_WIDTH_16
}DMC_ROW_WIDTH_T;
/**
* @brief Column Address Width
*/
typedef enum
{
DMC_COL_WIDTH_8 = 0x07,
DMC_COL_WIDTH_9,
DMC_COL_WIDTH_10,
DMC_COL_WIDTH_11,
DMC_COL_WIDTH_12,
DMC_COL_WIDTH_13,
DMC_COL_WIDTH_14,
DMC_COL_WIDTH_15
}DMC_COL_WIDTH_T;
/**
* @brief CAS Latency Select
*/
typedef enum
{
DMC_CAS_LATENCY_1,
DMC_CAS_LATENCY_2,
DMC_CAS_LATENCY_3,
DMC_CAS_LATENCY_4
}DMC_CAS_LATENCY_T;
/**
* @brief RAS Minimun Time Select
*/
typedef enum
{
DMC_RAS_MINIMUM_1,
DMC_RAS_MINIMUM_2,
DMC_RAS_MINIMUM_3,
DMC_RAS_MINIMUM_4,
DMC_RAS_MINIMUM_5,
DMC_RAS_MINIMUM_6,
DMC_RAS_MINIMUM_7,
DMC_RAS_MINIMUM_8,
DMC_RAS_MINIMUM_9,
DMC_RAS_MINIMUM_10,
DMC_RAS_MINIMUM_11,
DMC_RAS_MINIMUM_12,
DMC_RAS_MINIMUM_13,
DMC_RAS_MINIMUM_14,
DMC_RAS_MINIMUM_15,
DMC_RAS_MINIMUM_16
}DMC_RAS_MINIMUM_T;
/**
* @brief RAS To CAS Delay Time Select
*/
typedef enum
{
DMC_DELAY_TIME_1,
DMC_DELAY_TIME_2,
DMC_DELAY_TIME_3,
DMC_DELAY_TIME_4,
DMC_DELAY_TIME_5,
DMC_DELAY_TIME_6,
DMC_DELAY_TIME_7,
DMC_DELAY_TIME_8
}DMC_DELAY_TIME_T;
/**
* @brief Precharge Period Select
*/
typedef enum
{
DMC_PRECHARGE_1,
DMC_PRECHARGE_2,
DMC_PRECHARGE_3,
DMC_PRECHARGE_4,
DMC_PRECHARGE_5,
DMC_PRECHARGE_6,
DMC_PRECHARGE_7,
DMC_PRECHARGE_8
}DMC_PRECHARGE_T;
/**
* @brief Last Data Next Precharge For Write Time Select
*/
typedef enum
{
DMC_NEXT_PRECHARGE_1,
DMC_NEXT_PRECHARGE_2,
DMC_NEXT_PRECHARGE_3,
DMC_NEXT_PRECHARGE_4
}DMC_NEXT_PRECHARGE_T;
/**
* @brief Auto-Refresh Period Select
*/
typedef enum
{
DMC_AUTO_REFRESH_1,
DMC_AUTO_REFRESH_2,
DMC_AUTO_REFRESH_3,
DMC_AUTO_REFRESH_4,
DMC_AUTO_REFRESH_5,
DMC_AUTO_REFRESH_6,
DMC_AUTO_REFRESH_7,
DMC_AUTO_REFRESH_8,
DMC_AUTO_REFRESH_9,
DMC_AUTO_REFRESH_10,
DMC_AUTO_REFRESH_11,
DMC_AUTO_REFRESH_12,
DMC_AUTO_REFRESH_13,
DMC_AUTO_REFRESH_14,
DMC_AUTO_REFRESH_15,
DMC_AUTO_REFRESH_16,
}DMC_AUTO_REFRESH_T;
/**
* @brief Active-to-active Command Period Select
*/
typedef enum
{
DMC_ATA_CMD_1,
DMC_ATA_CMD_2,
DMC_ATA_CMD_3,
DMC_ATA_CMD_4,
DMC_ATA_CMD_5,
DMC_ATA_CMD_6,
DMC_ATA_CMD_7,
DMC_ATA_CMD_8,
DMC_ATA_CMD_9,
DMC_ATA_CMD_10,
DMC_ATA_CMD_11,
DMC_ATA_CMD_12,
DMC_ATA_CMD_13,
DMC_ATA_CMD_14,
DMC_ATA_CMD_15,
DMC_ATA_CMD_16,
}DMC_ATA_CMD_T;
/**
* @brief Clock PHASE
*/
typedef enum
{
DMC_CLK_PHASE_NORMAL,
DMC_CLK_PHASE_REVERSE
}DMC_CLK_PHASE_T;
/**
* @brief DMC Memory Size
*/
typedef enum
{
DMC_MEMORY_SIZE_0,
DMC_MEMORY_SIZE_64KB,
DMC_MEMORY_SIZE_128KB,
DMC_MEMORY_SIZE_256KB,
DMC_MEMORY_SIZE_512KB,
DMC_MEMORY_SIZE_1MB,
DMC_MEMORY_SIZE_2MB,
DMC_MEMORY_SIZE_4MB,
DMC_MEMORY_SIZE_8MB,
DMC_MEMORY_SIZE_16MB,
DMC_MEMORY_SIZE_32MB,
DMC_MEMORY_SIZE_64MB,
DMC_MEMORY_SIZE_128MB,
DMC_MEMORY_SIZE_256MB,
}DMC_MEMORY_SIZE_T;
/**
* @brief Open Banks Of Number
*/
typedef enum
{
DMC_BANK_NUMBER_1,
DMC_BANK_NUMBER_2,
DMC_BANK_NUMBER_3,
DMC_BANK_NUMBER_4,
DMC_BANK_NUMBER_5,
DMC_BANK_NUMBER_6,
DMC_BANK_NUMBER_7,
DMC_BANK_NUMBER_8,
DMC_BANK_NUMBER_9,
DMC_BANK_NUMBER_10,
DMC_BANK_NUMBER_11,
DMC_BANK_NUMBER_12,
DMC_BANK_NUMBER_13,
DMC_BANK_NUMBER_14,
DMC_BANK_NUMBER_15,
DMC_BANK_NUMBER_16,
}DMC_BANK_NUMBER_T;
/**
* @brief Full refresh type
*/
typedef enum
{
DMC_REFRESH_ROW_ONE, //!< Refresh one row
DMC_REFRESH_ROW_ALL, //!< Refresh all row
}DMC_REFRESH_T;
/**
* @brief Precharge type
*/
typedef enum
{
DMC_PRECHARGE_IM, //!< Immediate precharge
DMC_PRECHARGE_DELAY, //!< Delayed precharge
}DMC_PRECHARE_T;
/**
* @brief WRAP Burst Type
*/
typedef enum
{
DMC_WRAPB_4,
DMC_WRAPB_8,
}DMC_WRPB_T;
/**@} end of group DMC_Enumerations*/
/** @addtogroup DMC_Structure Data Structure
@{
*/
/**
* @brief Timing config definition
*/
typedef struct
{
uint32_t latencyCAS : 2; //!< DMC_CAS_LATENCY_T
uint32_t tRAS : 4; //!< DMC_RAS_MINIMUM_T
uint32_t tRCD : 3; //!< DMC_DELAY_TIME_T
uint32_t tRP : 3; //!< DMC_PRECHARGE_T
uint32_t tWR : 2; //!< DMC_NEXT_PRECHARGE_T
uint32_t tARP : 4; //!< DMC_AUTO_REFRESH_T
uint32_t tCMD : 4; //!< DMC_ATA_CMD_T
uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF
uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF
}DMC_TimingConfig_T;
/**
* @brief Config struct definition
*/
typedef struct
{
DMC_MEMORY_SIZE_T memorySize; //!< Memory size(byte)
DMC_BANK_WIDTH_T bankWidth; //!< Number of bank bits
DMC_ROW_WIDTH_T rowWidth; //!< Number of row address bits
DMC_COL_WIDTH_T colWidth; //!< Number of col address bits
DMC_CLK_PHASE_T clkPhase; //!< Clock phase
DMC_TimingConfig_T timing; //!< Timing
}DMC_Config_T;
/**@} end of group DMC_Structure*/
/** @addtogroup DMC_Fuctions Fuctions
@{
*/
/** Enable / Disable */
void DMC_Enable(void);
void DMC_Disable(void);
void DMC_EnableInit(void);
/** Global config */
void DMC_Config(DMC_Config_T* dmcConfig);
void DMC_ConfigStructInit(DMC_Config_T* dmcConfig);
/** Address */
void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
/** Timing */
void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig);
void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig);
void DMC_ConfigStableTimePowerup(uint16_t stableTime);
void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
void DMC_ConfigRefreshPeriod(uint16_t period);
/** Refresh mode */
void DMC_EixtSlefRefreshMode(void);
void DMC_EnterSlefRefreshMode(void);
/** Accelerate Module */
void DMC_EnableAccelerateModule(void);
void DMC_DisableAccelerateModule(void);
/** Config */
void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
void DMC_EnableUpdateMode(void);
void DMC_EnterPowerdownMode(void);
void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh);
void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
void DMC_ConfigWRAPB(DMC_WRPB_T burst);
/** read flag */
uint8_t DMC_ReadSelfRefreshStatus(void);
/**@} end of group DMC_Fuctions*/
/**@} end of group DMC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_DMC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h
+135
View File
@@ -0,0 +1,135 @@
/*!
* @file apm32f10x_eint.h
*
* @brief This file contains all the functions prototypes for the EINT firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_EINT_H
#define __APM32F10X_EINT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup EINT_Driver EINT Driver
@{
*/
/** @addtogroup EINT_Enumerations Enumerations
@{
*/
/**
* @brief EINT mode enumeration
*/
typedef enum
{
EINT_MODE_INTERRUPT = 0x00,
EINT_MODE_EVENT = 0x04
} EINT_MODE_T;
/**
* @brief EINT Trigger enumeration
*/
typedef enum
{
EINT_TRIGGER_RISING = 0x08,
EINT_TRIGGER_FALLING = 0x0C,
EINT_TRIGGER_RISING_FALLING = 0x10
} EINT_TRIGGER_T;
typedef enum
{
EINT_LINENONE = 0x00000, //!<No interrupt selected >
EINT_LINE_0 = 0x00001, //!< External interrupt line 0
EINT_LINE_1 = 0x00002, //!< External interrupt line 1
EINT_LINE_2 = 0x00004, //!< External interrupt line 2
EINT_LINE_3 = 0x00008, //!< External interrupt line 3
EINT_LINE_4 = 0x00010, //!< External interrupt line 4
EINT_LINE_5 = 0x00020, //!< External interrupt line 5
EINT_LINE_6 = 0x00040, //!< External interrupt line 6
EINT_LINE_7 = 0x00080, //!< External interrupt line 7
EINT_LINE_8 = 0x00100, //!< External interrupt line 8
EINT_LINE_9 = 0x00200, //!< External interrupt line 9
EINT_LINE_10 = 0x00400, //!< External interrupt line 10
EINT_LINE_11 = 0x00800, //!< External interrupt line 11
EINT_LINE_12 = 0x01000, //!< External interrupt line 12
EINT_LINE_13 = 0x02000, //!< External interrupt line 13
EINT_LINE_14 = 0x04000, //!< External interrupt line 14
EINT_LINE_15 = 0x08000, //!< External interrupt line 15
EINT_LINE_16 = 0x10000, //!< External interrupt line 16 Connected to the PVD Output
EINT_LINE_17 = 0x20000, //!< External interrupt line 17 Connected to the RTC Alarm event
EINT_LINE_18 = 0x40000, //!< External interrupt line 18 Connected to the USB Device
} EINT_LINE_T;
/**@} end of group EINT_Enumerations*/
/** @addtogroup EINT_Structure Data Structure
@{
*/
/**
* @brief EINT Config structure definition
*/
typedef struct
{
uint32_t line;
EINT_MODE_T mode;
EINT_TRIGGER_T trigger;
uint8_t lineCmd;
} EINT_Config_T;
/**@} end of group EINT_Structure*/
/** @addtogroup EINT_Fuctions Fuctions
@{
*/
/** Reset and configuration */
void EINT_Reset(void);
void EINT_Config( EINT_Config_T* eintConfig);
void EINT_ConfigStructInit(EINT_Config_T* eintConfig);
/** Interrupt and flag */
void EINT_SelectSWInterrupt(uint32_t line);
uint8_t EINT_ReadStatusFlag(EINT_LINE_T line);
void EINT_ClearStatusFlag(uint32_t line);
uint8_t EINT_ReadIntFlag(EINT_LINE_T line);
void EINT_ClearIntFlag(uint32_t line);
/**@} end of group EINT_Fuctions*/
/**@} end of group EINT_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10XEINT_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h
+369
View File
@@ -0,0 +1,369 @@
/*!
* @file apm32f10x_emmc.h
*
* @brief This file contains all the functions prototypes for the EMMC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_EMMC_H
#define __APM32F10X_EMMC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup EMMC_Driver EMMC Driver
@{
*/
/** @addtogroup EMMC_Enumerations Enumerations
@{
*/
/**
* @brief EMMC NORSRAM_Bank
*/
typedef enum
{
EMMC_BANK1_NORSRAM_1 = 0x00000000,
EMMC_BANK1_NORSRAM_2 = 0x00000002,
EMMC_BANK1_NORSRAM_3 = 0x00000004,
EMMC_BANK1_NORSRAM_4 = 0x00000006
} EMMC_BANK1_NORSRAM_T;
/**
* @brief EMMC NAND and PC Card Bank
*/
typedef enum
{
EMMC_BANK2_NAND = 0x00000010,
EMMC_BANK3_NAND = 0x00000100,
EMMC_BANK4_PCCARD = 0x00001000
} EMMC_BANK_NAND_T;
/**
* @brief EMMC_Data_Address_Bus_Multiplexing
*/
typedef enum
{
EMMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000,
EMMC_DATA_ADDRESS_MUX_ENABLE = 0x00000002
} EMMC_DATA_ADDRESS_MUX_T;
/**
* @brief EMMC_Memory_Type
*/
typedef enum
{
EMMC_MEMORY_TYPE_SRAM = 0x00000000,
EMMC_MEMORY_TYPE_PSRAM = 0x00000004,
EMMC_MEMORY_TYPE_NOR = 0x00000008
} EMMC_MEMORY_TYPE_T;
/**
* @brief EMMC_Data_Width
*/
typedef enum
{
EMMC_MEMORY_DATA_WIDTH_8BIT = 0x00000000,
EMMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010
} EMMC_MEMORY_DATA_WIDTH_T;
/**
* @brief EMMC_Burst_Access_Mode
*/
typedef enum
{
EMMC_BURST_ACCESS_MODE_DISABLE = 0x00000000,
EMMC_BURST_ACCESS_MODE_ENABLE = 0x00000100
} EMMC_BURST_ACCESS_MODE_T;
/**
* @brief EMMC_AsynchronousWait
*/
typedef enum
{
EMMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000,
EMMC_ASYNCHRONOUS_WAIT_ENABLE = 0x00008000
} EMMC_ASYNCHRONOUS_WAIT_T;
/**
* @brief EMMC_Wait_Signal_Polarity
*/
typedef enum
{
EMMC_WAIT_SIGNAL_POLARITY_LOW = 0x00000000,
EMMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200
} EMMC_WAIT_SIGNAL_POLARITY_T;
/**
* @brief EMMC_Wrap_Mode
*/
typedef enum
{
EMMC_WRAP_MODE_DISABLE = 0x00000000,
EMMC_WRAP_MODE_ENABLE = 0x00000400
} EMMC_WRAP_MODE_T;
/**
* @brief EMMC_Wait_Timing
*/
typedef enum
{
EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000,
EMMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800
} EMMC_WAIT_SIGNAL_ACTIVE_T;
/**
* @brief EMMC_Write_Operation
*/
typedef enum
{
EMMC_WRITE_OPERATION_DISABLE = 0x00000000,
EMMC_WRITE_OPERATION_ENABLE = 0x00001000
} EMMC_WRITE_OPERATION_T;
/**
* @brief EMMC_Wait_Signal
*/
typedef enum
{
EMMC_WAITE_SIGNAL_DISABLE = 0x00000000,
EMMC_WAITE_SIGNAL_ENABLE = 0x00002000
} EMMC_WAITE_SIGNAL_T;
/**
* @brief EMMC_Extended_Mode
*/
typedef enum
{
EMMC_EXTENDEN_MODE_DISABLE = 0x00000000,
EMMC_EXTENDEN_MODE_ENABLE = 0x00004000
} EMMC_EXTENDEN_MODE_T;
/**
* @brief EMMC_Write_Burst
*/
typedef enum
{
EMMC_WRITE_BURST_DISABLE = 0x00000000,
EMMC_WRITE_BURST_ENABLE = 0x00080000
} EMMC_WRITE_BURST_T;
/**
* @brief EMMC_WAIT_FEATURE
*/
typedef enum
{
EMMC_WAIT_FEATURE_DISABLE = 0x00000000,
EMMC_WAIT_FEATURE_ENABLE = 0x00000002
} EMMC_WAIT_FEATURE_T;
/**
* @brief EMMC_ECC
*/
typedef enum
{
EMMC_ECC_DISABLE = 0x00000000,
EMMC_ECC_ENABLE = 0x00000040
} EMMC_ECC_T;
/**
* @brief EMMC_ECC_Page_Size
*/
typedef enum
{
EMMC_ECC_PAGE_SIZE_BYTE_256 = 0x00000000,
EMMC_ECC_PAGE_SIZE_BYTE_512 = 0x00020000,
EMMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000,
EMMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000,
EMMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000,
EMMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000
} EMMC_ECC_PAGE_SIZE_BYTE_T;
/**
* @brief EMMC_Access_Mode
*/
typedef enum
{
EMMC_ACCESS_MODE_A = 0x00000000,
EMMC_ACCESS_MODE_B = 0x10000000,
EMMC_ACCESS_MODE_C = 0x20000000,
EMMC_ACCESS_MODE_D = 0x30000000
} EMMC_ACCESS_MODE_T;
/**
* @brief EMMC_Interrupt_sources
*/
typedef enum
{
EMMC_INT_EDGE_RISING = 0x00000008,
EMMC_INT_LEVEL_HIGH = 0x00000010,
EMMC_INT_EDGE_FALLING = 0x00000020
} EMMC_INT_T;
/**
* @brief EMMC_Flags
*/
typedef enum
{
EMMC_FLAG_EDGE_RISING = 0x00000001,
EMMC_FLAG_LEVEL_HIGH = 0x00000002,
EMMC_FLAG_EDGE_FALLING = 0x00000004,
EMMC_FLAG_FIFO_EMPTY = 0x00000040
} EMMC_FLAG_T;
/**@} end of group EMMC_Enumerations*/
/** @addtogroup EMMC_Structure Data Structure
@{
*/
/**
* @brief Timing parameters for NOR/SRAM Banks
*/
typedef struct
{
uint32_t addressSetupTime;
uint32_t addressHodeTime;
uint32_t dataSetupTime;
uint32_t busTurnaroundTime;
uint32_t clockDivision;
uint32_t dataLatency;
EMMC_ACCESS_MODE_T accessMode;
} EMMC_NORSRAMTimingConfig_T;
/**
* @brief EMMC NOR/SRAM Config structure
*/
typedef struct
{
EMMC_BANK1_NORSRAM_T bank;
EMMC_DATA_ADDRESS_MUX_T dataAddressMux;
EMMC_MEMORY_TYPE_T memoryType;
EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth;
EMMC_BURST_ACCESS_MODE_T burstAcceesMode;
EMMC_ASYNCHRONOUS_WAIT_T asynchronousWait;
EMMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity;
EMMC_WRAP_MODE_T wrapMode;
EMMC_WAIT_SIGNAL_ACTIVE_T waitSignalActive;
EMMC_WRITE_OPERATION_T writeOperation;
EMMC_WAITE_SIGNAL_T waiteSignal;
EMMC_EXTENDEN_MODE_T extendedMode;
EMMC_WRITE_BURST_T writeBurst;
EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct;
EMMC_NORSRAMTimingConfig_T* writeTimingStruct;
} EMMC_NORSRAMConfig_T;
/**
* @brief Timing parameters for NAND and PCCARD Banks
*/
typedef struct
{
uint32_t setupTime;
uint32_t waitSetupTime;
uint32_t holdSetupTime;
uint32_t HiZSetupTime;
} EMMC_NAND_PCCARDTimingConfig_T;
/**
* @brief EMMC NAND Config structure
*/
typedef struct
{
EMMC_BANK_NAND_T bank;
EMMC_WAIT_FEATURE_T waitFeature;
EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth;
EMMC_ECC_T ECC;
EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
uint32_t TCLRSetupTime;
uint32_t TARSetupTime;
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
} EMMC_NANDConfig_T;
/**
* @brief EMMC PCCARD Config structure
*/
typedef struct
{
EMMC_WAIT_FEATURE_T waitFeature;
uint32_t TCLRSetupTime;
uint32_t TARSetupTime;
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
} EMMC_PCCARDConfig_T;
/**@} end of group EMMC_Structure*/
/** @addtogroup EMMC_Fuctions Fuctions
@{
*/
/** EMMC reset */
void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank);
void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
void EMMC_ResetPCCard(void);
/** EMMC Configuration */
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
/** EMMC bank control */
void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
void EMMC_EnableNAND(EMMC_BANK_NAND_T bank);
void EMMC_DisableNAND(EMMC_BANK_NAND_T bank);
void EMMC_EnablePCCARD(void);
void EMMC_DisablePCCARD(void);
void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank);
void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank);
uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank);
/** Interrupt and flag */
void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag);
void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag);
void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
/**@} end of group EMMC_Fuctions*/
/**@} end of group EMMC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_EMMC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h
+265
View File
@@ -0,0 +1,265 @@
/*!
* @file apm32f10x_fmc.h
*
* @brief This file contains all the functions prototypes for the FMC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_FMC_H
#define __APM32F10X_FMC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup FMC_Driver FMC Driver
@{
*/
/** @addtogroup FMC_Enumerations Enumerations
@{
*/
/**
* @brief Flash Latency
*/
typedef enum
{
FMC_LATENCY_0,
FMC_LATENCY_1,
FMC_LATENCY_2
} FMC_LATENCY_T;
/**
* @brief FMC Status
*/
typedef enum
{
FMC_STATUS_BUSY = 1, //!< flash busy
FMC_STATUS_ERROR_PG, //!< flash programming error
FMC_STATUS_ERROR_WRP, //!< flash write protection error
FMC_STATUS_COMPLETE, //!< flash operation complete
FMC_STATUS_TIMEOUT //!< flash time out
} FMC_STATUS_T;
/**
* @brief Option Bytes IWatchdog
*/
typedef enum
{
OB_IWDT_HARD = 0x0000,
OB_IWDT_SOTF = 0x0001
} OB_IWDT_T;
/**
* @brief Option Bytes nRST STOP
*/
typedef enum
{
OB_STOP_RST = 0x0000,
OB_STOP_NORST = 0x0002
} OB_STOP_T;
/**
* @brief Option Bytes nRST STDBY
*/
typedef enum
{
OB_STDBY_RST = 0x0000,
OB_STDBY_NORST = 0x0004
} OB_STDBY_T;
/**
* @brief FMC Interrupts
*/
typedef enum
{
FMC_INT_ERR,
FMC_INT_OC
} FMC_INT_T;
/**
* @brief FMC flag
*/
typedef enum
{
FMC_FLAG_BUSY = 0x00000001, //!< FMC Busy flag
FMC_FLAG_OC = 0x00000020, //!< FMC End of Operation flag
FMC_FLAG_PE = 0x00000004, //!< FMC Program error flag
FMC_FLAG_WPE = 0x00000010, //!< FMC Write protected error flag
FMC_FLAG_OBE = 0x10000001, //!< FMC Option Byte error flag
} FMC_FLAG_T;
/**@} end of group FMC_Enumerations*/
/** @addtogroup FMC_Macros Macros
@{
*/
/** Macros description */
/** Values for APM32 Low and Medium density devices */
#define FLASH_WRP_PAGE_0_3 ((uint32_t)BIT0) //!< Write protection of page 0 to 3
#define FLASH_WRP_PAGE_4_7 ((uint32_t)BIT1) //!< Write protection of page 4 to 7
#define FLASH_WRP_PAGE_8_11 ((uint32_t)BIT2) //!< Write protection of page 8 to 11
#define FLASH_WRP_PAGE_12_15 ((uint32_t)BIT3) //!< Write protection of page 12 to 15
#define FLASH_WRP_PAGE_16_19 ((uint32_t)BIT4) //!< Write protection of page 16 to 19
#define FLASH_WRP_PAGE_20_23 ((uint32_t)BIT5) //!< Write protection of page 20 to 23
#define FLASH_WRP_PAGE_24_27 ((uint32_t)BIT6) //!< Write protection of page 24 to 27
#define FLASH_WRP_PAGE_28_31 ((uint32_t)BIT7) //!< Write protection of page 28 to 31
/** Values for APM32 Medium-density devices */
#define FLASH_WRP_PAGE_32_35 ((uint32_t)BIT8) //!< Write protection of page 32 to 35
#define FLASH_WRP_PAGE_36_39 ((uint32_t)BIT9) //!< Write protection of page 36 to 39
#define FLASH_WRP_PAGE_40_43 ((uint32_t)BIT10) //!< Write protection of page 40 to 43
#define FLASH_WRP_PAGE_44_47 ((uint32_t)BIT11) //!< Write protection of page 44 to 47
#define FLASH_WRP_PAGE_48_51 ((uint32_t)BIT12) //!< Write protection of page 48 to 51
#define FLASH_WRP_PAGE_52_55 ((uint32_t)BIT13) //!< Write protection of page 52 to 55
#define FLASH_WRP_PAGE_56_59 ((uint32_t)BIT14) //!< Write protection of page 56 to 59
#define FLASH_WRP_PAGE_60_63 ((uint32_t)BIT15) //!< Write protection of page 60 to 63
#define FLASH_WRP_PAGE_64_67 ((uint32_t)BIT16) //!< Write protection of page 64 to 67
#define FLASH_WRP_PAGE_68_71 ((uint32_t)BIT17) //!< Write protection of page 68 to 71
#define FLASH_WRP_PAGE_72_75 ((uint32_t)BIT18) //!< Write protection of page 72 to 75
#define FLASH_WRP_PAGE_76_79 ((uint32_t)BIT19) //!< Write protection of page 76 to 79
#define FLASH_WRP_PAGE_80_83 ((uint32_t)BIT20) //!< Write protection of page 80 to 83
#define FLASH_WRP_PAGE_84_87 ((uint32_t)BIT21) //!< Write protection of page 84 to 87
#define FLASH_WRP_PAGE_88_91 ((uint32_t)BIT22) //!< Write protection of page 88 to 91
#define FLASH_WRP_PAGE_92_95 ((uint32_t)BIT23) //!< Write protection of page 92 to 95
#define FLASH_WRP_PAGE_96_99 ((uint32_t)BIT24) //!< Write protection of page 96 to 99
#define FLASH_WRP_PAGE_100_103 ((uint32_t)BIT25) //!< Write protection of page 100 to 103
#define FLASH_WRP_PAGE_104_107 ((uint32_t)BIT26) //!< Write protection of page 104 to 107
#define FLASH_WRP_PAGE_108_111 ((uint32_t)BIT27) //!< Write protection of page 108 to 111
#define FLASH_WRP_PAGE_112_115 ((uint32_t)BIT28) //!< Write protection of page 112 to 115
#define FLASH_WRP_PAGE_116_119 ((uint32_t)BIT29) //!< Write protection of page 116 to 119
#define FLASH_WRP_PAGE_120_123 ((uint32_t)BIT30) //!< Write protection of page 120 to 123
#define FLASH_WRP_PAGE_124_127 ((uint32_t)BIT31) //!< Write protection of page 124 to 127
/** Values only for APM32 High-density devices */
#define FLASH_WRP_PAGE_0_1 ((uint32_t)BIT0) //!< Write protection of page 0 to 1
#define FLASH_WRP_PAGE_2_3 ((uint32_t)BIT1) //!< Write protection of page 2 to 3
#define FLASH_WRP_PAGE_4_5 ((uint32_t)BIT2) //!< Write protection of page 4 to 5
#define FLASH_WRP_PAGE_6_7 ((uint32_t)BIT3) //!< Write protection of page 6 to 7
#define FLASH_WRP_PAGE_8_9 ((uint32_t)BIT4) //!< Write protection of page 8 to 9
#define FLASH_WRP_PAGE_10_11 ((uint32_t)BIT5) //!< Write protection of page 10 to 11
#define FLASH_WRP_PAGE_12_13 ((uint32_t)BIT6) //!< Write protection of page 12 to 13
#define FLASH_WRP_PAGE_14_15 ((uint32_t)BIT7) //!< Write protection of page 14 to 15
#define FLASH_WRP_PAGE_16_17 ((uint32_t)BIT8) //!< Write protection of page 16 to 17
#define FLASH_WRP_PAGE_18_19 ((uint32_t)BIT9) //!< Write protection of page 18 to 19
#define FLASH_WRP_PAGE_20_21 ((uint32_t)BIT10) //!< Write protection of page 20 to 21
#define FLASH_WRP_PAGE_22_23 ((uint32_t)BIT11) //!< Write protection of page 22 to 23
#define FLASH_WRP_PAGE_24_25 ((uint32_t)BIT12) //!< Write protection of page 24 to 25
#define FLASH_WRP_PAGE_26_27 ((uint32_t)BIT13) //!< Write protection of page 26 to 27
#define FLASH_WRP_PAGE_28_29 ((uint32_t)BIT14) //!< Write protection of page 28 to 29
#define FLASH_WRP_PAGE_30_31 ((uint32_t)BIT15) //!< Write protection of page 30 to 31
#define FLASH_WRP_PAGE_32_33 ((uint32_t)BIT16) //!< Write protection of page 32 to 33
#define FLASH_WRP_PAGE_34_35 ((uint32_t)BIT17) //!< Write protection of page 34 to 35
#define FLASH_WRP_PAGE_36_37 ((uint32_t)BIT18) //!< Write protection of page 36 to 37
#define FLASH_WRP_PAGE_38_39 ((uint32_t)BIT19) //!< Write protection of page 38 to 39
#define FLASH_WRP_PAGE_40_41 ((uint32_t)BIT20) //!< Write protection of page 40 to 41
#define FLASH_WRP_PAGE_42_43 ((uint32_t)BIT21) //!< Write protection of page 42 to 43
#define FLASH_WRP_PAGE_44_45 ((uint32_t)BIT22) //!< Write protection of page 44 to 45
#define FLASH_WRP_PAGE_46_47 ((uint32_t)BIT23) //!< Write protection of page 46 to 47
#define FLASH_WRP_PAGE_48_49 ((uint32_t)BIT24) //!< Write protection of page 48 to 49
#define FLASH_WRP_PAGE_50_51 ((uint32_t)BIT25) //!< Write protection of page 50 to 51
#define FLASH_WRP_PAGE_52_53 ((uint32_t)BIT26) //!< Write protection of page 52 to 53
#define FLASH_WRP_PAGE_54_55 ((uint32_t)BIT27) //!< Write protection of page 54 to 55
#define FLASH_WRP_PAGE_56_57 ((uint32_t)BIT28) //!< Write protection of page 56 to 57
#define FLASH_WRP_PAGE_58_59 ((uint32_t)BIT29) //!< Write protection of page 58 to 59
#define FLASH_WRP_PAGE_60_61 ((uint32_t)BIT30) //!< Write protection of page 60 to 61
#define FLASH_WRP_PAGE_62_127 ((uint32_t)BIT31) //!< Write protection of page 62 to 127
#define FMC_WRP_PAGE_ALL ((uint32_t)0xFFFFFFFF) //!< Write protection of page all */
/**@} end of group FMC_Macros*/
/** @addtogroup FMC_Structure Data Structure
@{
*/
/**
* @brief User Option byte config struct definition
*/
typedef struct
{
OB_IWDT_T iwdtSet;
OB_STOP_T stopSet;
OB_STDBY_T stdbySet;
} FMC_UserConfig_T;
/**@} end of group FMC_Structure*/
/** @addtogroup FMC_Fuctions Fuctions
@{
*/
/** Initialization and Configuration */
void FMC_ConfigLatency(FMC_LATENCY_T latency);
void FMC_EnableHalfCycleAccess(void);
void FMC_DisableHalfCycleAccess(void);
void FMC_EnablePrefetchBuffer(void);
void FMC_DisablePrefetchBuffer(void);
/** Lock management */
void FMC_Unlock(void);
void FMC_Lock(void);
/** Erase management */
FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr);
FMC_STATUS_T FMC_EraseAllPage(void);
FMC_STATUS_T FMC_EraseOptionBytes(void);
/** Read Write management */
FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data);
FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data);
FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data);
FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page);
FMC_STATUS_T FMC_EnableReadOutProtection(void);
FMC_STATUS_T FMC_DisableReadOutProtection(void);
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig);
uint32_t FMC_ReadUserOptionByte(void);
uint32_t FMC_ReadOptionByteWriteProtection(void);
uint8_t FMC_GetReadProtectionStatus(void);
uint8_t FMC_ReadPrefetchBufferStatus(void);
/** Interrupts and flags */
void FMC_EnableInterrupt(FMC_INT_T interrupt);
void FMC_DisableInterrupt(FMC_INT_T interrupt);
uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag);
void FMC_ClearStatusFlag(uint32_t flag);
/** Status management */
FMC_STATUS_T FMC_ReadStatus(void);
FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut);
/**@} end of group FMC_Fuctions*/
/**@} end of group FMC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_FMC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h
+261
View File
@@ -0,0 +1,261 @@
/*!
* @file apm32f10x_gpio.h
*
* @brief This file contains all the functions prototypes for the GPIO firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_GPIO_H
#define __APM32F10X_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup GPIO_Enumerations Enumerations
@{
*/
/**
* @brief GPIO Output Maximum frequency selection
*/
typedef enum
{
GPIO_SPEED_10MHz = 1,
GPIO_SPEED_20MHz,
GPIO_SPEED_50MHz
}GPIO_SPEED_T;
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_MODE_ANALOG = 0x0, //!< Analog mode
GPIO_MODE_IN_FLOATING = 0x04, //!< Floating input
GPIO_MODE_IN_PD = 0x28, //!< Input with pull-down
GPIO_MODE_IN_PU = 0x48, //!< Input with pull-up
GPIO_MODE_OUT_PP = 0x80, //!< General purpose output push-pull
GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain
GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull
GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain
}GPIO_MODE_T;
/**
* @brief Definition of the GPIO pins
*/
typedef enum
{
GPIO_PIN_0 = ((uint16_t)BIT0),
GPIO_PIN_1 = ((uint16_t)BIT1),
GPIO_PIN_2 = ((uint16_t)BIT2),
GPIO_PIN_3 = ((uint16_t)BIT3),
GPIO_PIN_4 = ((uint16_t)BIT4),
GPIO_PIN_5 = ((uint16_t)BIT5),
GPIO_PIN_6 = ((uint16_t)BIT6),
GPIO_PIN_7 = ((uint16_t)BIT7),
GPIO_PIN_8 = ((uint16_t)BIT8),
GPIO_PIN_9 = ((uint16_t)BIT9),
GPIO_PIN_10 = ((uint16_t)BIT10),
GPIO_PIN_11 = ((uint16_t)BIT11),
GPIO_PIN_12 = ((uint16_t)BIT12),
GPIO_PIN_13 = ((uint16_t)BIT13),
GPIO_PIN_14 = ((uint16_t)BIT14),
GPIO_PIN_15 = ((uint16_t)BIT15),
GPIO_PIN_ALL = ((uint32_t)0XFFFF),
} GPIO_PIN_T;
/**
* @brief GPIO remap type define
*/
typedef enum
{
GPIO_NO_REMAP_SPI1 = 0x00000010,
GPIO_REMAP_SPI1 = 0x00000011,
GPIO_NO_REMAP_I2C1 = 0x00000110,
GPIO_REMAP_I2C1 = 0x00000111,
GPIO_NO_REMAP_USART1 = 0x00000210,
GPIO_REMAP_USART1 = 0x00000211,
GPIO_NO_REMAP_USART2 = 0x00000310,
GPIO_REMAP_USART2 = 0x00000311,
GPIO_NO_REMAP_USART3 = 0x00000430,
GPIO_PARTIAL_REMAP_USART3 = 0x00000431,
GPIO_FULL_REMAP_USART3 = 0x00000433,
GPIO_NO_REMAP_TMR1 = 0x00000630,
GPIO_PARTIAL_REMAP_TMR1 = 0x00000631,
GPIO_FULL_REMAP_TMR1 = 0x00000633,
GPIO_NO_REMAP_TMR2 = 0x00000830,
GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831,
GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832,
GPIO_FULL_REMAP_TMR2 = 0x00000833,
GPIO_NO_REMAP_TMR3 = 0x00000A30,
GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32,
GPIO_FULL_REMAP_TMR3 = 0x00000A33,
GPIO_NO_REMAP_TMR4 = 0x00000C10,
GPIO_REMAP_TMR4 = 0x00000C11,
GPIO_NO_REMAP_CAN1 = 0x00000D30,
GPIO_REMAP1_CAN1 = 0x00000D32,
GPIO_REMAP2_CAN1 = 0x00000D33,
GPIO_NO_REMAP_PD01 = 0x00000F10,
GPIO_REMAP_PD01 = 0x00000F11,
GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010,
GPIO_REMAP_TMR5CH4_LSI = 0x00001011,
GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110,
GPIO_REMAP_ADC1_ETRGINJ = 0x00001111,
GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210,
GPIO_REMAP_ADC1_ETRGREG = 0x00001211,
GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310,
GPIO_REMAP_ADC2_ETRGINJ = 0x00001311,
GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410,
GPIO_REMAP_ADC2_ETRGREG = 0x00001411,
GPIO_NO_REMAP_CAN2 = 0x00001610,
GPIO_REMAP_CAN2 = 0x00001611,
GPIO_NO_REMAP_SWJ = 0x00001870,
GPIO_REMAP_SWJ_NOJTRST = 0x00001871,
GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872,
GPIO_REMAP_SWJ_DISABLE = 0x00001874,
GPIO_NO_REMAP_EMMC_NADV = 0x00010A10,
GPIO_REMAP_EMMC_NADV = 0x00010A11,
}GPIO_REMAP_T;
/**
* @brief gpio port source define
*/
typedef enum
{
GPIO_PORT_SOURCE_A,
GPIO_PORT_SOURCE_B,
GPIO_PORT_SOURCE_C,
GPIO_PORT_SOURCE_D,
GPIO_PORT_SOURCE_E,
GPIO_PORT_SOURCE_F,
GPIO_PORT_SOURCE_G,
}GPIO_PORT_SOURCE_T;
/**
* @brief gpio pin source define
*/
typedef enum
{
GPIO_PIN_SOURCE_0,
GPIO_PIN_SOURCE_1,
GPIO_PIN_SOURCE_2,
GPIO_PIN_SOURCE_3,
GPIO_PIN_SOURCE_4,
GPIO_PIN_SOURCE_5,
GPIO_PIN_SOURCE_6,
GPIO_PIN_SOURCE_7,
GPIO_PIN_SOURCE_8,
GPIO_PIN_SOURCE_9,
GPIO_PIN_SOURCE_10,
GPIO_PIN_SOURCE_11,
GPIO_PIN_SOURCE_12,
GPIO_PIN_SOURCE_13,
GPIO_PIN_SOURCE_14,
GPIO_PIN_SOURCE_15,
}GPIO_PIN_SOURCE_T;
/**@} end of group GPIO_Enumerations*/
/** @addtogroup GPIO_Structure Data Structure
@{
*/
/**
* @brief GPIO Config structure definition
*/
typedef struct
{
uint16_t pin;
GPIO_SPEED_T speed;
GPIO_MODE_T mode;
}GPIO_Config_T;
/**@} end of group GPIO_Structure*/
/** @addtogroup GPIO_Fuctions Fuctions
@{
*/
/** Reset and common Configuration */
void GPIO_Reset(GPIO_T* port);
void GPIO_AFIOReset(void);
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig);
/** Read */
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
uint16_t GPIO_ReadInputPort(GPIO_T* port);
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
uint16_t GPIO_ReadOutputPort(GPIO_T* port);
/** Write */
void GPIO_SetBit(GPIO_T* port, uint16_t pin);
void GPIO_ResetBit(GPIO_T* port, uint16_t pin);
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal);
/** GPIO Configuration */
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
void GPIO_EnableEventOutput(void);
void GPIO_DisableEventOutput(void);
void GPIO_ConfigPinRemap(GPIO_REMAP_T remap);
void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
/**@} end of group GPIO_Fuctions*/
/**@} end of group GPIO_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_GPIO_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h
+348
View File
@@ -0,0 +1,348 @@
/*!
* @file apm32f10x_i2c.h
*
* @brief This file contains all the functions prototypes for the I2C firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_I2C_H
#define __APM32F10X_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup I2C_Driver I2C Driver
@{
*/
/** @addtogroup I2C_Enumerations Enumerations
@{
*/
/**
* @brief I2C Mode
*/
typedef enum
{
I2C_MODE_I2C = 0x0000,
I2C_MODE_SMBUUSDEVICE = 0x0002,
I2C_MODE_SMBUSHOST = 0x000A
} I2C_MODE_T;
/**
* @brief I2C duty cycle in fast mode
*/
typedef enum
{
I2C_DUTYCYCLE_16_9 = 0x4000,
I2C_DUTYCYCLE_2 = 0xBFFF
} I2C_DUTYCYCLE_T;
/**
* @brief I2C acknowledgement
*/
typedef enum
{
I2C_ACK_DISABLE,
I2C_ACK_ENABLE
} I2C_ACK_T;
/**
* @brief I2C acknowledged address
*/
typedef enum
{
I2C_ACK_ADDRESS_7BIT = 0x4000,
I2C_ACK_ADDRESS_10BIT = 0xC000
} I2C_ACK_ADDRESS_T;
/**
* @brief I2C interrupts definition
*/
typedef enum
{
I2C_INT_BUF = 0x0400,
I2C_INT_EVT = 0x0200,
I2C_INT_ERR = 0x0100
} I2C_INT_T;
/**
* @brief I2C transfer direction
*/
typedef enum
{
I2C_DIRECTION_TX,
I2C_DIRECTION_RX
} I2C_DIRECTION_T;
/**
* @brief I2C Register
*/
typedef enum
{
I2C_REGISTER_CTRL1,
I2C_REGISTER_CTRL2,
I2C_REGISTER_SADDR1,
I2C_REGISTER_SADDR2,
I2C_REGISTER_DATA,
I2C_REGISTER_STS1,
I2C_REGISTER_STS2,
I2C_REGISTER_CLKCTRL,
I2C_REGISTER_RISETMAX,
I2C_REGISTER_SWITCH
} I2C_REGISTER_T;
/**
* @brief I2C NCAK position
*/
typedef enum
{
I2C_NACK_POSITION_NEXT,
I2C_NACK_POSITION_CURRENT
} I2C_NACK_POSITION_T;
/**
* @brief I2C SMBus alert pin level
*/
typedef enum
{
I2C_SMBUSALER_LOW,
I2C_SMBUSALER_HIGH
} I2C_SMBUSALER_T;
/**
* @brief I2C PEC position
*/
typedef enum
{
I2C_PEC_POSITION_NEXT,
I2C_PEC_POSITION_CURRENT
} I2C_PEC_POSITION_T;
/**
* @brief I2C Events
*/
typedef enum
{
/** I2C Master Events */
/** Event 5: Communication start event */
I2C_EVENT_MASTER_MODE_SELECT = 0x00030001, //!< BUSBSYFLG, MSFLG and STARTFLG flag
/**
* Event 6: 7-bit Address Acknowledge
* in case of master receiver
*/
I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = 0x00070082, //!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */
I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = 0x00030002, //!< BUSBSYFLG, MSFLG and ADDRFLG flags */
/**
* Event 9: Master has sent the first byte
* in 10-bit address mode
*/
I2C_EVENT_MASTER_MODE_ADDRESS10 = 0x00030008, //!< BUSBSYFLG, MSFLG and ADDR10FLG flags */
/** Master RECEIVER mode */
/** Event 7 */
I2C_EVENT_MASTER_BYTE_RECEIVED = 0x00030040, //!< BUSBSYFLG, MSFLG and RXBNEFLG flags */
/** Master TRANSMITTER mode */
/** Event 8 */
I2C_EVENT_MASTER_BYTE_TRANSMITTING = 0x00070080, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */
/** Event 8_2 */
I2C_EVENT_MASTER_BYTE_TRANSMITTED = 0x00070084, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */
/** EV1 (all the events below are variants of EV1) */
/** 1, Case of One Single Address managed by the slave */
I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = 0x00020002, //!< BUSBSYFLG and ADDRFLG flags */
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = 0x00060082, //!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */
/** 2, Case of Dual address managed by the slave */
I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = 0x00820000, //!< DUALF and BUSBSYFLG flags */
I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = 0x00860080, //!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */
/** 3, Case of General Call enabled for the slave */
I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = 0x00120000, //!< GENCALL and BUSBSYFLG flags */
/** Slave RECEIVER mode */
/** EV2 */
I2C_EVENT_SLAVE_BYTE_RECEIVED = 0x00020040, //!< BUSBSYFLG and RXBNEFLG flags */
/** EV4 */
I2C_EVENT_SLAVE_STOP_DETECTED = 0x00000010, //!< STOPFLG flag */
/** Slave TRANSMITTER mode */
/** EV3 */
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = 0x00060084, //!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */
I2C_EVENT_SLAVE_BYTE_TRANSMITTING = 0x00060080, //!< TRFLG, BUSBSYFLG and TXBEFLG flags */
/** EV3_2 */
I2C_EVENT_SLAVE_ACK_FAILURE = 0x00000400, //!< AEFLG flag */
} I2C_EVENT_T;
/**
* @brief I2C flags
*/
typedef enum
{
/** STS2 register flags */
I2C_FLAG_DUALADDR,
I2C_FLAG_SMMHADDR,
I2C_FLAG_SMBDADDR,
I2C_FLAG_GENCALL,
I2C_FLAG_TR,
I2C_FLAG_BUSBSY,
I2C_FLAG_MS,
/** STS1 register flags */
I2C_FLAG_SMBALT,
I2C_FLAG_TTE,
I2C_FLAG_PECE,
I2C_FLAG_OVRUR,
I2C_FLAG_AE,
I2C_FLAG_AL,
I2C_FLAG_BERR,
I2C_FLAG_TXBE,
I2C_FLAG_RXBNE,
I2C_FLAG_STOP,
I2C_FLAG_ADDR10,
I2C_FLAG_BTC,
I2C_FLAG_ADDR,
I2C_FLAG_START,
} I2C_FLAG_T;
/**
* @brief I2C interrupt
*/
typedef enum
{
I2C_INT_FLAG_SMBALT = 0x01008000,
I2C_INT_FLAG_TTE = 0x01004000,
I2C_INT_FLAG_PECE = 0x01001000,
I2C_INT_FLAG_OVRUR = 0x01000800,
I2C_INT_FLAG_AE = 0x01000400,
I2C_INT_FLAG_AL = 0x01000200,
I2C_INT_FLAG_BERR = 0x01000100,
I2C_INT_FLAG_TXBE = 0x06000080,
I2C_INT_FLAG_RXBNE = 0x06000040,
I2C_INT_FLAG_STOP = 0x02000010,
I2C_INT_FLAG_ADDR10 = 0x02000008,
I2C_INT_FLAG_BTC = 0x02000004,
I2C_INT_FLAG_ADDR = 0x02000002,
I2C_INT_FLAG_START = 0x02000001,
} I2C_INT_FLAG_T;
/**@} end of group I2C_Enumerations*/
/** @addtogroup I2C_Structure Data Structure
@{
*/
/**
* @brief I2C Config structure definition
*/
typedef struct
{
uint32_t clockSpeed;
I2C_MODE_T mode;
I2C_DUTYCYCLE_T dutyCycle;
uint16_t ownAddress1;
I2C_ACK_T ack;
I2C_ACK_ADDRESS_T ackAddress;
} I2C_Config_T;
/**@} end of group I2C_Structure*/
/** @addtogroup I2C_Fuctions Fuctions
@{
*/
/** I2C reset and configuration */
void I2C_Reset(I2C_T* i2c);
void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig);
void I2C_ConfigStructInit(I2C_Config_T* i2cConfig);
void I2C_Enable(I2C_T* i2c);
void I2C_Disable(I2C_T* i2c);
void I2C_EnableGenerateStart(I2C_T* i2c);
void I2C_DisableGenerateStart(I2C_T* i2c);
void I2C_EnableGenerateStop(I2C_T* i2c);
void I2C_DisableGenerateStop(I2C_T* i2c);
void I2C_EnableAcknowledge(I2C_T* i2c);
void I2C_DisableAcknowledge(I2C_T* i2c);
void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address);
void I2C_EnableDualAddress(I2C_T* i2c);
void I2C_DisableDualAddress(I2C_T* i2c);
void I2C_EnableGeneralCall(I2C_T* i2c);
void I2C_DisableGeneralCall(I2C_T* i2c);
/** Transmit Configuration */
void I2C_TxData(I2C_T* i2c, uint8_t data);
uint8_t I2C_RxData(I2C_T* i2c);
void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction);
uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister);
void I2C_EnableSoftwareReset(I2C_T* i2c);
void I2C_DisableSoftwareReset(I2C_T* i2c);
void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition);
void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState);
void I2C_EnablePECTransmit(I2C_T* i2c);
void I2C_DisablePECTransmit(I2C_T* i2c);
void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition);
void I2C_EnablePEC(I2C_T* i2c);
void I2C_DisablePEC(I2C_T* i2c);
uint8_t I2C_ReadPEC(I2C_T* i2c);
void I2C_EnableARP(I2C_T* i2c);
void I2C_DisableARP(I2C_T* i2c);
void I2C_EnableStretchClock(I2C_T* i2c);
void I2C_DisableStretchClock(I2C_T* i2c);
void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle);
/** DMA */
void I2C_EnableDMA(I2C_T* i2c);
void I2C_DisableDMA(I2C_T* i2c);
void I2C_EnableDMALastTransfer(I2C_T* i2c);
void I2C_DisableDMALastTransfer(I2C_T* i2c);
/** Interrupts and flags */
void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt);
void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt);
uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent);
uint32_t I2C_ReadLastEvent(I2C_T* i2c);
uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag);
/**@} end of group I2C_Fuctions*/
/**@} end of group I2C_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_I2C_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h
+122
View File
@@ -0,0 +1,122 @@
/*!
* @file apm32f10x_iwdt.h
*
* @brief This file contains all the functions prototypes for the IWDT firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_IWDT_H
#define __APM32F10X_IWDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup IWDT_Driver IWDT Driver
@{
*/
/** @addtogroup IWDT_Enumerations Enumerations
@{
*/
/**
* @brief IWDT KEYWORD define
*/
typedef enum
{
IWDT_KEYWORD_RELOAD = 0xAAAA,
IWDT_KEYWORD_ENABLE = 0xCCCC
}IWDT_KEYWORD_T;
/**
* @brief IWDT Write Access define
*/
typedef enum
{
IWDT_WRITEACCESS_ENABLE = 0x5555,
IWDT_WRITEACCESS_DISABLE = 0x0000
}IWDT_WRITEACCESS_T;
/**
* @brief IWDT Divider
*/
typedef enum
{
IWDT_DIVIDER_4 = 0x00,
IWDT_DIVIDER_8 = 0x01,
IWDT_DIVIDER_16 = 0x02,
IWDT_DIVIDER_32 = 0x03,
IWDT_DIVIDER_64 = 0x04,
IWDT_DIVIDER_128 = 0x05,
IWDT_DIVIDER_256 = 0x06
}IWDT_DIVIDER_T;
/**
* @brief IWDT Flag
*/
typedef enum
{
IWDT_FLAG_PSCU = BIT0,
IWDT_FLAG_CNTU = BIT1
}IWDT_FLAG_T;
/**@} end of group IWDT_Enumerations*/
/** @addtogroup IWDT_Fuctions Fuctions
@{
*/
/** Enable IWDT */
void IWDT_Enable(void);
/** Refresh IWDT */
void IWDT_Refresh(void);
/** Counter reload */
void IWDT_ConfigReload(uint16_t reload);
/** Divider */
void IWDT_ConfigDivider(uint8_t div);
/** Write Access */
void IWDT_EnableWriteAccess(void);
void IWDT_DisableWriteAccess(void);
/** flag */
uint8_t IWDT_ReadStatusFlag(uint16_t flag);
/**@} end of group IWDT_Fuctions*/
/**@} end of group IWDT_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_IWDT_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h
+118
View File
@@ -0,0 +1,118 @@
/*!
* @file apm32f10x_misc.h
*
* @brief This file provides all the miscellaneous firmware functions.
* Include NVIC,SystemTick and Power management.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_MISC_H
#define __APM32F10X_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup MISC_Driver MISC Driver
@{
*/
/** @addtogroup MISC_Enumerations Enumerations
@{
*/
/**
* @brief NVIC Vect table
*/
typedef enum
{
NVIC_VECT_TAB_RAM = 0x20000000,
NVIC_VECT_TAB_FLASH = 0x08000000,
}NVIC_VECT_TAB_T;
/**
* @brief system low power mode
*/
typedef enum
{
NVIC_LOWPOWER_SEVONPEND = 0x10,
NVIC_LOWPOWER_SLEEPDEEP = 0x04,
NVIC_LOWPOWER_SLEEPONEXIT = 0x02
}NVIC_LOWPOWER_T;
/**
* @brief nvic priority group
*/
typedef enum
{
NVIC_PRIORITY_GROUP_0 = 0x700, //!< 0 bits for pre-emption priority,4 bits for subpriority
NVIC_PRIORITY_GROUP_1 = 0x600, //!< 1 bits for pre-emption priority,3 bits for subpriority
NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority
NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority
NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority
}NVIC_PRIORITY_GROUP_T;
/**
* @brief SysTick Clock source
*/
typedef enum
{
SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
SYSTICK_CLK_SOURCE_HCLK = 0x01
}SYSTICK_CLK_SOURCE_T;
/**@} end of group MISC_Enumerations*/
/** @addtogroup MISC_Fuctions Fuctions
@{
*/
/** NVIC */
void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup);
void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority);
void NVIC_DisableIRQRequest(IRQn_Type irq);
/** Vector Table */
void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset);
/** Power */
void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
/** Systick */
void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource);
/**@} end of group MISC_Fuctions*/
/**@} end of group MISC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_MISC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h
+123
View File
@@ -0,0 +1,123 @@
/*!
* @file apm32f10x_pmu.h
*
* @brief This file contains all the functions prototypes for the PMU firmware library.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_PMU_H
#define __APM32F10X_PMU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup PMU_Driver PMU Driver
@{
*/
/** @addtogroup PMU_Enumerations Enumerations
@{
*/
/**
* @brief PMU PVD detection level
*/
typedef enum
{
PMU_PVD_LEVEL_2V2 = 0x00, //!< PVD detection level set to 2.2V
PMU_PVD_LEVEL_2V3 = 0x01, //!< PVD detection level set to 2.3V
PMU_PVD_LEVEL_2V4 = 0x02, //!< PVD detection level set to 2.4V
PMU_PVD_LEVEL_2V5 = 0x03, //!< PVD detection level set to 2.5V
PMU_PVD_LEVEL_2V6 = 0x04, //!< PVD detection level set to 2.6V
PMU_PVD_LEVEL_2V7 = 0x05, //!< PVD detection level set to 2.7V
PMU_PVD_LEVEL_2V8 = 0x06, //!< PVD detection level set to 2.8V
PMU_PVD_LEVEL_2V9 = 0x07, //!< PVD detection level set to 2.9V
} PMU_PVD_LEVEL_T;
/**
* @brief PMU Regulator state in STOP mode
*/
typedef enum
{
PMU_REGULATOR_ON = 0x00,
PMU_REGULATOR_LOWPOWER = 0x01
} PMU_REGULATOR_T;
/**
* @brief PMU STOP mode entry
*/
typedef enum
{
PMU_STOP_ENTRY_WFI = 0x01,
PMU_STOP_ENTRY_WFE = 0x02
} PMU_STOP_ENTRY_T;
/**
* @brief PMU Flag
*/
typedef enum
{
PMU_FLAG_WUE,
PMU_FLAG_SB,
PMU_FLAG_PVDO
} PMU_FLAG_T;
/**@} end of group PMU_Enumerations*/
/** @addtogroup PMU_Fuctions Fuctions
@{
*/
/** PMU Reset */
void PMU_Reset(void);
/** Configuration and Operation modes */
void PMU_EnableBackupAccess(void);
void PMU_DisableBackupAccess(void);
void PMU_EnablePVD(void);
void PMU_DisablePVD(void);
void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level);
void PMU_EnableWakeUpPin(void);
void PMU_DisableWakeUpPin(void);
void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry);
void PMU_EnterSTANDBYMode(void);
/** flags */
uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag);
void PMU_ClearStatusFlag(PMU_FLAG_T flag);
/**@} end of group PMU_Fuctions*/
/**@} end of group PMU_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_PMU_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h
+351
View File
@@ -0,0 +1,351 @@
/*!
* @file apm32f10x_qspi.h
*
* @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_QSPI_H
#define __APM32F10X_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup QSPI_Driver QSPI Driver
@{
*/
/** @addtogroup QSPI_Enumerations Enumerations
@{
*/
/**
* @brief Frame format
*/
typedef enum
{
QSPI_FRF_STANDARD, //!< Standard mode
QSPI_FRF_DUAL, //!< Dual SPI
QSPI_FRF_QUAD //!< QUAD SPI
}QSPI_FRF_T;
/**
* @brief Transmission mode
*/
typedef enum
{
QSPI_TRANS_MODE_TX_RX, //!< TX and RX mode
QSPI_TRANS_MODE_TX, //!< TX mode only
QSPI_TRANS_MODE_RX, //!< RX mode only
QSPI_TRANS_MODE_EEPROM_READ //!< EEPROM read mode
}QSPI_TRANS_MODE_T;
/**
* @brief Clock polarity
*/
typedef enum
{
QSPI_CLKPOL_LOW,
QSPI_CLKPOL_HIGH
}QSPI_CLKPOL_T;
/**
* @brief Clock phase
*/
typedef enum
{
QSPI_CLKPHA_1EDGE,
QSPI_CLKPHA_2EDGE
}QSPI_CLKPHA_T;
/**
* @brief Data format size
*/
typedef enum
{
QSPI_DFS_4BIT = 3,
QSPI_DFS_5BIT,
QSPI_DFS_6BIT,
QSPI_DFS_7BIT,
QSPI_DFS_8BIT,
QSPI_DFS_9BIT,
QSPI_DFS_10BIT,
QSPI_DFS_11BIT,
QSPI_DFS_12BIT,
QSPI_DFS_13BIT,
QSPI_DFS_14BIT,
QSPI_DFS_15BIT,
QSPI_DFS_16BIT,
QSPI_DFS_17BIT,
QSPI_DFS_18BIT,
QSPI_DFS_19BIT,
QSPI_DFS_20BIT,
QSPI_DFS_21BIT,
QSPI_DFS_22BIT,
QSPI_DFS_23BIT,
QSPI_DFS_24BIT,
QSPI_DFS_25BIT,
QSPI_DFS_26BIT,
QSPI_DFS_27BIT,
QSPI_DFS_28BIT,
QSPI_DFS_29BIT,
QSPI_DFS_30BIT,
QSPI_DFS_31BIT,
QSPI_DFS_32BIT
}QSPI_DFS_T;
/**
* @brief QSPI flag
*/
typedef enum
{
QSPI_FLAG_BUSY = BIT0, //!< Busy flag
QSPI_FLAG_TFNF = BIT1, //!< TX FIFO not full flag
QSPI_FLAG_TFE = BIT2, //!< TX FIFO empty flag
QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag
QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag
QSPI_FLAG_DCE = BIT6 //!< Data collision error
}QSPI_FLAG_T;
/**
* @brief QSPI interrupt source
*/
typedef enum
{
QSPI_INT_TFE = BIT0, //!< TX FIFO empty interrupt
QSPI_INT_TFO = BIT1, //!< TX FIFO overflow interrupt
QSPI_INT_RFU = BIT2, //!< RX FIFO underflow interrupt
QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt
QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt
QSPI_INT_MST = BIT5 //!< Master interrupt
}QSPI_INT_T;
/**
* @brief QSPI interrupt flag
*/
typedef enum
{
QSPI_INT_FLAG_TFE = BIT0, //!< TX FIFO empty interrupt flag
QSPI_INT_FLAG_TFO = BIT1, //!< TX FIFO overflow interrupt flag
QSPI_INT_FLAG_RFU = BIT2, //!< RX FIFO underflow interrupt flag
QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag
QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag
QSPI_INT_FLAG_MST = BIT5 //!< Master interrupt flag
}QSPI_INT_FLAG_T;
/**
* @brief Reception sample edge
*/
typedef enum
{
QSPI_RSE_RISING,
QSPI_RSE_FALLING
}QSPI_RSE_T;
/**
* @brief Instruction length
*/
typedef enum
{
QSPI_INST_LEN_0,
QSPI_INST_LEN_4BIT,
QSPI_INST_LEN_8BIT,
QSPI_INST_LEN_16BIT
}QSPI_INST_LEN_T;
/**
* @brief QSPI address length
*/
typedef enum
{
QSPI_ADDR_LEN_0,
QSPI_ADDR_LEN_4BIT,
QSPI_ADDR_LEN_8BIT,
QSPI_ADDR_LEN_12BIT,
QSPI_ADDR_LEN_16BIT,
QSPI_ADDR_LEN_20BIT,
QSPI_ADDR_LEN_24BIT,
QSPI_ADDR_LEN_28BIT,
QSPI_ADDR_LEN_32BIT,
QSPI_ADDR_LEN_36BIT,
QSPI_ADDR_LEN_40BIT,
QSPI_ADDR_LEN_44BIT,
QSPI_ADDR_LEN_48BIT,
QSPI_ADDR_LEN_52BIT,
QSPI_ADDR_LEN_56BIT,
QSPI_ADDR_LEN_60BIT
}QSPI_ADDR_LEN_T;
/**
* @brief Instruction and address transmission mode
*/
typedef enum
{
QSPI_INST_ADDR_TYPE_STANDARD,
QSPI_INST_TYPE_STANDARD,
QSPI_INST_ADDR_TYPE_FRF
}QSPI_INST_ADDR_TYPE_T;
/**
* @brief Slave Select Toggle
*/
typedef enum
{
QSPI_SST_DISABLE,
QSPI_SST_ENABLE
}QSPI_SST_T;
/**@} end of group QSPI_Enumerations*/
/** @addtogroup QSPI_Macros Macros
@{
*/
/** CTRL1 register reset value */
#define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007)
/** CTRL2 register reset value */
#define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00)
/** SSIEN register reset value */
#define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00)
/** SLAEN register reset value */
#define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00)
/** BR register reset value */
#define QSPI_BR_RESET_VALUE ((uint32_t)0x00)
/** TFTL register reset value */
#define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00)
/** RFTL register reset value */
#define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00)
/** TFL register reset value */
#define QSPI_TFL_RESET_VALUE ((uint32_t)0x00)
/** RFL register reset value */
#define QSPI_RFL_RESET_VALUE ((uint32_t)0x00)
/** STS register reset value */
#define QSPI_STS_RESET_VALUE ((uint32_t)0x06)
/** INTEN register reset value */
#define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F)
/** RSD register reset value */
#define QSPI_RSD_RESET_VALUE ((uint32_t)0x00)
/** CTRL3 register reset value */
#define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200)
/** IOSW register reset value */
#define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00)
/**@} end of group QSPI_Macros*/
/** @addtogroup QSPI_Structure Data Structure
@{
*/
typedef struct
{
QSPI_SST_T selectSlaveToggle; //!< Slave Select Toggle
QSPI_FRF_T frameFormat; //!< Frame format
uint16_t clockDiv; //!< Clock divider
QSPI_CLKPOL_T clockPolarity; //!< Clock polarity
QSPI_CLKPHA_T clockPhase; //!< Clock phase
QSPI_DFS_T dataFrameSize; //!< Data frame size
}QSPI_Config_T;
/**@} end of group QSPI_Structure*/
/** @addtogroup QSPI_Fuctions Fuctions
@{
*/
/** Reset */
void QSPI_Reset(void);
/** Configuration */
void QSPI_Config(QSPI_Config_T *qspiConfig);
void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig);
/** Data frame size, frame number, frame format */
void QSPI_ConfigFrameNum(uint16_t num);
void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs);
void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat);
/** Disable or Enable */
void QSPI_Enable(void);
void QSPI_Disable(void);
/** TX and RX FIFO */
uint8_t QSPI_ReadTxFifoDataNum(void);
uint8_t QSPI_ReadRxFifoDataNum(void);
void QSPI_ConfigRxFifoThreshold(uint8_t threshold);
void QSPI_ConfigTxFifoThreshold(uint8_t threshold);
void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold);
/** RX Sample */
void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse);
void QSPI_ConfigRxSampleDelay(uint8_t delay);
/** Clock stretch */
void QSPI_EnableClockStretch(void);
void QSPI_DisableClockStretch(void);
/** Instruction, address, Wait cycle */
void QSPI_ConfigInstLen(QSPI_INST_LEN_T len);
void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len);
void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type);
void QSPI_ConfigWaitCycle(uint8_t cycle);
/** IO */
void QSPI_OpenIO(void);
void QSPI_CloseIO(void);
/** Transmission mode */
void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode);
/** Rx and Tx data */
uint32_t QSPI_RxData(void);
void QSPI_TxData(uint32_t data);
/** Slave */
void QSPI_EnableSlave(void);
void QSPI_DisableSlave(void);
/** Interrupt */
void QSPI_EnableInterrupt(uint32_t interrupt);
void QSPI_DisableInterrupt(uint32_t interrupt);
/** Flag */
uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag);
void QSPI_ClearStatusFlag(void);
uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag);
void QSPI_ClearIntFlag(uint32_t flag);
/**@} end of group QSPI_Fuctions*/
/**@} end of group QSPI_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_QSPI_H_ */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h
+379
View File
@@ -0,0 +1,379 @@
/*!
* @file apm32f10x_rcm.h
*
* @brief This file contains all the functions prototypes for the RCM firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_RCM_H
#define __APM32F10X_RCM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup RCM_Driver RCM Driver
@{
*/
/** @addtogroup RCM_Enumerations Enumerations
@{
*/
/**
* @brief HSE state
*/
typedef enum
{
RCM_HSE_CLOSE,
RCM_HSE_OPEN,
RCM_HSE_BYPASS
} RCM_HSE_T;
/**
* @brief PLL multiplication factor
*/
typedef enum
{
RCM_PLLMF_2,
RCM_PLLMF_3,
RCM_PLLMF_4,
RCM_PLLMF_5,
RCM_PLLMF_6,
RCM_PLLMF_7,
RCM_PLLMF_8,
RCM_PLLMF_9,
RCM_PLLMF_10,
RCM_PLLMF_11,
RCM_PLLMF_12,
RCM_PLLMF_13,
RCM_PLLMF_14,
RCM_PLLMF_15,
RCM_PLLMF_16
} RCM_PLLMF_T;
/**
* @brief System clock select
*/
typedef enum
{
RCM_SYSCLK_SEL_HSI,
RCM_SYSCLK_SEL_HSE,
RCM_SYSCLK_SEL_PLL
} RCM_SYSCLK_SEL_T;
/**
* @brief AHB divider Number
*/
typedef enum
{
RCM_AHB_DIV_1 = 7,
RCM_AHB_DIV_2,
RCM_AHB_DIV_4,
RCM_AHB_DIV_8,
RCM_AHB_DIV_16,
RCM_AHB_DIV_64,
RCM_AHB_DIV_128,
RCM_AHB_DIV_256,
RCM_AHB_DIV_512
} RCM_AHB_DIV_T;
/**
* @brief APB divider Number
*/
typedef enum
{
RCM_APB_DIV_1 = 3,
RCM_APB_DIV_2,
RCM_APB_DIV_4,
RCM_APB_DIV_8,
RCM_APB_DIV_16
} RCM_APB_DIV_T;
/**
* @brief USB divider Number
*/
typedef enum
{
RCM_USB_DIV_1_5,
RCM_USB_DIV_1,
RCM_USB_DIV_2,
RCM_USB_DIV_2_5 //!< (Only for High-density devices for APM32F103xx)
} RCM_USB_DIV_T;
/**
* @brief FPU divider Number
*/
typedef enum
{
RCM_FPU_DIV_1,
RCM_FPU_DIV_2
} RCM_FPU_DIV_T;
/**
* @brief ADC divider Number
*/
typedef enum
{
RCM_PCLK2_DIV_2,
RCM_PCLK2_DIV_4,
RCM_PCLK2_DIV_6,
RCM_PCLK2_DIV_8
} RCM_PCLK2_DIV_T;
/**
* @brief LSE State
*/
typedef enum
{
RCM_LSE_CLOSE,
RCM_LSE_OPEN,
RCM_LSE_BYPASS
} RCM_LSE_T;
/**
* @brief RTC clock select
*/
typedef enum
{
RCM_RTCCLK_LSE = 1,
RCM_RTCCLK_LSI,
RCM_RTCCLK_HSE_DIV_128
} RCM_RTCCLK_T;
/**
* @brief Clock output control
*/
typedef enum
{
RCM_MCOCLK_NO_CLOCK = 3,
RCM_MCOCLK_SYSCLK,
RCM_MCOCLK_HSI,
RCM_MCOCLK_HSE,
RCM_MCOCLK_PLLCLK_DIV_2
} RCM_MCOCLK_T;
/**
* @brief PLL entry clock select
*/
typedef enum
{
RCM_PLLSEL_HSI_DIV_2 = 0,
RCM_PLLSEL_HSE = 1,
RCM_PLLSEL_HSE_DIV2 = 3,
} RCM_PLLSEL_T;
/**
* @brief RCM Interrupt Source
*/
typedef enum
{
RCM_INT_LSIRDY = BIT0, //!< LSI ready interrupt
RCM_INT_LSERDY = BIT1, //!< LSE ready interrupt
RCM_INT_HSIRDY = BIT2, //!< HSI ready interrupt
RCM_INT_HSERDY = BIT3, //!< HSE ready interrupt
RCM_INT_PLLRDY = BIT4, //!< PLL ready interrupt
RCM_INT_CSS = BIT7 //!< Clock security system interrupt
} RCM_INT_T;
/**
* @brief AHB peripheral
*/
typedef enum
{
RCM_AHB_PERIPH_DMA1 = BIT0,
RCM_AHB_PERIPH_DMA2 = BIT1,
RCM_AHB_PERIPH_SRAM = BIT2,
RCM_AHB_PERIPH_FPU = BIT3,
RCM_AHB_PERIPH_FMC = BIT4,
RCM_AHB_PERIPH_QSPI = BIT5,
RCM_AHB_PERIPH_CRC = BIT6,
RCM_AHB_PERIPH_EMMC = BIT8,
RCM_AHB_PERIPH_SDIO = BIT10
} RCM_AHB_PERIPH_T;
/**
* @brief AHB2 peripheral
*/
typedef enum
{
RCM_APB2_PERIPH_AFIO = BIT0,
RCM_APB2_PERIPH_GPIOA = BIT2,
RCM_APB2_PERIPH_GPIOB = BIT3,
RCM_APB2_PERIPH_GPIOC = BIT4,
RCM_APB2_PERIPH_GPIOD = BIT5,
RCM_APB2_PERIPH_GPIOE = BIT6,
RCM_APB2_PERIPH_GPIOF = BIT7,
RCM_APB2_PERIPH_GPIOG = BIT8,
RCM_APB2_PERIPH_ADC1 = BIT9,
RCM_APB2_PERIPH_ADC2 = BIT10,
RCM_APB2_PERIPH_TMR1 = BIT11,
RCM_APB2_PERIPH_SPI1 = BIT12,
RCM_APB2_PERIPH_TMR8 = BIT13,
RCM_APB2_PERIPH_USART1 = BIT14,
RCM_APB2_PERIPH_ADC3 = BIT15
} RCM_APB2_PERIPH_T;
/**
* @brief AHB1 peripheral
*/
typedef enum
{
RCM_APB1_PERIPH_TMR2 = BIT0,
RCM_APB1_PERIPH_TMR3 = BIT1,
RCM_APB1_PERIPH_TMR4 = BIT2,
RCM_APB1_PERIPH_TMR5 = BIT3,
RCM_APB1_PERIPH_TMR6 = BIT4,
RCM_APB1_PERIPH_TMR7 = BIT5,
RCM_APB1_PERIPH_WWDT = BIT11,
RCM_APB1_PERIPH_SPI2 = BIT14,
RCM_APB1_PERIPH_SPI3 = BIT15,
RCM_APB1_PERIPH_USART2 = BIT17,
RCM_APB1_PERIPH_USART3 = BIT18,
RCM_APB1_PERIPH_UART4 = BIT19,
RCM_APB1_PERIPH_UART5 = BIT20,
RCM_APB1_PERIPH_I2C1 = BIT21,
RCM_APB1_PERIPH_I2C2 = BIT22,
RCM_APB1_PERIPH_USB = BIT23,
RCM_APB1_PERIPH_CAN1 = BIT25,
RCM_APB1_PERIPH_CAN2 = BIT26,
RCM_APB1_PERIPH_BAKR = BIT27,
RCM_APB1_PERIPH_PMU = BIT28,
RCM_APB1_PERIPH_DAC = BIT29
} RCM_APB1_PERIPH_T;
/**
* @brief RCM FLAG define
*/
typedef enum
{
RCM_FLAG_HSIRDY = 0x001, //!< HSI Ready Flag
RCM_FLAG_HSERDY = 0x011, //!< HSE Ready Flag
RCM_FLAG_PLLRDY = 0x019, //!< PLL Ready Flag
RCM_FLAG_LSERDY = 0x101, //!< LSE Ready Flag
RCM_FLAG_LSIRDY = 0x201, //!< LSI Ready Flag
RCM_FLAG_PINRST = 0x21A, //!< PIN reset flag
RCM_FLAG_PORRST = 0x21B, //!< POR/PDR reset flag
RCM_FLAG_SWRST = 0x21C, //!< Software reset flag
RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag
RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag
RCM_FLAG_LPRRST = 0x21F //!< Low-power reset flag
} RCM_FLAG_T;
/**@} end of group RCM_Enumerations*/
/** @addtogroup RCM_Fuctions Fuctions
@{
*/
/** Function description */
/** RCM Reset */
void RCM_Reset(void);
/** HSE clock */
void RCM_ConfigHSE(RCM_HSE_T state);
uint8_t RCM_WaitHSEReady(void);
/** HSI clock */
void RCM_ConfigHSITrim(uint8_t HSITrim);
void RCM_EnableHSI(void);
void RCM_DisableHSI(void);
/** LSE and LSI clock */
void RCM_ConfigLSE(RCM_LSE_T state);
void RCM_EnableLSI(void);
void RCM_DisableLSI(void);
/** PLL clock */
void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf);
void RCM_EnablePLL(void);
void RCM_DisablePLL(void);
/** Clock Security System */
void RCM_EnableCSS(void);
void RCM_DisableCSS(void);
void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock);
void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect);
RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void);
/** Config clock prescaler of AHB, APB1, APB2, USB and ADC */
void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv);
void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div);
void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div);
void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv);
void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv);
void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv);
/** RTC clock */
void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect);
void RCM_EnableRTCCLK(void);
void RCM_DisableRTCCLK(void);
/** Reads the clock frequency */
uint32_t RCM_ReadSYSCLKFreq(void);
uint32_t RCM_ReadHCLKFreq(void);
void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
uint32_t RCM_ReadADCCLKFreq(void);
/** Enable or disable Periph Clock */
void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph);
void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph);
void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph);
void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph);
void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph);
void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph);
/** Enable or disable Periph Reset */
void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph);
void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph);
void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph);
void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph);
/** Backup domain reset */
void RCM_EnableBackupReset(void);
void RCM_DisableBackupReset(void);
/** Interrupts and flags */
void RCM_EnableInterrupt(uint32_t interrupt);
void RCM_DisableInterrupt(uint32_t interrupt);
uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag);
void RCM_ClearStatusFlag(void);
uint8_t RCM_ReadIntFlag(RCM_INT_T flag);
void RCM_ClearIntFlag(uint32_t flag);
/**@} end of group RCM_Fuctions*/
/**@} end of group RCM_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_RCM_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h
+99
View File
@@ -0,0 +1,99 @@
/*!
* @file apm32f10x_rtc.h
*
* @brief This file contains all the functions prototypes for the RTC firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_RTC_H
#define __APM32F10X_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup RTC_Driver RTC Driver
@{
*/
/** @addtogroup RTC_Enumerations Enumerations
@{
*/
typedef enum
{
RTC_FLAG_OC = 0x0020, //!< RTC Operation Complete flag
RTC_FLAG_RSYNC = 0x0008, //!< Registers Synchronized flag
RTC_FLAG_OVR = 0x0004, //!< Overflow flag
RTC_FLAG_ALR = 0x0002, //!< Alarm flag
RTC_FLAG_SEC = 0x0001 //!< Second flag
} RTC_FLAG_T;
typedef enum
{
RTC_INT_OVR = 0x0004, //!< Overflow interrupt
RTC_INT_ALR = 0x0002, //!< Alarm interrupt
RTC_INT_SEC = 0x0001 //!< Second interrupt
} RTC_INT_T;
/**@} end of group RTC_Enumerations*/
/** @addtogroup RTC_Fuctions Fuctions
@{
*/
/** Operation modes */
void RTC_EnableConfigMode(void);
void RTC_DisableConfigMode(void);
/** Configuration */
uint32_t RTC_ReadCounter(void);
void RTC_ConfigCounter(uint32_t value);
void RTC_ConfigPrescaler(uint32_t value);
void RTC_ConfigAlarm(uint32_t value);
uint32_t RTC_ReadDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchor(void);
/** Interrupts and flags */
void RTC_EnableInterrupt(uint16_t interrupt);
void RTC_DisableInterrupt(uint16_t interrupt);
uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag);
void RTC_ClearStatusFlag(uint16_t flag);
uint8_t RTC_ReadIntFlag(RTC_INT_T flag);
void RTC_ClearIntFlag(uint16_t flag);
/**@} end of group RTC_Fuctions*/
/**@} end of group RTC_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_RTC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h
+325
View File
@@ -0,0 +1,325 @@
/*!
* @file apm32f10x_sci2c.h
*
* @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_SCI2C_H
#define __APM32F10X_SCI2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SCI2C_Driver SCI2C Driver
@{
*/
/** @addtogroup SCI2C_Enumerations Enumerations
@{
*/
/**
* @brief SCI2C speed enumeration
*/
typedef enum
{
SCI2C_SPEED_STANDARD = 1,
SCI2C_SPEED_FAST,
SCI2C_SPEED_HIGH
}SCI2C_SPEED_T;
/**
* @brief Address mode
*/
typedef enum
{
SCI2C_ADDR_MODE_7BIT,
SCI2C_ADDR_MODE_10BIT
}SCI2C_ADDR_MODE_T;
/**
* @brief SCI2C mode enumeration
*/
typedef enum
{
SCI2C_MODE_MASTER,
SCI2C_MODE_SLAVE
}SCI2C_MODE_T;
/**
* @brief Restart enable or disable
*/
typedef enum
{
SCI2C_RESTART_DISABLE,
SCI2C_RESTART_ENABLE
}SCI2C_RESTART_T;
/**
* @brief Enable or disable generate stop condition
*/
typedef enum
{
SCI2C_STOP_DISABLE,
SCI2C_STOP_ENABLE
}SCI2C_STOP_T;
/**
* @brief Data direction
*/
typedef enum
{
SCI2C_DATA_DIR_WRITE,
SCI2C_DATA_DIR_READ,
}SCI2C_DATA_DIR_T;
/**
* @brief SCI2C interrupt
*/
typedef enum
{
SCI2C_INT_RFU = BIT0, //!< Rx FIFO underflow interrupt
SCI2C_INT_RFO = BIT1, //!< Rx FIFO onverflow interrupt
SCI2C_INT_RFF = BIT2, //!< Rx FIFO full interrupt
SCI2C_INT_TFO = BIT3, //!< Tx FIFO onverflow interrupt
SCI2C_INT_TFE = BIT4, //!< Tx FIFO empty interrupt
SCI2C_INT_RR = BIT5, //!< Read request interrupt
SCI2C_INT_TA = BIT6, //!< Tx abort interrupt
SCI2C_INT_RD = BIT7, //!< Read done interrupt
SCI2C_INT_ACT = BIT8, //!< Activity interrupt
SCI2C_INT_STPD = BIT9, //!< Stop detect interrupt
SCI2C_INT_STAD = BIT10, //!< Start detect interrupt
SCI2C_INT_GC = BIT11, //!< Gernal call interrupt
SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt
SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt
SCI2C_INT_ALL = BIT15 //!< All interrupt
}SCI2C_INT_T;
/**
* @brief Flag enumeration
*/
typedef enum
{
SCI2C_FLAG_ACT = BIT0, //!< Activity flag
SCI2C_FLAG_TFNF = BIT1, //!< Tx FIFO not full flag
SCI2C_FLAG_TFE = BIT2, //!< Tx FIFO empty flag
SCI2C_FLAG_RFNE = BIT3, //!< Rx FIFO not empty flag
SCI2C_FLAG_RFF = BIT4, //!< Rx FIFO full flag
SCI2C_FLAG_MA = BIT5, //!< Master activity flag
SCI2C_FLAG_SA = BIT6, //!< Slave activity flag
SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag
SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag
SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag
}SCI2C_FLAG_T;
/**
* @brief Tx abort source
*/
typedef enum
{
SCI2C_TAS_AD7NA = BIT0, //!< 7 bit address mode NACK
SCI2C_TAS_AD10FBNA = BIT1, //!< 10 bit address mode first byte NACK
SCI2C_TAS_AD10SBNA = BIT2, //!< 10 bit address mode second byte NACK
SCI2C_TAS_TDNA = BIT3, //!< Tx data NACK
SCI2C_TAS_GCNA = BIT4, //!< Gernal call NACK
SCI2C_TAS_GCR = BIT5, //!< Gernal call read
SCI2C_TAS_HSAD = BIT6, //!< High speed ack detected
SCI2C_TAS_SNR = BIT7, //!< Start byte no restart
SCI2C_TAS_RNR10B = BIT8, //!< Read 10bit address mode when restart disable
SCI2C_TAS_MSTDIS = BIT9, //!< Master disable
SCI2C_TAS_ARBLOST = BIT10, //!< Arbitration lost
SCI2C_TAS_LFTF = BIT11, //!< Slave flush tx FIFO
SCI2C_TAS_SAL = BIT12, //!< Slave arbitration lost
SCI2C_TAS_SRI = BIT13, //!< Slave read done
SCI2C_TAS_USRARB = BIT14, //!< User abort
SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter
}SCI2C_TAS_T;
/**
* @brief DMA Enable
*/
typedef enum
{
SCI2C_DMA_RX = BIT0,
SCI2C_DMA_TX = BIT1,
}SCI2C_DMA_T;
/**@} end of group SCI2C_Enumerations*/
/** @addtogroup SCI2C_Macros Macros
@{
*/
/** Macros description */
#define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E)
#define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055)
#define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55)
#define SCI2C_HSMC_RESET_VALUE ((uint32_t)0x07)
#define SCI2C_DATA_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_SSCHC_RESET_VALUE ((uint32_t)0x190)
#define SCI2C_SSCLC_RESET_VALUE ((uint32_t)0x1D6)
#define SCI2C_FSCHC_RESET_VALUE ((uint32_t)0x3C)
#define SCI2C_FSCLC_RESET_VALUE ((uint32_t)0x82)
#define SCI2C_HSCHC_RESET_VALUE ((uint32_t)0x06)
#define SCI2C_HSCLC_RESET_VALUE ((uint32_t)0x10)
#define SCI2C_INTEN_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_RFT_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_TFT_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_CTRL2_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_TFL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_RFL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_SDAHOLD_RESET_VALUE ((uint32_t)0x01)
#define SCI2C_SDNO_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_DMACTRL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_DTDL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_DRDL_RESET_VALUE ((uint32_t)0x00)
#define SCI2C_SDADLY_RESET_VALUE ((uint32_t)0x64)
#define SCI2C_GCA_RESET_VALUE ((uint32_t)0x01)
#define SCI2C_LSSSL_RESET_VALUE ((uint32_t)0x05)
#define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01)
#define SCI2C_FIFO_DEPTH (0X08)
/**@} end of group SCI2C_Macros*/
/** @addtogroup SCI2C_Structure Data Structure
@{
*/
/**
* @brief Struct description
*/
typedef struct
{
uint16_t slaveAddr; //!< Slave address.
SCI2C_MODE_T mode; //!< Specifies mode, master mode or slave mode
SCI2C_SPEED_T speed; //!< Specifies speed. Standard speed, fast speed or high speed.
uint16_t clkLowPeriod; //!< SCL high period
uint16_t clkHighPeriod; //!< SCL low period
uint8_t rxFifoThreshold; //!< Rx FIFO threshold
uint8_t txFifoThreshold; //!< Tx FIFO threshold
SCI2C_RESTART_T restart; //!< Enable or disable restart
SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode.
}SCI2C_Config_T;
/**@} end of group SCI2C_Structure*/
/** @addtogroup SCI2C_Fuctions Fuctions
@{
*/
/** Reset */
void SCI2C_Reset(SCI2C_T *i2c);
/** Configuration */
void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig);
void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig);
/** Stop detect */
void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c);
void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c);
void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c);
void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c);
/** Restart */
void SCI2C_EnableRestart(SCI2C_T *i2c);
void SCI2C_DisableRestart(SCI2C_T *i2c);
/** Speed */
void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed);
/** Address */
void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
/** Master mode and slave mode */
void SCI2C_EnableMasterMode(SCI2C_T *i2c);
void SCI2C_DisableMasterMode(SCI2C_T *i2c);
void SCI2C_EnableSlaveMode(SCI2C_T *i2c);
void SCI2C_DisableSlaveMode(SCI2C_T *i2c);
void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code);
/** Data */
void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir);
void SCI2C_TxData(SCI2C_T *i2c, uint8_t data);
uint8_t SCI2C_RxData(SCI2C_T *i2c);
void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data);
/** Rx and Tx FIFO */
uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c);
uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c);
void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
/** I2C Enable, disable, abort, block */
void SCI2C_Enable(SCI2C_T *i2c);
void SCI2C_Disable(SCI2C_T *i2c);
void SCI2C_Abort(SCI2C_T *i2c);
void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable);
/** SCL and SDA */
void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod);
void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold);
void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay);
/** ACK and NACK */
void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable);
void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable);
/** Abort */
uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c);
/** DMA */
void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt);
void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt);
/** Spike suppression limit */
void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit);
/** Ingerrupt and flag */
uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag);
void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
/**@} end of group SCI2C_Fuctions*/
/**@} end of group SCI2C_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_SCI2C_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h
+432
View File
@@ -0,0 +1,432 @@
/*!
* @file apm32f10x_sdio.h
*
* @brief This file contains all the functions prototypes for the SDIO firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_SDIO_H
#define __APM32F10X_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SDIO_Driver SDIO Driver
@{
*/
/** @addtogroup SDIO_Enumerations Enumerations
@{
*/
/**
* @brief SDIO clock edge
*/
typedef enum
{
SDIO_CLOCK_EDGE_RISING = 0x00000000,
SDIO_CLOCK_EDGE_FALLING = 0x00002000
}SDIO_CLOCK_EDGE_T;
/**
* @brief SDIO clock bypass
*/
typedef enum
{
SDIO_CLOCK_BYPASS_DISABLE = 0x00000000,
SDIO_CLOCK_BYPASS_ENABLE = 0x00000400
}SDIO_CLOCK_BYPASS_T;
/**
* @brief SDIO clock power save
*/
typedef enum
{
SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000,
SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200
}SDIO_CLOCK_POWER_SAVE_T;
/**
* @brief SDIO bus wide
*/
typedef enum
{
SDIO_BUS_WIDE_1B = 0x00000000,
SDIO_BUS_WIDE_4B = 0x00000800,
SDIO_BUS_WIDE_8B = 0x00001000
}SDIO_BUS_WIDE_T;
/**
* @brief SDIO hardware flow control
*/
typedef enum
{
SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000,
SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000
}SDIO_HARDWARE_FLOW_CONTROL_T;
/**
* @brief SDIO power state
*/
typedef enum
{
SDIO_POWER_STATE_OFF = 0x00000000,
SDIO_POWER_STATE_ON = 0x00000003
}SDIO_POWER_STATE_T;
/**
* @brief SDIO interrupt sources
*/
typedef enum
{
SDIO_INT_COMRESP = 0x00000001,
SDIO_INT_DBDR = 0x00000002,
SDIO_INT_CMDRESTO = 0x00000004,
SDIO_INT_DATATO = 0x00000008,
SDIO_INT_TXUDRER = 0x00000010,
SDIO_INT_RXOVRER = 0x00000020,
SDIO_INT_CMDRES = 0x00000040,
SDIO_INT_CMDSENT = 0x00000080,
SDIO_INT_DATAEND = 0x00000100,
SDIO_INT_SBE = 0x00000200,
SDIO_INT_DBCP = 0x00000400,
SDIO_INT_CMDACT = 0x00000800,
SDIO_INT_TXACT = 0x00001000,
SDIO_INT_RXACT = 0x00002000,
SDIO_INT_TXFHF = 0x00004000,
SDIO_INT_RXFHF = 0x00008000,
SDIO_INT_TXFF = 0x00010000,
SDIO_INT_RXFF = 0x00020000,
SDIO_INT_TXFE = 0x00040000,
SDIO_INT_RXFE = 0x00080000,
SDIO_INT_TXDA = 0x00100000,
SDIO_INT_RXDA = 0x00200000,
SDIO_INT_SDIOINT = 0x00400000,
SDIO_INT_ATAEND = 0x00800000
}SDIO_INT_T;
/**
* @brief SDIO response
*/
typedef enum
{
SDIO_RESPONSE_NO = 0x00000000,
SDIO_RESPONSE_SHORT = 0x00000040,
SDIO_RESPONSE_LONG = 0x000000C0
}SDIO_RESPONSE_T;
/**
* @brief SDIO wait interrupt state
*/
typedef enum
{
SDIO_WAIT_NO = 0x00000000,
SDIO_WAIT_INT = 0x00000100,
SDIO_WAIT_PEND = 0x00000200
}SDIO_WAIT_T;
/**
* @brief SDIO CPSM state
*/
typedef enum
{
SDIO_CPSM_DISABLE = 0x00000000,
SDIO_CPSM_ENABLE = 0x00000400
}SDIO_CPSM_T;
/**
* @brief SDIO response registers
*/
typedef enum
{
SDIO_RES1 = 0x00000000,
SDIO_RES2 = 0x00000004,
SDIO_RES3 = 0x00000008,
SDIO_RES4 = 0x0000000C
}SDIO_RES_T;
/**
* @brief SDIO data block size
*/
typedef enum
{
SDIO_DATA_BLOCKSIZE_1B = 0x00000000,
SDIO_DATA_BLOCKSIZE_2B = 0x00000010,
SDIO_DATA_BLOCKSIZE_4B = 0x00000020,
SDIO_DATA_BLOCKSIZE_8B = 0x00000030,
SDIO_DATA_BLOCKSIZE_16B = 0x00000040,
SDIO_DATA_BLOCKSIZE_32B = 0x00000050,
SDIO_DATA_BLOCKSIZE_64B = 0x00000060,
SDIO_DATA_BLOCKSIZE_128B = 0x00000070,
SDIO_DATA_BLOCKSIZE_256B = 0x00000080,
SDIO_DATA_BLOCKSIZE_512B = 0x00000090,
SDIO_DATA_BLOCKSIZE_1024B = 0x000000A0,
SDIO_DATA_BLOCKSIZE_2048B = 0x000000B0,
SDIO_DATA_BLOCKSIZE_496B = 0x000000C0,
SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0,
SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0
}SDIO_DATA_BLOCKSIZE_T;
/**
* @brief SDIO transfer direction
*/
typedef enum
{
SDIO_TRANSFER_DIR_TO_CARD = 0x00000000,
SDIO_TRANSFER_DIR_TO_SDIO = 0x00000002
}SDIO_TRANSFER_DIR_T;
/**
* @brief SDIO transfer type
*/
typedef enum
{
SDIO_TRANSFER_MODE_BLOCK = 0x00000000,
SDIO_TRANSFER_MODE_STREAM = 0x00000004
}SDIO_TRANSFER_MODE_T;
/**
* @brief SDIO DPSM state
*/
typedef enum
{
SDIO_DPSM_DISABLE = 0x00000000,
SDIO_DPSM_ENABLE = 0x00000001
}SDIO_DPSM_T;
/**
* @brief SDIO flag
*/
typedef enum
{
SDIO_FLAG_COMRESP = 0x00000001,
SDIO_FLAG_DBDR = 0x00000002,
SDIO_FLAG_CMDRESTO = 0x00000004,
SDIO_FLAG_DATATO = 0x00000008,
SDIO_FLAG_TXUDRER = 0x00000010,
SDIO_FLAG_RXOVRER = 0x00000020,
SDIO_FLAG_CMDRES = 0x00000040,
SDIO_FLAG_CMDSENT = 0x00000080,
SDIO_FLAG_DATAEND = 0x00000100,
SDIO_FLAG_SBE = 0x00000200,
SDIO_FLAG_DBCP = 0x00000400,
SDIO_FLAG_CMDACT = 0x00000800,
SDIO_FLAG_TXACT = 0x00001000,
SDIO_FLAG_RXACT = 0x00002000,
SDIO_FLAG_TXFHF = 0x00004000,
SDIO_FLAG_RXFHF = 0x00008000,
SDIO_FLAG_TXFF = 0x00010000,
SDIO_FLAG_RXFF = 0x00020000,
SDIO_FLAG_TXFE = 0x00040000,
SDIO_FLAG_RXFE = 0x00080000,
SDIO_FLAG_TXDA = 0x00100000,
SDIO_FLAG_RXDA = 0x00200000,
SDIO_FLAG_SDIOINT = 0x00400000,
SDIO_FLAG_ATAEND = 0x00800000
}SDIO_FLAG_T;
/**
* @brief SDIO read wait mode
*/
typedef enum
{
SDIO_READ_WAIT_MODE_CLK = 0x00000001,
SDIO_READ_WAIT_MODE_DATA2 = 0x00000000
}SDIO_READ_WAIT_MODE_T;
/**@} end of group SDIO_Enumerations*/
/** @addtogroup SDIO_Macros Macros
@{
*/
/** ------------ SDIO registers bit address in the alias region ----------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/** --- CLKCTRL Register ---*/
/** Alias word address of CLKEN bit */
#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04)
#define CLKEN_BitNumber 0x08
#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4))
/** --- CMD Register ---*/
/** Alias word address of SDIOSC bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define SDIOSC_BitNumber 0x0B
#define CMD_SDIOSC_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4))
/** Alias word address of CMDCPEN bit */
#define CMDCPEN_BitNumber 0x0C
#define CMD_CMDCPEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4))
/** Alias word address of INTEN bit */
#define INTEN_BitNumber 0x0D
#define CMD_INTEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4))
/** Alias word address of ATACMD bit */
#define ATACMD_BitNumber 0x0E
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
/** --- DCTRL Register ---*/
/** Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define DMAEN_BitNumber 0x03
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
/** Alias word address of RWSTR bit */
#define RWSTR_BitNumber 0x08
#define DCTRL_RWSTR_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4))
/** Alias word address of RWSTOP bit */
#define RWSTOP_BitNumber 0x09
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
/** Alias word address of RDWAIT bit */
#define RDWAIT_BitNumber 0x0A
#define DCTRL_RDWAIT_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4))
/** Alias word address of SDIOF bit */
#define SDIOF_BitNumber 0x0B
#define DCTRL_SDIOF_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4))
/**@} end of group SDIO_Macros*/
/** @addtogroup SDIO_Structure Data Structure
@{
*/
/**
* @brief SDIO Config structure definition
*/
typedef struct
{
SDIO_CLOCK_EDGE_T clockEdge;
SDIO_CLOCK_BYPASS_T clockBypass;
SDIO_CLOCK_POWER_SAVE_T clockPowerSave;
SDIO_BUS_WIDE_T busWide;
SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl;
uint8_t clockDiv;
}SDIO_Config_T;
/**
* @brief SDIO CMD Config structure definition
*/
typedef struct
{
uint32_t argument;
uint32_t cmdIndex;
SDIO_RESPONSE_T response;
SDIO_WAIT_T wait;
SDIO_CPSM_T CPSM;
}SDIO_CmdConfig_T;
/**
* @brief SDIO Data Config structure definition
*/
typedef struct
{
uint32_t dataTimeOut;
uint32_t dataLength;
SDIO_DATA_BLOCKSIZE_T dataBlockSize;
SDIO_TRANSFER_DIR_T transferDir;
SDIO_TRANSFER_MODE_T transferMode;
SDIO_DPSM_T DPSM;
}SDIO_DataConfig_T;
/**@} end of group SDIO_Structure*/
/** @addtogroup SDIO_Fuctions Fuctions
@{
*/
/** SDIO reset and configuration */
void SDIO_Reset(void);
void SDIO_Config(SDIO_Config_T* sdioConfig);
void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig);
void SDIO_EnableClock(void);
void SDIO_DisableClock(void);
void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState);
uint32_t SDIO_ReadPowerState(void);
/** DMA */
void SDIO_EnableDMA(void);
void SDIO_DisableDMA(void);
/** Command */
void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig);
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdconfig);
uint8_t SDIO_ReadCommandResponse(void);
uint32_t SDIO_ReadResponse(SDIO_RES_T res);
/** SDIO data configuration */
void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig);
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig);
uint32_t SDIO_ReadDataCounter(void);
void SDIO_WriteData(uint32_t data);
uint32_t SDIO_ReadData(void);
uint32_t SDIO_ReadFIFOCount(void);
/** SDIO mode */
void SDIO_EnableStartReadWait(void);
void SDIO_DisableStartReadWait(void);
void SDIO_EnableStopReadWait(void);
void SDIO_DisableStopReadWait(void);
void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode);
void SDIO_EnableSDIO(void);
void SDIO_DisableSDIO(void);
void SDIO_EnableTxSDIOSuspend(void);
void SDIO_DisableTxSDIOSuspend(void);
void SDIO_EnableCommandCompletion(void);
void SDIO_DisableCommandCompletion(void);
void SDIO_EnableCEATAInterrupt(void);
void SDIO_DisableCEATAInterrupt(void);
void SDIO_EnableTxCEATA(void);
void SDIO_DisableTxCEATA(void);
/** Interrupt and flags */
void SDIO_EnableInterrupt(uint32_t interrupt);
void SDIO_DisableInterrupt(uint32_t interrupt);
uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag);
void SDIO_ClearStatusFlag(uint32_t flag);
uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag);
void SDIO_ClearIntFlag(uint32_t flag);
/**@} end of group SDIO_Fuctions*/
/**@} end of group SDIO_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_SDIO_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h
+333
View File
@@ -0,0 +1,333 @@
/*!
* @file apm32f10x_spi.h
*
* @brief This file contains all the functions prototypes for the SPI firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_SPI_H
#define __APM32F10X_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SPI_Driver SPI Driver
@{
*/
/** @addtogroup SPI_Enumerations Enumerations
@{
*/
/**
* @brief SPI data direction mode
*/
typedef enum
{
SPI_DIRECTION_2LINES_FULLDUPLEX = 0x0000,
SPI_DIRECTION_2LINES_RXONLY = 0x0400,
SPI_DIRECTION_1LINE_RX = 0x8000,
SPI_DIRECTION_1LINE_TX = 0xC000
}SPI_DIRECTION_T;
/**
* @brief SPI mode
*/
typedef enum
{
SPI_MODE_MASTER = 0x0104,
SPI_MODE_SLAVE = 0x0000
}SPI_MODE_T;
/**
* @brief SPI Data length
*/
typedef enum
{
SPI_DATA_LENGTH_16B = 0x0800,
SPI_DATA_LENGTH_8B = 0x0000
}SPI_DATA_LENGTH_T;
/**
* @brief SPI Clock Polarity
*/
typedef enum
{
SPI_CLKPOL_LOW = 0x0000,
SPI_CLKPOL_HIGH = 0x0002
}SPI_CLKPOL_T;
/**
* @brief SPI Clock Phase
*/
typedef enum
{
SPI_CLKPHA_1EDGE = 0x0000,
SPI_CLKPHA_2EDGE = 0x0001
}SPI_CLKPHA_T;
/**
* @brief SPI Slave Select management
*/
typedef enum
{
SPI_NSS_SOFT = 0x0200,
SPI_NSS_HARD = 0x0000
}SPI_NSS_T;
/**
* @brief SPI BaudRate Prescaler
*/
typedef enum
{
SPI_BAUDRATE_DIV_2 = 0x0000,
SPI_BAUDRATE_DIV_4 = 0x0008,
SPI_BAUDRATE_DIV_8 = 0x0010,
SPI_BAUDRATE_DIV_16 = 0x0018,
SPI_BAUDRATE_DIV_32 = 0x0020,
SPI_BAUDRATE_DIV_64 = 0x0028,
SPI_BAUDRATE_DIV_128 = 0x0030,
SPI_BAUDRATE_DIV_256 = 0x0038,
}SPI_BAUDRATE_DIV_T;
/**
* @brief SPI MSB LSB transmission
*/
typedef enum
{
SPI_FIRSTBIT_MSB = 0x0000,
SPI_FIRSTBIT_LSB = 0x0080
}SPI_FIRSTBIT_T;
/**
* @brief I2S Mode
*/
typedef enum
{
I2S_MODE_SLAVE_TX = 0x0000,
I2S_MODE_SLAVE_RX = 0x0100,
I2S_MODE_MASTER_TX = 0x0200,
I2S_MODE_MASTER_RX = 0x0300
}I2S_MODE_T;
/**
* @brief I2S Standard
*/
typedef enum
{
I2S_STANDARD_PHILLIPS = 0x0000,
I2S_STANDARD_MSB = 0x0010,
I2S_STANDARD_LSB = 0x0020,
I2S_STANDARD_PCMSHORT = 0x0030,
I2S_STANDARD_PCMLONG = 0x00B0
}I2S_STANDARD_T;
/**
* @brief I2S data length
*/
typedef enum
{
I2S_DATA_LENGHT_16B = 0x0000,
I2S_DATA_LENGHT_16BEX = 0x0001,
I2S_DATA_LENGHT_24B = 0x0003,
I2S_DATA_LENGHT_32B = 0x0005,
} I2S_DATA_LENGTH_T;
/**
* @brief I2S_MCLK_Output
*/
typedef enum
{
I2S_MCLK_OUTPUT_DISABLE = 0x0000,
I2S_MCLK_OUTPUT_ENABLE = 0x0200,
}I2S_MCLK_OUTPUT_T;
/**
* @brief I2S Audio divider
*/
typedef enum
{
I2S_AUDIO_DIV_192K = 192000,
I2S_AUDIO_DIV_96K = 96000,
I2S_AUDIO_DIV_48K = 48000,
I2S_AUDIO_DIV_44K = 44100,
I2S_AUDIO_DIV_32K = 32000,
I2S_AUDIO_DIV_22K = 22050,
I2S_AUDIO_DIV_16K = 16000,
I2S_AUDIO_DIV_11K = 11025,
I2S_AUDIO_DIV_8K = 8000,
I2S_AUDIO_DIV_DEFAULT = 2
}I2S_AUDIO_DIV_T;
/**
* @brief I2S Clock Polarity
*/
typedef enum
{
I2S_CLKPOL_LOW = 0x0000,
I2S_CLKPOL_HIGH = 0x0008
}I2S_CLKPOL_T;
/**
* @brief SPI Direction select
*/
typedef enum
{
SPI_DIRECTION_RX = 0xBFFF,
SPI_DIRECTION_TX = 0x4000
}SPI_DIRECTION_SELECT_T;
/**
* @brief SPI interrupts definition
*/
typedef enum
{
SPI_I2S_INT_TXBE = 0x8002,
SPI_I2S_INT_RXBNE = 0x4001,
SPI_I2S_INT_ERR = 0x2000,
SPI_I2S_INT_OVR = 0x2040,
SPI_INT_CRCE = 0x2010,
SPI_INT_ME = 0x2020,
I2S_INT_UDR = 0x2008
}SPI_I2S_INT_T;
/**
* @brief SPI flags definition
*/
typedef enum
{
SPI_FLAG_RXBNE = 0x0001,
SPI_FLAG_TXBE = 0x0002,
I2S_FLAG_SCHDIR = 0x0004,
I2S_FLAG_UDR = 0x0008,
SPI_FLAG_CRCE = 0x0010,
SPI_FLAG_ME = 0x0020,
SPI_FLAG_OVR = 0x0040,
SPI_FLAG_BSY = 0x0080
}SPI_FLAG_T;
/**
* @brief SPI I2S DMA requests
*/
typedef enum
{
SPI_I2S_DMA_REQ_TX = 0x0002,
SPI_I2S_DMA_REQ_RX = 0x0001
}SPI_I2S_DMA_REQ_T;
/**@} end of group SPI_Enumerations*/
/** @addtogroup SPI_Structure Data Structure
@{
*/
/**
* @brief SPI Config structure definition
*/
typedef struct
{
SPI_MODE_T mode;
SPI_DATA_LENGTH_T length;
SPI_CLKPHA_T phase;
SPI_CLKPOL_T polarity;
SPI_NSS_T nss;
SPI_FIRSTBIT_T firstBit;
SPI_DIRECTION_T direction;
SPI_BAUDRATE_DIV_T baudrateDiv;
uint16_t crcPolynomial;
}SPI_Config_T;
/**
* @brief I2S Config structure definition
*/
typedef struct
{
I2S_MODE_T mode;
I2S_STANDARD_T standard;
I2S_DATA_LENGTH_T length;
I2S_MCLK_OUTPUT_T MCLKOutput;
I2S_AUDIO_DIV_T audioDiv;
I2S_CLKPOL_T polarity;
}I2S_Config_T;
/**@} end of group SPI_Structure*/
/** @addtogroup SPI_Fuctions Fuctions
@{
*/
/** Reset and Configuration */
void SPI_I2S_Reset(SPI_T* spi);
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig);
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig);
void SPI_ConfigStructInit(SPI_Config_T* spiConfig);
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig);
void SPI_Enable(SPI_T* spi);
void SPI_Disable(SPI_T* spi);
void I2S_Enable(SPI_T* spi);
void I2S_Disable(SPI_T* spi);
void SPI_I2S_TxData(SPI_T* spi, uint16_t data);
uint16_t SPI_I2S_RxData(SPI_T* spi);
void SPI_SetSoftwareNSS(SPI_T* spi);
void SPI_ResetSoftwareNSS(SPI_T* spi);
void SPI_EnableSSOutput(SPI_T* spi);
void SPI_DisableSSOutput(SPI_T* spi);
void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length);
/** DMA */
void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
/** CRC */
void SPI_TxCRC(SPI_T* spi);
void SPI_EnableCRC(SPI_T* spi);
void SPI_DisableCRC(SPI_T* spi);
uint16_t SPI_ReadTxCRC(SPI_T* spi);
uint16_t SPI_ReadRxCRC(SPI_T* spi);
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi);
void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction);
/** Interrupts and flag */
void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
/**@} end of group SPI_Fuctions*/
/**@} end of group SPI_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_SPI_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h
+673
View File
@@ -0,0 +1,673 @@
/*!
* @file apm32f10x_tmr.h
*
* @brief This file contains all the functions prototypes for the TMR firmware library.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_TMR_H
#define __APM32F10X_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup TMR_Driver TMR Driver
@{
*/
/** @addtogroup TMR_Enumerations Enumerations
@{
*/
/**
* @brief TMR Counter Mode
*/
typedef enum
{
TMR_COUNTER_MODE_UP = 0x0000,
TMR_COUNTER_MODE_DOWN = 0x0010,
TMR_COUNTER_MODE_CENTERALIGNED1 = 0x0020,
TMR_COUNTER_MODE_CENTERALIGNED2 = 0x0040,
TMR_COUNTER_MODE_CENTERALIGNED3 = 0x0060
} TMR_COUNTER_MODE_T;
/**
* @brief TMR Clock division
*/
typedef enum
{
TMR_CLOCK_DIV_1,
TMR_CLOCK_DIV_2,
TMR_CLOCK_DIV_4
} TMR_CLOCK_DIV_T;
/**
* @brief TMR Output Compare and PWM modes
*/
typedef enum
{
TMR_OC_MODE_TMRING = 0x00,
TMR_OC_MODE_ACTIVE = 0x01,
TMR_OC_MODE_INACTIVE = 0x02,
TMR_OC_MODE_TOGGEL = 0x03,
TMR_OC_MODE_LOWLEVEL = 0x04,
TMR_OC_MODE_HIGHLEVEL = 0x05,
TMR_OC_MODE_PWM1 = 0x06,
TMR_OC_MODE_PWM2 = 0x07
} TMR_OC_MODE_T;
/**
* @brief TMR Output Compare state
*/
typedef enum
{
TMR_OC_STATE_DISABLE,
TMR_OC_STATE_ENABLE
} TMR_OC_STATE_T;
/**
* @brief TMR Output Compare N state
*/
typedef enum
{
TMR_OC_NSTATE_DISABLE,
TMR_OC_NSTATE_ENABLE
} TMR_OC_NSTATE_T;
/**
* @brief TMR Output Compare Polarity
*/
typedef enum
{
TMR_OC_POLARITY_HIGH,
TMR_OC_POLARITY_LOW
} TMR_OC_POLARITY_T;
/**
* @brief TMR Output Compare N Polarity
*/
typedef enum
{
TMR_OC_NPOLARITY_HIGH,
TMR_OC_NPOLARITY_LOW
} TMR_OC_NPOLARITY_T;
/**
* @brief TMR Output Compare Idle State
*/
typedef enum
{
TMR_OC_IDLE_STATE_RESET,
TMR_OC_IDLE_STATE_SET
} TMR_OC_IDLE_STATE_T;
/**
* @brief TMR Output Compare N Idle State
*/
typedef enum
{
TMR_OC_NIDLE_STATE_RESET,
TMR_OC_NIDLE_STATE_SET
} TMR_OC_NIDLE_STATE_T;
/**
* @brief TMR Input Capture Init structure definition
*/
typedef enum
{
TMR_CHANNEL_1 = 0x0000,
TMR_CHANNEL_2 = 0x0004,
TMR_CHANNEL_3 = 0x0008,
TMR_CHANNEL_4 = 0x000C
} TMR_CHANNEL_T;
/**
* @brief TMR Input Capture Polarity
*/
typedef enum
{
TMR_IC_POLARITY_RISING = 0x00,
TMR_IC_POLARITY_FALLING = 0x02,
TMR_IC_POLARITY_BOTHEDGE = 0x0A
} TMR_IC_POLARITY_T;
/**
* @brief TMR Input Capture Selection
*/
typedef enum
{
TMR_IC_SELECTION_DIRECT_TI = 0x01,
TMR_IC_SELECTION_INDIRECT_TI = 0x02,
TMR_IC_SELECTION_TRC = 0x03
} TMR_IC_SELECTION_T;
/**
* @brief TMR Input Capture Prescaler
*/
typedef enum
{
TMR_IC_PSC_1,
TMR_IC_PSC_2,
TMR_IC_PSC_4,
TMR_IC_PSC_8
} TMR_IC_PSC_T;
/**
* @brief TMR Specifies the Off-State selection used in Run mode
*/
typedef enum
{
TMR_RMOS_STATE_DISABLE,
TMR_RMOS_STATE_ENABLE
} TMR_RMOS_STATE_T;
/**
* @brief TMR Closed state configuration in idle mode
*/
typedef enum
{
TMR_IMOS_STATE_DISABLE,
TMR_IMOS_STATE_ENABLE
} TMR_IMOS_STATE_T;
/**
* @brief TMR Protect mode configuration values
*/
typedef enum
{
TMR_LOCK_LEVEL_OFF,
TMR_LOCK_LEVEL_1,
TMR_LOCK_LEVEL_2,
TMR_LOCK_LEVEL_3
} TMR_LOCK_LEVEL_T;
/**
* @brief TMR BRK state
*/
typedef enum
{
TMR_BRK_STATE_DISABLE,
TMR_BRK_STATE_ENABLE
} TMR_BRK_STATE_T;
/**
* @brief TMR Specifies the Break Input pin polarity.
*/
typedef enum
{
TMR_BRK_POLARITY_LOW,
TMR_BRK_POLARITY_HIGH
} TMR_BRK_POLARITY_T;
/**
* @brief TMR Specifies the Break Input pin polarity.
*/
typedef enum
{
TMR_AUTOMATIC_OUTPUT_DISABLE,
TMR_AUTOMATIC_OUTPUT_ENABLE
} TMR_AUTOMATIC_OUTPUT_T;
/**
* @brief TMR_interrupt_sources
*/
typedef enum
{
TMR_INT_UPDATE = 0x0001,
TMR_INT_CC1 = 0x0002,
TMR_INT_CC2 = 0x0004,
TMR_INT_CC3 = 0x0008,
TMR_INT_CC4 = 0x0010,
TMR_INT_COM = 0x0020,
TMR_INT_TRG = 0x0040,
TMR_INT_BRK = 0x0080
} TMR_INT_T;
/**
* @brief TMR event sources
*/
typedef enum
{
TMR_EVENT_UPDATE = 0x001,
TMR_EVENT_CC1 = 0x002,
TMR_EVENT_CC2 = 0x004,
TMR_EVENT_CC3 = 0x008,
TMR_EVENT_CC4 = 0x010,
TMR_EVENT_COM = 0x020,
TMR_EVENT_TRG = 0x040,
TMR_EVENT_BRK = 0x080
} TMR_EVENT_T;
/**
* @brief TMR DMA Base Address
*/
typedef enum
{
TMR_DMA_BASE_CTRL1 = 0x0000,
TMR_DMA_BASE_CTRL2 = 0x0001,
TMR_DMA_BASE_SMCTRL = 0x0002,
TMR_DMA_BASE_DIEN = 0x0003,
TMR_DMA_BASE_STS = 0x0004,
TMR_DMA_BASE_CEG = 0x0005,
TMR_DMA_BASE_CCM1 = 0x0006,
TMR_DMA_BASE_CCM2 = 0x0007,
TMR_DMA_BASE_CCEN = 0x0008,
TMR_DMA_BASE_CNT = 0x0009,
TMR_DMA_BASE_PSC = 0x000A,
TMR_DMA_BASE_AUTORLD = 0x000B,
TMR_DMA_BASE_REPCNT = 0x000C,
TMR_DMA_BASE_CC1 = 0x000D,
TMR_DMA_BASE_CC2 = 0x000E,
TMR_DMA_BASE_CC3 = 0x000F,
TMR_DMA_BASE_CC4 = 0x0010,
TMR_DMA_BASE_BDT = 0x0011,
TMR_DMA_BASE_DCTRL = 0x0012
} TMR_DMA_BASE_T;
/**
* @brief TMR DMA Burst Length
*/
typedef enum
{
TMR_DMA_BURSTLENGTH_1TRANSFER = 0x0000,
TMR_DMA_BURSTLENGTH_2TRANSFERS = 0x0100,
TMR_DMA_BURSTLENGTH_3TRANSFERS = 0x0200,
TMR_DMA_BURSTLENGTH_4TRANSFERS = 0x0300,
TMR_DMA_BURSTLENGTH_5TRANSFERS = 0x0400,
TMR_DMA_BURSTLENGTH_6TRANSFERS = 0x0500,
TMR_DMA_BURSTLENGTH_7TRANSFERS = 0x0600,
TMR_DMA_BURSTLENGTH_8TRANSFERS = 0x0700,
TMR_DMA_BURSTLENGTH_9TRANSFERS = 0x0800,
TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900,
TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00,
TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00,
TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00,
TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00,
TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00,
TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00,
TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000,
TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100,
} TMR_DMA_BURSTLENGTH_T;
/**
* @brief TMR DMA Soueces
*/
typedef enum
{
TMR_DMA_SOURCE_UPDATE = 0x0100,
TMR_DMA_SOURCE_CC1 = 0x0200,
TMR_DMA_SOURCE_CC2 = 0x0400,
TMR_DMA_SOURCE_CC3 = 0x0800,
TMR_DMA_SOURCE_CC4 = 0x1000,
TMR_DMA_SOURCE_COM = 0x2000,
TMR_DMA_SOURCE_TRG = 0x4000
} TMR_DMA_SOURCE_T;
/**
* @brief TMR Internal Trigger Selection
*/
typedef enum
{
TMR_TRIGGER_SOURCE_ITR0 = 0x00,
TMR_TRIGGER_SOURCE_ITR1 = 0x01,
TMR_TRIGGER_SOURCE_ITR2 = 0x02,
TMR_TRIGGER_SOURCE_ITR3 = 0x03,
TMR_TRIGGER_SOURCE_TI1F_ED = 0x04,
TMR_TRIGGER_SOURCE_TI1FP1 = 0x05,
TMR_TRIGGER_SOURCE_TI2FP2 = 0x06,
TMR_TRIGGER_SOURCE_ETRF = 0x07
} TMR_TRIGGER_SOURCE_T;
/**
* @brief TMR The external Trigger Prescaler.
*/
typedef enum
{
TMR_EXTTRG_PSC_OFF = 0x00,
TMR_EXTTRG_PSC_DIV2 = 0x01,
TMR_EXTTRG_PSC_DIV4 = 0x02,
TMR_EXTTRG_PSC_DIV8 = 0x03
} TMR_EXTTRG_PSC_T;
/**
* @brief TMR External Trigger Polarity
*/
typedef enum
{
TMR_EXTTGR_POL_NONINVERTED,
TMR_EXTTRG_POL_INVERTED
} TMR_EXTTRG_POL_T;
/**
* @brief TMR Prescaler Reload Mode
*/
typedef enum
{
TMR_PSC_RELOAD_UPDATE,
TMR_PSC_RELOAD_IMMEDIATE
} TMR_PSC_RELOAD_T;
/**
* @brief TMR Encoder Mode
*/
typedef enum
{
TMR_ENCODER_MODE_TI1 = 0x01,
TMR_ENCODER_MODE_TI2 = 0x02,
TMR_ENCODER_MODE_TI12 = 0x03
} TMR_ENCODER_MODE_T;
/**
* @brief TMR Forced Action
*/
typedef enum
{
TMR_FORCED_ACTION_INACTIVE = 0x04,
TMR_FORCED_ACTION_ACTIVE = 0x05
} TMR_FORCED_ACTION_T;
/**
* @brief TMR Output Compare Preload State
*/
typedef enum
{
TMR_OC_PRELOAD_DISABLE,
TMR_OC_PRELOAD_ENABLE
} TMR_OC_PRELOAD_T;
/**
* @brief TMR Output Compare Preload State
*/
typedef enum
{
TMR_OC_FAST_DISABLE,
TMR_OC_FAST_ENABLE
} TMR_OC_FAST_T;
/**
* @brief TMR Output Compare Preload State
*/
typedef enum
{
TMR_OC_CLEAR_DISABLE,
TMR_OC_CLEAR_ENABLE
} TMR_OC_CLEAR_T;
/**
* @brief TMR UpdateSource
*/
typedef enum
{
TMR_UPDATE_SOURCE_GLOBAL,
TMR_UPDATE_SOURCE_REGULAR,
} TMR_UPDATE_SOURCE_T;
/**
* @brief TMR Single Pulse Mode
*/
typedef enum
{
TMR_SPM_REPETITIVE,
TMR_SPM_SINGLE,
} TMR_SPM_T;
/**
* @brief TMR Trigger Output Source
*/
typedef enum
{
TMR_TRGO_SOURCE_RESET,
TMR_TRGO_SOURCE_ENABLE,
TMR_TRGO_SOURCE_UPDATE,
TMR_TRGO_SOURCE_OC1,
TMR_TRGO_SOURCE_OC1REF,
TMR_TRGO_SOURCE_OC2REF,
TMR_TRGO_SOURCE_OC3REF,
TMR_TRGO_SOURCE_OC4REF
} TMR_TRGO_SOURCE_T;
/**
* @brief TMR Slave Mode
*/
typedef enum
{
TMR_SLAVE_MODE_RESET = 0x04,
TMR_SLAVE_MODE_GATED = 0x05,
TMR_SLAVE_MODE_TRIGGER = 0x06,
TMR_SLAVE_MODE_EXTERNAL1 = 0x07
} TMR_SLAVE_MODE_T;
/**
* @brief TMR Flag
*/
typedef enum
{
TMR_FLAG_UPDATE = 0x0001,
TMR_FLAG_CC1 = 0x0002,
TMR_FLAG_CC2 = 0x0004,
TMR_FLAG_CC3 = 0x0008,
TMR_FLAG_CC4 = 0x0010,
TMR_FLAG_COM = 0x0020,
TMR_FLAG_TRG = 0x0040,
TMR_FLAG_BRK = 0x0080,
TMR_FLAG_CC1RC = 0x0200,
TMR_FLAG_CC2RC = 0x0400,
TMR_FLAG_CC3RC = 0x0800,
TMR_FLAG_CC4RC = 0x1000
} TMR_FLAG_T;
/**@} end of group TMR_Enumerations*/
/** @addtogroup TMR_Structure Data Structure
@{
*/
/**
* @brief TMR Config struct definition
*/
typedef struct
{
TMR_COUNTER_MODE_T countMode;
TMR_CLOCK_DIV_T clockDivision;
uint16_t period; //!< This must between 0x0000 and 0xFFFF
uint16_t division; //!< This must between 0x0000 and 0xFFFF
uint8_t repetitionCounter; //!< This must between 0x00 and 0xFF, only for TMR1 and TMR8.
} TMR_BaseConfig_T; ;
/**
* @brief TMR Config struct definition
*/
typedef struct
{
TMR_OC_MODE_T mode;
TMR_OC_STATE_T outputState;
TMR_OC_NSTATE_T outputNState;
TMR_OC_POLARITY_T polarity;
TMR_OC_NPOLARITY_T nPolarity;
TMR_OC_IDLE_STATE_T idleState;
TMR_OC_NIDLE_STATE_T nIdleState;
uint16_t pulse; //!< This must between 0x0000 and 0xFFFF
} TMR_OCConfig_T;
/**
* @brief TMR BDT structure definition
*/
typedef struct
{
TMR_RMOS_STATE_T RMOS;
TMR_IMOS_STATE_T IMOS;
TMR_LOCK_LEVEL_T lockLevel;
uint16_t deadTime;
TMR_BRK_STATE_T BRKState;
TMR_BRK_POLARITY_T BRKPolarity;
TMR_AUTOMATIC_OUTPUT_T automaticOutput;
} TMR_BDTConfig_T;
/**
* @brief TMR Input Capture Config struct definition
*/
typedef struct
{
TMR_CHANNEL_T channel;
TMR_IC_POLARITY_T polarity;
TMR_IC_SELECTION_T selection;
TMR_IC_PSC_T prescaler;
uint16_t filter; //!< This must between 0x00 and 0x0F
} TMR_ICConfig_T;
/**@} end of group TMR_Structure*/
/** @addtogroup TMR_Fuctions Fuctions
@{
*/
/** Reset and Configuration */
void TMR_Reset(TMR_T* tmr);
void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig);
void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig);
void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig);
void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig);
void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
void TMR_Enable(TMR_T* tmr);
void TMR_Disable(TMR_T* tmr);
/** PWM Configuration */
void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig);
void TMR_EnablePWMOutputs(TMR_T* tmr);
void TMR_DisablePWMOutputs(TMR_T* tmr);
/** DMA */
void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
/** Configuration */
void TMR_ConfigInternalClock(TMR_T* tmr);
void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
TMR_IC_POLARITY_T IC2Polarity);
void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_EnableAutoReload(TMR_T* tmr);
void TMR_DisableAutoReload(TMR_T* tmr);
void TMR_EnableSelectCOM(TMR_T* tmr);
void TMR_DisableSelectCOM(TMR_T* tmr);
void TMR_EnableCCDMA(TMR_T* tmr);
void TMR_DisableCCDMA(TMR_T* tmr);
void TMR_EnableCCPreload(TMR_T* tmr);
void TMR_DisableCCPreload(TMR_T* tmr);
void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
void TMR_EnableUpdate(TMR_T* tmr);
void TMR_DisableUpdate(TMR_T* tmr);
void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
void TMR_EnableHallSensor(TMR_T* tmr);
void TMR_DisableHallSensor(TMR_T* tmr);
void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
void TMR_EnableMasterSlaveMode(TMR_T* tmr);
void TMR_DisableMasterSlaveMode(TMR_T* tmr);
void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
uint16_t TMR_ReadCaputer1(TMR_T* tmr);
uint16_t TMR_ReadCaputer2(TMR_T* tmr);
uint16_t TMR_ReadCaputer3(TMR_T* tmr);
uint16_t TMR_ReadCaputer4(TMR_T* tmr);
uint16_t TMR_ReadCounter(TMR_T* tmr);
uint16_t TMR_ReadPrescaler(TMR_T* tmr);
/** Interrupts and Event */
void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources);
/** flags */
uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag);
/**@} end of group TMR_Fuctions*/
/**@} end of group TMR_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_TMR_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h
+310
View File
@@ -0,0 +1,310 @@
/*!
* @file apm32f10x_usart.h
*
* @brief This file contains all the functions prototypes for the USART firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_USART_H
#define __APM32F10X_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup USART_Driver USART Driver
@{
*/
/** @addtogroup USART_Enumerations Enumerations
@{
*/
/**
* @brief USART Word Length define
*/
typedef enum
{
USART_WORD_LEN_8B = 0,
USART_WORD_LEN_9B = BIT12
} USART_WORD_LEN_T;
/**
* @brief USART Stop bits define
*/
typedef enum
{
USART_STOP_BIT_1 = 0,
USART_STOP_BIT_0_5 = BIT12,
USART_STOP_BIT_2 = BIT13,
USART_STOP_BIT_1_5 = BIT12 | BIT13
} USART_STOP_BIT_T;
/**
* @brief USART Parity define
*/
typedef enum
{
USART_PARITY_NONE = 0,
USART_PARITY_EVEN = BIT10,
USART_PARITY_ODD = BIT10 | BIT9
} USART_PARITY_T;
/**
* @brief USART mode define
*/
typedef enum
{
USART_MODE_RX = BIT2,
USART_MODE_TX = BIT3,
USART_MODE_TX_RX = BIT2 | BIT3
} USART_MODE_T;
/**
* @brief USART hardware flow control define
*/
typedef enum
{
USART_HARDWARE_FLOW_NONE = 0,
USART_HARDWARE_FLOW_RTS = BIT8,
USART_HARDWARE_FLOW_CTS = BIT9,
USART_HARDWARE_FLOW_RTS_CTS = BIT8 | BIT9
} USART_HARDWARE_FLOW_T;
/**
* @brief USART Clock enable
*/
typedef enum
{
USART_CLKEN_DISABLE,
USART_CLKEN_ENABLE
} USART_CLKEN_T;
/**
* @brief USART Clock polarity define
*/
typedef enum
{
USART_CLKPOL_LOW,
USART_CLKPOL_HIGH
} USART_CLKPOL_T;
/**
* @brief USART Clock phase define
*/
typedef enum
{
USART_CLKPHA_1EDGE,
USART_CLKPHA_2EDGE
} USART_CLKPHA_T;
/**
* @brief USART Last bit clock pulse enable
*/
typedef enum
{
USART_LBCP_DISABLE,
USART_LBCP_ENABLE,
} USART_LBCP_T;
/**
* @brief USART Interrupt Source
*/
typedef enum
{
USART_INT_PE = 0x0010100,
USART_INT_TXBE = 0x7010080,
USART_INT_TXC = 0x6010040,
USART_INT_RXBNE = 0x5010020,
USART_INT_IDLE = 0x4010010,
USART_INT_LBD = 0x8020040,
USART_INT_CTS = 0x9040400,
USART_INT_ERR = 0x0040001,
USART_INT_OVRE = 0x3040001,
USART_INT_NE = 0x2040001,
USART_INT_FE = 0x1040001
} USART_INT_T;
/**
* @brief USART DMA enable
*/
typedef enum
{
USART_DMA_TX = BIT7,
USART_DMA_RX = BIT6,
USART_DMA_TX_RX = BIT6 | BIT7
} USART_DMA_T;
/**
* @brief USART Wakeup method
*/
typedef enum
{
USART_WAKEUP_IDLE_LINE,
USART_WAKEUP_ADDRESS_MARK
} USART_WAKEUP_T;
/**
* @brief USART LIN break detection length
*/
typedef enum
{
USART_LBDL_10B,
USART_LBDL_11B
} USART_LBDL_T;
/**
* @brief USART IrDA low-power
*/
typedef enum
{
USART_IRDALP_NORMAL,
USART_IRDALP_LOWPOWER
} USART_IRDALP_T;
/**
* @brief USART flag define
*/
typedef enum
{
USART_FLAG_CTS = 0x0200,
USART_FLAG_LBD = 0x0100,
USART_FLAG_TXBE = 0x0080,
USART_FLAG_TXC = 0x0040,
USART_FLAG_RXBNE = 0x0020,
USART_FLAG_IDLE = 0x0010,
USART_FLAG_OVRE = 0x0008,
USART_FLAG_NE = 0x0004,
USART_FLAG_FE = 0x0002,
USART_FLAG_PE = 0x0001
} USART_FLAG_T;
/**@} end of group USART_Enumerations*/
/** @addtogroup USART_Structure Data Structure
@{
*/
/**
* @brief USART Config struct definition
*/
typedef struct
{
uint32_t baudRate; //!< Specifies the baud rate
USART_WORD_LEN_T wordLength; //!< Specifies the word length
USART_STOP_BIT_T stopBits; //!< Specifies the stop bits
USART_PARITY_T parity; //!< Specifies the parity
USART_MODE_T mode; //!< Specifies the mode
USART_HARDWARE_FLOW_T hardwareFlow; //!< Specifies the hardware flow control
} USART_Config_T;
/**
* @brief USART synchronous communication clock config struct definition
*/
typedef struct
{
USART_CLKEN_T clock; //!< Enable or Disable Clock
USART_CLKPOL_T polarity; //!< Specifies the clock polarity
USART_CLKPHA_T phase; //!< Specifies the clock phase
USART_LBCP_T lastBit; //!< Enable or Disable last bit clock
} USART_ClockConfig_T;
/**@} end of group USART_Structure*/
/** @addtogroup USART_Fuctions Fuctions
@{
*/
/** USART Reset and Configuration */
void USART_Reset(USART_T* usart);
void USART_Config(USART_T* uart, USART_Config_T* usartConfig);
void USART_ConfigStructInit(USART_Config_T* usartConfig);
void USART_Address(USART_T* usart, uint8_t address);
void USART_Enable(USART_T* usart);
void USART_Disable(USART_T* usart);
/** Clock communication */
void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig);
void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig);
/** DMA mode */
void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq);
void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq);
/** Mute mode */
void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup);
void USART_EnableMuteMode(USART_T* usart);
void USART_DisableMuteMode(USART_T* usart);
/** LIN mode */
void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length);
void USART_EnableLIN(USART_T* usart);
void USART_DisableLIN(USART_T* usart);
/** Transmit and receive */
void USART_EnableTx(USART_T* usart);
void USART_DisableTx(USART_T* usart);
void USART_EnableRx(USART_T* usart);
void USART_DisableRx(USART_T* usart);
void USART_TxData(USART_T* usart, uint16_t data);
uint16_t USART_RxData(USART_T* usart);
void USART_TxBreak(USART_T* usart);
/** Smartcard mode */
void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime);
void USART_ConfigPrescaler(USART_T* usart, uint8_t div);
void USART_EnableSmartCard(USART_T* usart);
void USART_DisableSmartCard(USART_T* usart);
void USART_EnableSmartCardNACK(USART_T* usart);
void USART_DisableSmartCardNACK(USART_T* usart);
/** Half-duplex mode */
void USART_EnableHalfDuplex(USART_T* usart);
void USART_DisableHalfDuplex(USART_T* usart);
/** IrDA mode */
void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode);
void USART_EnableIrDA(USART_T* usart);
void USART_DisableIrDA(USART_T* usart);
/** Interrupt and flag */
void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt);
void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt);
uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag);
void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag);
uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag);
void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag);
/**@} end of group USART_Fuctions*/
/**@} end of group USART_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_USART_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h
+92
View File
@@ -0,0 +1,92 @@
/*!
* @file apm32f10x_wwdt.h
*
* @brief This file contains all the functions prototypes for the WWDT firmware library
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F10X_WWDT_H
#define __APM32F10X_WWDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f10x.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup WWDT_Enumerations Enumerations
@{
*/
/**
* @brief WWDT Timebase(Prescaler) define
*/
typedef enum
{
WWDT_TIME_BASE_1 = 0x00000000,
WWDT_TIME_BASE_2 = 0x00000080,
WWDT_TIME_BASE_4 = 0x00000100,
WWDT_TIME_BASE_8 = 0x00000180
}WWDT_TIME_BASE_T;
/**@} end of group WWDT_Enumerations*/
/** @addtogroup WWDT_Fuctions Fuctions
@{
*/
/** WWDT reset */
void WWDT_Reset(void);
/** Config WWDT Timebase */
void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase);
/** Config Window Data */
void WWDT_ConfigWindowData(uint8_t windowData);
/** Config Couter */
void WWDT_ConfigCounter(uint8_t counter);
/** Enable WWDT and Early Wakeup interrupt */
void WWDT_EnableEWI(void);
void WWDT_Enable(uint8_t count);
/** Read Flag and Clear Flag */
uint8_t WWDT_ReadFlag(void);
void WWDT_ClearFlag(void);
/**@} end of group WWDT_Fuctions*/
/**@} end of group WWDT_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __APM32F10X_WWDT_H */
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c
+1064
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c
+248
View File
@@ -0,0 +1,248 @@
/*!
* @file apm32f10x_bakpr.c
*
* @brief This file provides all the BAKPR firmware functions.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_bakpr.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup BAKPR_Driver ADC Driver
@{
*/
/** @addtogroup BAKPR_Fuctions Fuctions
@{
*/
/*!
* @brief Reset the BAKPR peripheral registers to their default reset values.
*
* @param None
*
* @retval None
*/
void BAKPR_Reset(void)
{
RCM_EnableBackupReset();
RCM_DisableBackupReset();
}
/*!
* @brief Deinitializes the BAKPR peripheral registers to their default reset values.
*
* @param value: specifies the RTC output source.
* This parameter can be one of the following values:
* @arg BAKPR_TAMPER_PIN_LEVEL_HIGH: Tamper pin active on high level
* @arg BAKPR_TAMPER_PIN_LEVEL_LOW: Tamper pin active on low level
*
* @retval None
*/
void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value)
{
BAKPR->CTRL_B.TPALCFG = value;
}
/*!
* @brief Enables the Tamper Pin activation.
*
* @param None
*
* @retval None
*/
void BAKPR_EnableTamperPin(void)
{
BAKPR->CTRL_B.TPFCFG = ENABLE ;
}
/*!
* @brief Disables the Tamper Pin activation.
*
* @param None
*
* @retval None
*/
void BAKPR_DisableTamperPin(void)
{
BAKPR->CTRL_B.TPFCFG = DISABLE ;
}
/*!
* @brief Enables the Tamper Pin Interrupt.
*
* @param None
*
* @retval None
*/
void BAKPR_EnableInterrupt(void)
{
BAKPR->CSTS_B.TPIEN = ENABLE ;
}
/*!
* @brief Disables the Tamper Pin Interrupt.
*
* @param None
*
* @retval None
*/
void BAKPR_DisableInterrupt(void)
{
BAKPR->CSTS_B.TPIEN = DISABLE ;
}
/*!
* @brief Select the RTC output source to output on the Tamper pin.
*
* @param soure: specifies the RTC output source.
* This parameter can be one of the following values:
* @arg BAKPR_RTC_OUTPUT_SOURCE_NONE : no RTC output on the Tamper pin.
* @arg BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK: output the RTC clock with frequency divided by 64 on the Tamper pin.
* @arg BAKPR_RTC_OUTPUT_SOURCE_ALARM : output the RTC Alarm pulse signal on the Tamper pin.
* @arg BAKPR_RTC_OUTPUT_SOURCE_SECOND : output the RTC Second pulse signal on the Tamper pin.
*
* @retval None
*/
void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure)
{
if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
{
BAKPR->CLKCAL = RESET;
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
{
BAKPR->CLKCAL_B.CALCOEN = BIT_SET;
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
{
BAKPR->CLKCAL_B.ASPOEN = BIT_SET;
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
{
BAKPR->CLKCAL_B.ASPOSEL = BIT_SET;
}
}
/*!
* @brief Sets RTC Clock Calibration value.
*
* @param calibrationValue: Specifies the calibration value.
* This parameter must be a number between 0 and 0x7F.
*
* @retval None
*/
void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue)
{
BAKPR->CLKCAL_B.CALVALUE = calibrationValue;
}
/*!
* @brief Set user data to the specified Data Backup Register.
*
* @param bakrData : specifies the Data Backup Register.
* This parameter can be BAKPR_DATAx where x is between 1 and 42.
*
* @param data : data to set
* This parameter can be a 16bit value.
*
* @retval None
*/
void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data)
{
__IOM uint32_t tmp = 0;
tmp = (uint32_t)BAKPR_BASE;
tmp += bakrData;
*(__IOM uint32_t *) tmp = data;
}
/*!
* @brief Reads user data from the specified Data Backup Register.
*
* @param bakrData : specifies the Data Backup Register.
* This parameter can be BAKPR_DATAx where x is between 1 and 42.
*
* @retval The content of the specified Data Backup Register
*/
uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData)
{
__IOM uint32_t tmp = 0;
tmp = (uint32_t)BAKPR_BASE;
tmp += bakrData;
return (*(__IOM uint32_t *) tmp);
}
/*!
* @brief Read whether the Tamper Pin Event flag is set or not.
*
* @param None
*
* @retval Tamper Pin Event flag state
*/
uint8_t BAKPR_ReadStatusFlag(void)
{
return BAKPR->CSTS_B.TEFLG;
}
/*!
* @brief Clears Tamper Pin Event pending flag.
*
* @param None
*
* @retval None
*/
void BAKPR_ClearStatusFlag(void)
{
BAKPR->CSTS_B.TECLR = BIT_SET;
}
/*!
* @brief Get whether the Tamper Pin Interrupt has occurred or not.
*
* @param None
*
* @retval Tamper Pin Interrupt State
*/
uint8_t BAKPR_ReadIntFlag(void)
{
return BAKPR->CSTS_B.TIFLG;
}
/*!
* @brief Clears Tamper Pin Interrupt pending bit.
*
* @param None
*
* @retval None
*/
void BAKPR_ClearIntFlag(void)
{
BAKPR->CSTS_B.TICLR = BIT_SET;
}
/**@} end of group BAKPR_Fuctions*/
/**@} end of group BAKPR_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c
+1094
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c
+124
View File
@@ -0,0 +1,124 @@
/*!
* @file apm32f10x_crc.c
*
* @brief This file provides all the CRC firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_crc.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup CRC_Driver CRC Driver
@{
*/
/** @addtogroup CRC_Fuctions Fuctions
@{
*/
/*!
* @brief Reset CRC data register.
*
* @param None
*
* @retval None
*/
void CRC_ResetDATA(void)
{
CRC->CTRL_B.RST = BIT_SET;
}
/*!
* @brief Calculate CRC of a 32bit data word.
*
* @param data: a data word to compute its CRC.
* This parameter can be a 32bit value:
*
* @retval A 32-bit CRC value
*/
uint32_t CRC_CalculateCRC(uint32_t data)
{
CRC->DATA = data;
return (CRC->DATA);
}
/*!
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
*
* @param buf: Pointer to the buffer containing the data to be computed.
*
* @param bufLen: The length of buffer which is computed.
*
* @retval A 32-bit CRC value
*/
uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen)
{
while(bufLen--)
{
CRC->DATA = *buf++;
}
return (CRC->DATA);
}
/*!
* @brief Returns the current CRC value.
*
* @param None
*
* @retval A 32-bit CRC value
*/
uint32_t CRC_ReadCRC(void)
{
return (CRC->DATA);
}
/*!
* @brief Saves a 8bit data in the Independent Data register(INDATA).
*
* @param inData: a 8-bit value to be stored in the ID register
*
* @retval None
*/
void CRC_WriteIDRegister(uint8_t inData)
{
CRC->INDATA = inData;
}
/*!
* @brief Reads a 8-bit data saved in the Independent Data register(INDATA).
*
* @param None
*
* @retval a 8-bit value from the INDATA register
*/
uint8_t CRC_ReadIDRegister(void)
{
return (CRC->INDATA);
}
/**@} end of group CRC_Fuctions*/
/**@} end of group CRC_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c
+411
View File
@@ -0,0 +1,411 @@
/*!
* @file apm32f10x_dac.c
*
* @brief This file provides all the DAC firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_dac.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DAC_Driver DAC Driver
@{
*/
/** @addtogroup DAC_Fuctions Fuctions
@{
*/
/*!
* @brief Reset dac peripheral registers to their default reset values.
*
* @param None
*
* @retval None
*/
void DAC_Reset(void)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_DAC);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_DAC);
}
/*!
* @brief Config the DAC peripheral according to the specified parameters in the dacConfig
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @param dacConfig: pointer to a DAC_Config_T structure
*
* @retval None
*/
void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
{
uint32_t tmp1 = 0, tmp2 = 0;
tmp1 = DAC->CTRL;
tmp1 &= ~(((uint32_t)0x00000FFE) << channel);
tmp2 = ((uint32_t)dacConfig->trigger | \
(uint32_t)dacConfig->waveGeneration | \
(uint32_t)dacConfig->maskAmplitudeSelect | \
(uint32_t)dacConfig->outputBuffer);
tmp1 |= tmp2 << channel;
DAC->CTRL = tmp1;
}
/*!
* @brief Fills each DAC_Config_T member with its default value
*
* @param dacConfig: pointer to a DAC_Config_T structure which will be initialized
*
* @retval None
*/
void DAC_ConfigStructInit(DAC_Config_T* dacConfig)
{
/** Initialize the DAC_Trigger member */
dacConfig->trigger = DAC_TRIGGER_NONE;
/** Initialize the DAC_WaveGeneration member */
dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE;
/** Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
dacConfig->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1;
/** Initialize the DAC_OutputBuffer member */
dacConfig->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE;
}
/*!
* @brief Enables the specified DAC peripheral
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @retval None
*/
void DAC_Enable(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.ENCH1 = BIT_SET;
}
else if (channel == DAC_CHANNEL_2)
{
DAC->CTRL_B.ENCH2 = BIT_SET;
}
}
/*!
* @brief Disables the specified DAC peripheral
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @retval None
*/
void DAC_Disable(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.ENCH1 = BIT_RESET;
}
else if (channel == DAC_CHANNEL_2)
{
DAC->CTRL_B.ENCH2 = BIT_RESET;
}
}
/*!
* @brief Enables the specified DAC channel DMA request
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @retval None
*/
void DAC_DMA_Enable(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.DMAENCH1 = BIT_SET;
}
else if (channel == DAC_CHANNEL_2)
{
DAC->CTRL_B.DMAENCH2 = BIT_SET;
}
}
/*!
* @brief Disables the specified DAC channel DMA request
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @retval None
*/
void DAC_DMA_Disable(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.DMAENCH1 = BIT_RESET;
}
else if (channel == DAC_CHANNEL_2)
{
DAC->CTRL_B.DMAENCH2 = BIT_RESET;
}
}
/*!
* @brief Enables the selected DAC channel software trigger
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @retval None
*/
void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->SWTRG_B.SWTRG1 = BIT_SET;
}
else if (channel == DAC_CHANNEL_2)
{
DAC->SWTRG_B.SWTRG2 = BIT_SET;
}
}
/*!
* @brief Disable the selected DAC channel software trigger
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @retval None
*/
void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->SWTRG_B.SWTRG1 = BIT_RESET;
}
else if (channel == DAC_CHANNEL_2)
{
DAC->SWTRG_B.SWTRG2 = BIT_RESET;
}
}
/*!
* @brief Enables simultaneously the two DAC channels software
*
* @param None
*
* @retval None
*/
void DAC_EnableDualSoftwareTrigger(void)
{
DAC->SWTRG_B.SWTRG1 = BIT_SET;
DAC->SWTRG_B.SWTRG2 = BIT_SET;
}
/*!
* @brief Disables simultaneously the two DAC channels software
*
* @param None
*
* @retval None
*/
void DAC_DisableDualSoftwareTrigger(void)
{
DAC->SWTRG_B.SWTRG1 = BIT_RESET;
DAC->SWTRG_B.SWTRG2 = BIT_RESET;
}
/*!
* @brief Enables the selected DAC channel wave generation
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @param wave: Select the wave
* This parameter can be one of the following values:
* @arg DAC_WAVE_GENERATION_NONE : no wave generation
* @arg DAC_WAVE_GENERATION_NOISE : Noise wave generation
* @arg DAC_WAVE_GENERATION_TRIANGLE : Triangle wave generation
*
* @retval None
*/
void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave)
{
DAC->CTRL &= 0xFF3FFF3F;
DAC->CTRL |= wave << channel;
}
/*!
* @brief Disables the selected DAC channel wave generation
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @param wave: Select the wave
* This parameter can be one of the following values:
* @arg DAC_WAVE_GENERATION_NONE : no wave generation
* @arg DAC_WAVE_GENERATION_NOISE : Noise wave generation
* @arg DAC_WAVE_GENERATION_TRIANGLE : Triangle wave generation
*
* @retval None
*/
void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave)
{
DAC->CTRL &= ~(wave << channel);
}
/*!
* @brief Set the specified data holding register value for DAC channel 1
*
* @param align: DAC channel 1 data alignment
* This parameter can be one of the following values:
* @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data
* @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data
* @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data
*
* @param data: The data to be loaded in the selected data register.
*
* @retval None
*/
void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += 0x00000008 + align;
/** Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = data;
}
/*!
* @brief Set the specified data holding register value for DAC channel 2
*
* @param align: DAC channel 2 data alignment
* This parameter can be one of the following values:
* @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data
* @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data
* @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data
*
* @param data: The data to be loaded in the selected data register.
*
* @retval None
*/
void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += 0x00000014 + align;
/** Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = data;
}
/*!
* @brief Set the specified data holding register value for dual DAC channel
*
* @param align: Dual DAC channel data alignment
* This parameter can be one of the following values:
* @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data
* @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data
* @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data
*
* @param data2: Data for channel2 to be loaded in the selected data register.
*
* @param data1: Data for channel1 to be loaded in the selected data register
*
* @retval None
*/
void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1)
{
uint32_t data = 0, tmp = 0;
/** Calculate and set dual DAC data holding register value */
if (align == DAC_ALIGN_8BIT_R)
{
data = ((uint32_t)data2 << 8) | data1;
}
else
{
data = ((uint32_t)data2 << 16) | data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += 0x00000020 + align;
/** Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
}
/*!
* @brief Reads the specified DAC channel data output value.
*
* @param channel: Select the DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1 : DAC channel 1
* @arg DAC_CHANNEL_2 : DAC channel 2
*
* @retval The data output value of the specified DAC channel.
*/
uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t) DAC_BASE ;
tmp += 0x0000002C + ((uint32_t)channel >> 2);
/** Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
/**@} end of group DAC_Fuctions*/
/**@} end of group DAC_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c
+146
View File
@@ -0,0 +1,146 @@
/*!
* @file apm32f10x_dbgmcu.c
*
* @brief This file provides all the DEBUG firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_dbgmcu.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DBGMCU_Driver DBGMCU Driver
@{
*/
/** @addtogroup DBGMCU_Fuctions Fuctions
@{
*/
/*!
* @brief Returns the device identifier.
*
* @param None
*
* @retval Device identifier
*/
uint32_t DBGMCU_ReadDEVID(void)
{
return(DBGMCU->IDCODE_B.EQR);
}
/*!
* @brief Returns the device revision identifier.
*
* @param None
*
* @retval Device revision identifier
*/
uint32_t DBGMCU_ReadREVID(void)
{
return(DBGMCU->IDCODE_B.WVR);
}
/*!
* @brief Enable the specified peripheral and low power mode behavior
* when the MCU under Debug mode
*
* @param periph: Specifies the peripheral and low power mode
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP : Keep debugger connection during SLEEP mode
* @arg DBGMCU_STOP : Keep debugger connection during STOP mode
* @arg DBGMCU_STANDBY : Keep debugger connection during STANDBY mode
* @arg DBGMCU_IWDT_STOP : Debug IWDT stopped when Core is halted
* @arg DBGMCU_WWDT_STOP : Debug WWDT stopped when Core is halted
* @arg DBGMCU_TMR1_STOP : TMR1 counter stopped when Core is halted
* @arg DBGMCU_TMR2_STOP : TMR2 counter stopped when Core is halted
* @arg DBGMCU_TMR3_STOP : TMR3 counter stopped when Core is halted
* @arg DBGMCU_TMR4_STOP : TMR4 counter stopped when Core is halted
* @arg DBGMCU_CAN1_STOP : Debug CAN1 stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_TMR5_STOP : TMR5 counter stopped when Core is halted
* @arg DBGMCU_TMR6_STOP : TMR6 counter stopped when Core is halted
* @arg DBGMCU_TMR7_STOP : TMR7 counter stopped when Core is halted
* @arg DBGMCU_TMR8_STOP : TMR8 counter stopped when Core is halted
* @arg DBGMCU_CAN2_STOP : Debug CAN2 stopped when Core is halted
* @arg DBGMCU_TMR15_STOP : TMR15 counter stopped when Core is halted
* @arg DBGMCU_TMR16_STOP : TMR16 counter stopped when Core is halted
* @arg DBGMCU_TMR17_STOP : TMR17 counter stopped when Core is halted
* @arg DBGMCU_TMR9_STOP : TMR9 counter stopped when Core is halted
* @arg DBGMCU_TMR10_STOP : TMR10 counter stopped when Core is halted
* @arg DBGMCU_TMR11_STOP : TMR11 counter stopped when Core is halted
* @arg DBGMCU_TMR12_STOP : TMR12 counter stopped when Core is halted
* @arg DBGMCU_TMR13_STOP : TMR13 counter stopped when Core is halted
* @arg DBGMCU_TMR14_STOP : TMR14 counter stopped when Core is halted
*
* @retval None
*/
void DBGMCU_Enable(uint32_t periph)
{
DBGMCU->CFG |= periph;
}
/*!
* @brief Enable the specified peripheral and low power mode behavior
* when the MCU under Debug mode
*
* @param periph: Specifies the peripheral and low power mode
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP : Keep debugger connection during SLEEP mode
* @arg DBGMCU_STOP : Keep debugger connection during STOP mode
* @arg DBGMCU_STANDBY : Keep debugger connection during STANDBY mode
* @arg DBGMCU_IWDT_STOP : Debug IWDT stopped when Core is halted
* @arg DBGMCU_WWDT_STOP : Debug WWDT stopped when Core is halted
* @arg DBGMCU_TMR1_STOP : TMR1 counter stopped when Core is halted
* @arg DBGMCU_TMR2_STOP : TMR2 counter stopped when Core is halted
* @arg DBGMCU_TMR3_STOP : TMR3 counter stopped when Core is halted
* @arg DBGMCU_TMR4_STOP : TMR4 counter stopped when Core is halted
* @arg DBGMCU_CAN1_STOP : Debug CAN1 stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_TMR5_STOP : TMR5 counter stopped when Core is halted
* @arg DBGMCU_TMR6_STOP : TMR6 counter stopped when Core is halted
* @arg DBGMCU_TMR7_STOP : TMR7 counter stopped when Core is halted
* @arg DBGMCU_TMR8_STOP : TMR8 counter stopped when Core is halted
* @arg DBGMCU_CAN2_STOP : Debug CAN2 stopped when Core is halted
* @arg DBGMCU_TMR15_STOP : TMR15 counter stopped when Core is halted
* @arg DBGMCU_TMR16_STOP : TMR16 counter stopped when Core is halted
* @arg DBGMCU_TMR17_STOP : TMR17 counter stopped when Core is halted
* @arg DBGMCU_TMR9_STOP : TMR9 counter stopped when Core is halted
* @arg DBGMCU_TMR10_STOP : TMR10 counter stopped when Core is halted
* @arg DBGMCU_TMR11_STOP : TMR11 counter stopped when Core is halted
* @arg DBGMCU_TMR12_STOP : TMR12 counter stopped when Core is halted
* @arg DBGMCU_TMR13_STOP : TMR13 counter stopped when Core is halted
* @arg DBGMCU_TMR14_STOP : TMR14 counter stopped when Core is halted
*
* @retval None
*/
void DBGMCU_Disable(uint32_t periph)
{
DBGMCU->CFG &= ~periph;
}
/**@} end of group DBGMCU_Fuctions*/
/**@} end of group DBGMCU_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c
+560
View File
@@ -0,0 +1,560 @@
/*!
* @file apm32f10x_dma.c
*
* @brief This file provides all the DMA firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_dma.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DMA_Driver DMA Driver
@{
*/
/** @addtogroup DMA_Fuctions Fuctions
@{
*/
/*!
* @brief Reset specified DMA Channel registers to their default reset
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5).
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_Reset(DMA_Channel_T *channel)
{
channel->CHCFG_B.CHEN = BIT_RESET;
channel->CHCFG = 0;
channel->CHNDATA = 0;
channel->CHMADDR = 0;
channel->CHPADDR = 0;
if(channel == DMA1_Channel1)
{
DMA1->INTFCLR |= 0xFFFFFFF0;
}
else if(channel == DMA1_Channel2)
{
DMA1->INTFCLR |= 0xFFFFFF0F;
}
else if(channel == DMA1_Channel3)
{
DMA1->INTFCLR |= 0xFFFFF0FF;
}
else if(channel == DMA1_Channel4)
{
DMA1->INTFCLR |= 0xFFFF0FFF;
}
else if(channel == DMA1_Channel5)
{
DMA1->INTFCLR |= 0xFFF0FFFF;
}
else if(channel == DMA1_Channel6)
{
DMA1->INTFCLR |= 0xFF0FFFFF;
}
else if(channel == DMA1_Channel7)
{
DMA1->INTFCLR |= 0xF0FFFFFF;
}
else if(channel == DMA2_Channel1)
{
DMA2->INTFCLR |= 0xFFFFFFF0;
}
else if(channel == DMA2_Channel2)
{
DMA2->INTFCLR |= 0xFFFFFF0F;
}
else if(channel == DMA2_Channel3)
{
DMA2->INTFCLR |= 0xFFFFF0FF;
}
else if(channel == DMA2_Channel4)
{
DMA2->INTFCLR |= 0xFFFF0FFF;
}
else if(channel == DMA2_Channel5)
{
DMA2->INTFCLR |= 0xFFF0FFFF;
}
}
/*!
* @brief Configs specified DMA Channel through a structure.
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
*
* @param dmaConfig: Point to a DMA_Config_T structure
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
{
channel->CHCFG_B.DIRCFG = dmaConfig->dir;
channel->CHCFG_B.CIRMODE = dmaConfig->loopMode;
channel->CHCFG_B.PERIMODE = dmaConfig->peripheralInc;
channel->CHCFG_B.MIMODE = dmaConfig->memoryInc;
channel->CHCFG_B.PERSIZE = dmaConfig->peripheralDataSize;
channel->CHCFG_B.MEMSIZE = dmaConfig->memoryDataSize;
channel->CHCFG_B.CHPL = dmaConfig->priority;
channel->CHCFG_B.M2MMODE = dmaConfig->M2M;
channel->CHNDATA = dmaConfig->bufferSize;
channel->CHPADDR = dmaConfig->peripheralBaseAddr;
channel->CHMADDR = dmaConfig->memoryBaseAddr;
}
/*!
* @brief Populate the structure with default values.
*
* @param dmaConfig: Point to a DMA_Config_T structure.
*
* @retval None
*/
void DMA_ConfigStructInit( DMA_Config_T* dmaConfig)
{
dmaConfig->peripheralBaseAddr = 0;
dmaConfig->memoryBaseAddr = 0;
dmaConfig->dir = DMA_DIR_PERIPHERAL_SRC;
dmaConfig->bufferSize = 0;
dmaConfig->peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
dmaConfig->memoryInc = DMA_MEMORY_INC_DISABLE;
dmaConfig->peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_BYTE;
dmaConfig->memoryDataSize = DMA_MEMORY_DATA_SIZE_BYTE;
dmaConfig->loopMode = DMA_MODE_NORMAL;
dmaConfig->priority = DMA_PRIORITY_LOW;
dmaConfig->M2M = DMA_M2MEN_DISABLE;
}
/*!
* @brief Enable the specified DMA Channel
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_Enable(DMA_Channel_T *channel)
{
channel->CHCFG_B.CHEN = ENABLE;
}
/*!
* @brief Disable the specified DMA Channel
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_Disable(DMA_Channel_T *channel)
{
channel->CHCFG_B.CHEN = DISABLE;
}
/*!
* @brief Configs the number of data units in the channel.
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
*
* @param dataNumber:The number of data units in the current DMA Channel transfer.
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber)
{
channel->CHNDATA = dataNumber;
}
/*!
* @brief Read the number of data units in the channel
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
*
* @retval The number of CHNDATA value
*
* @note DMA2 Channel only for APM32 High density devices.
*/
uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel)
{
return channel->CHNDATA;
}
/*!
* @brief Enables the specified DMA Channel interrupts.
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
*
* @param interrupt: DMA interrupts sources to selsct
* This parameter can be any combination of the following values:
* @arg DMA_INT_TC : All Transfer Complete Interrupt
* @arg DMA_INT_HT : Half Transfer Complete Interrupt
* @arg DMA_INT_TERR : Transfer Error Occur Interrupt
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
{
channel->CHCFG |= interrupt;
}
/*!
* @brief Disable the specified DMA Channel interrupts.
*
* @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
*
* @param interrupt: DMA interrupts sources to selsct
* This parameter can be any combination of the following values:
* @arg DMA_INT_TC : All Transfer Complete Interrupt
* @arg DMA_INT_HT : Half Transfer Complete Interrupt
* @arg DMA_INT_TERR : Transfer Error Occur Interrupt
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
{
channel->CHCFG &= ~interrupt;
}
/*!
* @brief Read whether the specifie DMA Channel flag is set or not.
*
* @param flag: the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag.
* @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag.
* @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag.
*
* @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag.
* @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag.
* @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag.
* @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag.
* @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag.
* @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag.
* @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag.
* @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag.
* @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag.
* @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag.
*
* @retval Flag State
*
* @note DMA2 Channel only for APM32 High density devices.
*/
uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
{
if((flag & 0x10000000) != RESET )
{
if((DMA2->INTSTS & flag ) != RESET )
{
return SET ;
} else
{
return RESET ;
}
}
else
{
if((DMA1->INTSTS & flag ) != RESET )
{
return SET ;
} else
{
return RESET ;
}
}
}
/*!
* @brief Clears the specifie DMA Channel's flags.
*
* @param flag:the flag to Clear.
* This parameter can be any combination of the following values:
* @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag.
* @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag.
* @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag.
* @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag.
* @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag.
* @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag.
* @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag.
* @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag.
* @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag.
* @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag.
* @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag.
* @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag.
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_ClearStatusFlag(uint32_t flag)
{
if((flag & 0x10000000) != RESET)
{
DMA2->INTFCLR = flag;
} else
{
DMA1->INTFCLR = flag;
}
}
/*!
* @brief Read whether the specified DMA Channel interrupts is set or not.
*
* @param interrupt: interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt.
* @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt.
* @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt.
* @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt.
* @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt.
* @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt.
* @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt.
* @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt.
* @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt.
* @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt.
* @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt.
* @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt.
* @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt.
*
* @retval interrupt State
*
* @note DMA2 Channel only for APM32 High density devices.
*/
uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
{
if((flag & 0x10000000) != RESET )
{
if((DMA2->INTSTS & flag ) != RESET )
{
return SET ;
} else
{
return RESET ;
}
} else
{
if((DMA1->INTSTS & flag ) != RESET )
{
return SET ;
} else
{
return RESET ;
}
}
}
/*!
* @brief Clears the specified DMA Channel's interrupts.
*
* @param flag: the interrupt flag to Clear.
* This parameter can be any combination of the following values:
* @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt.
* @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt.
* @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt.
* @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt.
* @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt.
* @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt.
* @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt.
* @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt.
* @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt.
* @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt.
* @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt.
* @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt.
* @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt.
* @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt.
* @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt.
* @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt.
* @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt.
* @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt.
*
* @retval None
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_ClearIntFlag(uint32_t flag)
{
if((flag & 0x10000000) != RESET)
{
DMA2->INTFCLR = flag;
} else
{
DMA1->INTFCLR = flag;
}
}
/**@} end of group DMA_Fuctions*/
/**@} end of group DMA_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c
+464
View File
@@ -0,0 +1,464 @@
/*!
* @file apm32f10x_dmc.c
*
* @brief This file contains all the functions for the DMC controler peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifdef APM32F10X_HD
#include "apm32f10x_dmc.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup DMC_Driver DMC Driver
@{
*/
/** @addtogroup DMC_Fuctions Fuctions
@{
*/
/*!
* @brief DMC controler configuration
*
* @param dmcConfig: pointer to a DMC_Config_T structure
*
* @retval None
*/
void DMC_Config(DMC_Config_T * dmcConfig)
{
DMC->SW_B.MCSW = 1;
while(!DMC->CTRL1_B.INIT);
DMC->CFG_B.BAWCFG = dmcConfig->bankWidth;
DMC->CFG_B.RAWCFG = dmcConfig->rowWidth;
DMC->CFG_B.CAWCFG = dmcConfig->colWidth;
DMC->MASK_B.MSIZESEL = dmcConfig->memorySize;
DMC->CTRL2_B.CPHACFG = dmcConfig->clkPhase;
DMC_ConfigTiming(&dmcConfig->timing);
DMC->CTRL1_B.MODESET = 1;
while(!DMC->CTRL1_B.MODESET);
DMC->CTRL2_B.RDDEN = 1;
DMC->CTRL2_B.RDDCFG = 7;
}
/*!
* @brief Fills each dmcConfig member with its default value
*
* @param dmcConfig: pointer to a DMC_Config_T structure
*
* @retval None
*/
void DMC_ConfigStructInit(DMC_Config_T * dmcConfig)
{
dmcConfig->bankWidth = DMC_BANK_WIDTH_2;
dmcConfig->clkPhase = DMC_CLK_PHASE_REVERSE;
dmcConfig->colWidth = DMC_COL_WIDTH_10;
dmcConfig->rowWidth = DMC_ROW_WIDTH_13;
dmcConfig->memorySize = DMC_MEMORY_SIZE_8MB;
DMC_ConfigTimingStructInit(&dmcConfig->timing);
}
/*!
* @brief Timing configuration
*
* @param timingConfig: pointer to a DMC_TimingConfig_T structure
*
* @retval None
*/
void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig)
{
DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS;
DMC->TIM0_B.DTIMSEL = timingConfig->tRCD;
DMC->TIM0_B.PCPSEL = timingConfig->tRP;
DMC->TIM0_B.WRTIMSEL = timingConfig->tWR;
DMC->TIM0_B.ARPSEL = timingConfig->tARP;
DMC->TIM0_B.ATACP = timingConfig->tCMD;
DMC->TIM0_B.CASLSEL0 = timingConfig->latencyCAS & 0x03;
DMC->TIM0_B.ECASLSEL1 = (timingConfig->latencyCAS >> 2) & 0x01;
DMC->TIM0_B.XSR0 = timingConfig->tXSR & 0X0F;
DMC->TIM0_B.EXSR1 = (timingConfig->tXSR >> 4) & 0X1F;
DMC->REF_B.RCYCCFG = timingConfig->tRFP;
}
/*!
* @brief Fills each config member with its default value
*
* @param timingConfig: pointer to a DMC_TimingConfig_T structure
*
* @retval None
*/
void DMC_ConfigTimingStructInit(DMC_TimingConfig_T * timingConfig)
{
timingConfig->latencyCAS = DMC_CAS_LATENCY_3;
timingConfig->tARP = DMC_AUTO_REFRESH_10;
timingConfig->tRAS = DMC_RAS_MINIMUM_5;
timingConfig->tCMD = DMC_ATA_CMD_7;
timingConfig->tRCD = DMC_DELAY_TIME_2;
timingConfig->tRP = DMC_PRECHARGE_2;
timingConfig->tWR = DMC_NEXT_PRECHARGE_2;
timingConfig->tXSR = 6;
timingConfig->tRFP = 0xC3;
}
/*!
* @brief Set number of bank bits
*
* @param bankWidth: Specifies the bank bits number
* This parameter can be one of the following values:
* @arg DMC_BANK_WIDTH_1
* @arg DMC_BANK_WIDTH_2
* @retval None
*/
void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth)
{
DMC->CFG_B.BAWCFG = bankWidth;
}
/*!
* @brief Set address bus width
*
* @param rowWidth: Specifies the row address bits number
* This parameter can be one of the following values:
* @arg DMC_ROW_WIDTH_11
* @arg DMC_ROW_WIDTH_12
* @arg DMC_ROW_WIDTH_13
* @arg DMC_ROW_WIDTH_14
* @arg DMC_ROW_WIDTH_15
* @arg DMC_ROW_WIDTH_16
* @param colWidth: Specifies the column address bits number
* This parameter can be one of the following values:
* @arg DMC_COL_WIDTH_8
* @arg DMC_COL_WIDTH_9
* @arg DMC_COL_WIDTH_10
* @arg DMC_COL_WIDTH_11
* @arg DMC_COL_WIDTH_12
* @arg DMC_COL_WIDTH_13
* @arg DMC_COL_WIDTH_14
* @arg DMC_COL_WIDTH_15
* @retval None
*/
void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth)
{
DMC->CFG_B.RAWCFG = rowWidth;
DMC->CFG_B.CAWCFG = colWidth;
}
/*!
* @brief Set stable time after power up
*
* @param stableTime: Numper of the clock, can be 0x0000 to 0xFFFF
*
* @retval None
*/
void DMC_ConfigStableTimePowerup(uint16_t stableTime)
{
DMC->TIM1_B.STBTIM = stableTime;
}
/*!
* @brief Number of auto-refreshes during initialization
*
* @param num: Number of auto-refreshes can 1 to 16
* This parameter can be one of the following values:
* @arg DMC_AUTO_REFRESH_1
* @arg DMC_AUTO_REFRESH_2
* ......
* @arg DMC_AUTO_REFRESH_15
* @arg DMC_AUTO_REFRESH_16
*
* @retval None
*/
void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num)
{
DMC->TIM1_B.ARNUMCFG = num;
}
/*!
* @brief Number of DMC internal banks to be open at any time;
*
* @param num: Number of banks can 1 to 16
* This parameter can be one of the following values:
* @arg DMC_BANK_NUMBER_1
* @arg DMC_BANK_NUMBER_2
* ......
* @arg DMC_BANK_NUMBER_15
* @arg DMC_BANK_NUMBER_16
* @retval None
*/
void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num)
{
DMC->CTRL1_B.BANKNUMCFG = num;
}
/*!
* @brief Read self-refresh status
*
* @param None
*
* @retval The status of self-refresh (SET or RESET)
*/
uint8_t DMC_ReadSelfRefreshStatus(void)
{
uint8_t ret;
ret = DMC->CTRL1_B.SRMFLG ? SET : RESET;
return ret;
}
/*!
* @brief Set update mode bit
*
* @param None
*
* @retval None
*/
void DMC_EnableUpdateMode(void)
{
DMC->CTRL1_B.MODESET = 1;
}
/*!
* @brief Enter power down mode
*
* @param None
*
* @retval None
*/
void DMC_EnterPowerdownMode(void)
{
DMC->CTRL1_B.PDMEN = 1;
}
/*!
* @brief Exit self-refresh mode
*
* @param None
*
* @retval None
*/
void DMC_EixtSlefRefreshMode(void)
{
DMC->CTRL1_B.SRMEN = 0;
}
/*!
* @brief Enter self-refresh mode
*
* @param None
*
* @retval None
*/
void DMC_EnterSlefRefreshMode(void)
{
DMC->CTRL1_B.SRMEN = 1;
}
/*!
* @brief Enable Accelerate Module
*
* @param None
*
* @retval None
*/
void DMC_EnableAccelerateModule(void)
{
DMC->CTRL2_B.BUFFEN = BIT_SET;
}
/*!
* @brief Disable Accelerate Module
*
* @param None
*
* @retval None
*/
void DMC_DisableAccelerateModule(void)
{
DMC->CTRL2_B.BUFFEN = BIT_RESET;
}
/*!
* @brief Init DMC
*
* @param None
*
* @retval None
*/
void DMC_EnableInit(void)
{
DMC->CTRL1_B.INIT = 1;
}
/*!
* @brief Set refresh type before enter self-refresh
*
* @param refresh: Specifies the refresh type
* The parameter can be one of following values:
* @arg DMC_REFRESH_ROW_ONE: Refresh one row
* @arg DMC_REFRESH_ROW_ALL: Refresh all row
*
* @retval None
*/
void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh)
{
DMC->CTRL1_B.FRBSREN = refresh;
}
/*!
* @brief Set refresh type after exit self-refresh
*
* @param refresh: Specifies the refresh type
* The parameter can be one of following values:
* @arg DMC_REFRESH_ROW_ONE: Refresh one row
* @arg DMC_REFRESH_ROW_ALL: Refresh all row
*
* @retval None
*/
void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh)
{
DMC->CTRL1_B.FRASREN = refresh;
}
/*!
* @brief Config precharge type
*
* @param precharge: Specifies the precharge type
* The parameter can be one of following values:
* @arg DMC_PRECHARGE_IM: Immediate precharge
* @arg DMC_PRECHARGE_DELAY: Delayed precharge
*
* @retval None
*/
void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge)
{
DMC->CTRL1_B.PCACFG = precharge;
}
/*!
* @brief Config refresh period
*
* @param period: Specifies the refresh period, can be 0x0000 to 0xFFFF
*
* @retval None
*/
void DMC_ConfigRefreshPeriod(uint16_t period)
{
DMC->REF_B.RCYCCFG = period;
}
/*!
* @brief Config memory size
*
* @param memorySize: Specifies memory size
* The parameter can be one of following values:
* @arg DMC_MEMORY_SIZE_0: Memory size is no link
* @arg DMC_MEMORY_SIZE_64KB: Memory size is 64KB
* @arg DMC_MEMORY_SIZE_128KB: Memory size is 128KB
* @arg DMC_MEMORY_SIZE_256KB: Memory size is 256KB
* @arg DMC_MEMORY_SIZE_512KB: Memory size is 512KB
* @arg DMC_MEMORY_SIZE_1MB: Memory size is 1MB
* @arg DMC_MEMORY_SIZE_2MB: Memory size is 2MB
* @arg DMC_MEMORY_SIZE_4MB: Memory size is 4MB
* @arg DMC_MEMORY_SIZE_8MB: Memory size is 8MB
* @arg DMC_MEMORY_SIZE_16MB: Memory size is 16MB
* @arg DMC_MEMORY_SIZE_32MB: Memory size is 32MB
* @arg DMC_MEMORY_SIZE_64MB: Memory size is 64MB
* @arg DMC_MEMORY_SIZE_128MB: Memory size is 128MB
* @arg DMC_MEMORY_SIZE_256MB: Memory size is 256MB
*
* @retval None
*/
void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize)
{
DMC->MASK_B.MSIZESEL = memorySize;
}
/*!
* @brief Enable DMC controler
*
* @param None
*
* @retval None
*/
void DMC_Enable(void)
{
DMC->SW_B.MCSW = 1;
}
/*!
* @brief Disable DMC controler
*
* @param None
*
* @retval None
*/
void DMC_Disable(void)
{
DMC->SW_B.MCSW = 0;
}
/*!
* @brief Set DMC clock phase
*
* @param clkPhase: Specifies clock phase
* The parameter can be one of following values:
* @arg DMC_CLK_PHASE_NORMAL: Clock phase is normal
* @arg DMC_CLK_PHASE_REVERSE: Clock phase is reverse
*
* @retval None
*/
void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase)
{
DMC->CTRL2_B.CPHACFG = clkPhase;
}
/*!
* @brief Set DMC WRAP burst
*
* @param burst: WRAP burst Type Selection
* The parameter can be one of following values:
* @arg DMC_WRAPB_4: wrap4 burst transfer
* @arg DMC_WRAPB_8: wrap8 burst transfer
*
* @retval None
*/
void DMC_ConfigWRAPB(DMC_WRPB_T burst)
{
DMC->CTRL2_B.WRPBSEL = burst;
}
#endif //defined APM32F10X_HD
/**@} end of group DMC_Fuctions*/
/**@} end of group DMC_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c
+205
View File
@@ -0,0 +1,205 @@
/*!
* @file apm32f10x_eint.c
*
* @brief This file provides all the EINT firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_eint.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup EINT_Driver EINT Driver
@{
*/
/** @addtogroup EINT_Fuctions Fuctions
@{
*/
/*!
* @brief Reset the EINT peripheral registers to their default reset values.
*
* @param None
*
* @retval None
*/
void EINT_Reset(void)
{
EINT->IMASK = 0x00000000;
EINT->EMASK = 0x00000000;
EINT->RTEN = 0x00000000;
EINT->FTEN = 0x00000000;
EINT->IPEND = 0x000FFFFF;
}
/*!
* @brief Configure the EINT
*
* @param eintConfig: pointer to a EINT_Config_T structure.
*
* @retval None
*/
void EINT_Config(EINT_Config_T* eintConfig)
{
uint32_t temp = 0;
temp = (uint32_t)EINT_BASE;
if(eintConfig->lineCmd != DISABLE)
{
EINT->IMASK &= ~eintConfig->line;
EINT->EMASK &= ~eintConfig->line;
temp += eintConfig->mode;
*(__IOM uint32_t *) temp |= eintConfig->line;
EINT->RTEN &= ~eintConfig->line;
EINT->FTEN &= ~eintConfig->line;
if (eintConfig->trigger == EINT_TRIGGER_RISING_FALLING)
{
EINT->RTEN |= eintConfig->line;
EINT->FTEN |= eintConfig->line;
}
else
{
temp = (uint32_t)EINT_BASE;
temp += eintConfig->trigger;
*(__IOM uint32_t *) temp |= eintConfig->line;
}
}
else
{
temp += eintConfig->mode;
*(__IOM uint32_t *) temp &= ~eintConfig->line;
}
}
/*!
* @brief Fills each EINT_Config_T member with its reset value.
*
* @param eintConfig: pointer to a EINT_Config_T structure
*
* @retval None
*/
void EINT_ConfigStructInit(EINT_Config_T* eintConfig)
{
eintConfig->line = EINT_LINENONE;
eintConfig->mode = EINT_MODE_INTERRUPT;
eintConfig->trigger = EINT_TRIGGER_FALLING;
eintConfig->lineCmd = DISABLE;
}
/*!
* @brief Select Software interrupt on EINT line
*
* @param line: specifies the EINT lines.
* This parameter can be any combination of EINT_LINE_T(can be from 0 to 18)
*
* @retval None
*/
void EINT_SelectSWInterrupt(uint32_t line)
{
EINT->SWINTE |= line;
}
/*!
* @brief Read the specified EINT_Line flag
*
* @param line: Select the EINT_Line.
* This parameter can be one of EINT_LINE_T(can be from 0 to 18)
*
* @retval status: The new state of flag (SET or RESET)
*/
uint8_t EINT_ReadStatusFlag(EINT_LINE_T line)
{
uint8_t status = RESET;
if((EINT->IPEND & line) != (uint32_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/*!
* @brief Clears the EINT_Line pending bits
*
* @param line: Select the EINT_Line.
* This parameter can be any combination of EINT_LINE_T(can be from 0 to 18)
*
* @retval None
*/
void EINT_ClearStatusFlag(uint32_t line)
{
EINT->IPEND = line;
}
/*!
* @brief Read the specified EINT_Line Interrupt Flag.
*
* @param line: Select the EINT_Line.
* This parameter can be one of EINT_LINE_T(can be from 0 to 18)
*
* @retval None
*/
uint8_t EINT_ReadIntFlag(EINT_LINE_T line)
{
uint8_t status = RESET;
uint32_t enablestatus = 0;
enablestatus = EINT->IMASK & line;
if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/*!
* @brief Clears the EINT_Line pending bits
*
* @param line: Select the EINT_Line
* This parameter can be any combination of EINT_LINE_T(can be from 0 to 18)
*
* @retval None
*/
void EINT_ClearIntFlag(uint32_t line)
{
EINT->IPEND = line;
}
/**@} end of group EINT_Fuctions*/
/**@} end of group EINT_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c
+747
View File
@@ -0,0 +1,747 @@
/*!
* @file apm32f10x_emmc.c
*
* @brief This file provides all the EMMC firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_emmc.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup EMMC_Driver EMMC Driver
@{
*/
/** @addtogroup EMMC_Fuctions Fuctions
@{
*/
/*!
* @brief Rest the EMMMC NOR/SRAM Banks registers
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1
* @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2
* @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3
* @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4
*
* @retval None
*/
void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
{
/** EMMC_BANK1_NORSRAM_1 */
if(bank == EMMC_BANK1_NORSRAM_1)
{
EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB;
}
/** EMMC_BANK1_NORSRAM_2, EMMC_BANK1_NORSRAM_3 or EMMC_BANK1_NORSRAM_4 */
else
{
EMMC_Bank1->SNCTRL_T[bank] = 0x000030D2;
}
EMMC_Bank1->SNCTRL_T[bank + 1] = 0x0FFFFFFF;
EMMC_Bank1E->WRTTIM[bank] = 0x0FFFFFFF;
}
/*!
* @brief Rest the EMMMC NAND Banks registers
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
*
* @retval None
*/
void EMMC_ResetNAND(EMMC_BANK_NAND_T bank)
{
if(bank == EMMC_BANK2_NAND)
{
/** Set the EMMC_Bank2 registers to their reset values */
EMMC_Bank2->CTRL2 = 0x00000018;
EMMC_Bank2->STSINT2 = 0x00000040;
EMMC_Bank2->CMSTIM2 = 0xFCFCFCFC;
EMMC_Bank2->AMSTIM2 = 0xFCFCFCFC;
}
/** EMMC_BANK3_NAND */
else
{
/** Set the EMMC_Bank3 registers to their reset values */
EMMC_Bank3->CTRL3 = 0x00000018;
EMMC_Bank3->STSINT3 = 0x00000040;
EMMC_Bank3->CMSTIM3 = 0xFCFCFCFC;
EMMC_Bank3->AMSTIM3 = 0xFCFCFCFC;
}
}
/*!
* @brief Reset the EMMMC PCCARD Banks registers
*
* @param None
*
* @retval None
*/
void EMMC_ResetPCCard(void)
{
/** Set the EMMC_Bank4 registers to their reset values */
EMMC_Bank4->CTRL4 = 0x00000018;
EMMC_Bank4->STSINT4 = 0x00000040;
EMMC_Bank4->CMSTIM4 = 0xFCFCFCFC;
EMMC_Bank4->AMSTIM4 = 0xFCFCFCFC;
EMMC_Bank4->IOSTIM4 = 0xFCFCFCFC;
}
/*!
* @brief Config the EMMC NOR/SRAM Banks according to the specified parameters in the emmcNORSRAMConfig.
*
* @param emmcNORSRAMConfig: Point to a EMMC_NORSRAMConfig_T structure
*
* @retval None
*/
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
{
/** Bank1 NOR/SRAM control register configuration */
EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] =
(uint32_t)emmcNORSRAMConfig->dataAddressMux |
emmcNORSRAMConfig->memoryType |
emmcNORSRAMConfig->memoryDataWidth |
emmcNORSRAMConfig->burstAcceesMode |
emmcNORSRAMConfig->asynchronousWait |
emmcNORSRAMConfig->waitSignalPolarity |
emmcNORSRAMConfig->wrapMode |
emmcNORSRAMConfig->waitSignalActive |
emmcNORSRAMConfig->writeOperation |
emmcNORSRAMConfig->waiteSignal |
emmcNORSRAMConfig->extendedMode |
emmcNORSRAMConfig->writeBurst;
if(emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
{
EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040;
}
/** Bank1 NOR/SRAM timing register configuration */
EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank + 1] =
(uint32_t)emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime |
(emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) |
(emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime << 8) |
(emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime << 16) |
(emmcNORSRAMConfig->readWriteTimingStruct->clockDivision << 20) |
(emmcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) |
emmcNORSRAMConfig->readWriteTimingStruct->accessMode;
/** Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if(emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
{
EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] =
(uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime |
(emmcNORSRAMConfig->writeTimingStruct->addressHodeTime << 4) |
(emmcNORSRAMConfig->writeTimingStruct->dataSetupTime << 8) |
(emmcNORSRAMConfig->writeTimingStruct->clockDivision << 20) |
(emmcNORSRAMConfig->writeTimingStruct->dataLatency << 24) |
emmcNORSRAMConfig->writeTimingStruct->accessMode;
}
else
{
EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] = 0x0FFFFFFF;
}
}
/*!
* @brief Config the EMMC NAND Banks according to the specified parameters in the emmcNANDConfig.
*
* @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure.
*
* @retval None
*/
void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
{
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
/** Set the tmppcr value according to EMMC_NANDInitStruct parameters */
tmppcr = (uint32_t)emmcNANDConfig->waitFeature | 0x00000008 |
emmcNANDConfig->memoryDataWidth |
emmcNANDConfig->ECC |
emmcNANDConfig->ECCPageSize |
(emmcNANDConfig->TCLRSetupTime << 9) |
(emmcNANDConfig->TARSetupTime << 13);
/** Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */
tmppmem = (uint32_t)emmcNANDConfig->commonSpaceTimingStruct->setupTime |
(emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
(emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
(emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
/** Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */
tmppatt = (uint32_t)emmcNANDConfig->attributeSpaceTimingStruct->setupTime |
(emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
(emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
(emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
if(emmcNANDConfig->bank == EMMC_BANK2_NAND)
{
/** EMMC_BANK2_NAND registers configuration */
EMMC_Bank2->CTRL2 = tmppcr;
EMMC_Bank2->CMSTIM2 = tmppmem;
EMMC_Bank2->AMSTIM2 = tmppatt;
}
else
{
/** EMMC_BANK3_NAND registers configuration */
EMMC_Bank3->CTRL3 = tmppcr;
EMMC_Bank3->CMSTIM3 = tmppmem;
EMMC_Bank3->AMSTIM3 = tmppatt;
}
}
/*!
* @brief Config the EMMC PCCARD according to the specified parameters in the emmcPCCardConfig.
*
* @param emmcPCCardConfig: Point to a EMMC_PCCARDConfig_T structure.
*
* @retval None
*/
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig)
{
/** Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */
EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT |
(emmcPCCardConfig->TCLRSetupTime << 9) |
(emmcPCCardConfig->TARSetupTime << 13);
/** Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */
EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime |
(emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
/** Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */
EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime |
(emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
/** Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */
EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime |
(emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
}
/*!
* @brief Fills each emmcNORSRAMConfig member with its default value.
*
* @param emmcNORSRAMConfig : Point to a EMMC_NORSRAMConfig_T structure.
*
* @retval None
*/
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
{
/** Reset NOR/SRAM Init structure parameters values */
emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1;
emmcNORSRAMConfig->dataAddressMux = EMMC_DATA_ADDRESS_MUX_ENABLE;
emmcNORSRAMConfig->memoryType = EMMC_MEMORY_TYPE_SRAM;
emmcNORSRAMConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT;
emmcNORSRAMConfig->burstAcceesMode = EMMC_BURST_ACCESS_MODE_DISABLE;
emmcNORSRAMConfig->asynchronousWait = EMMC_ASYNCHRONOUS_WAIT_DISABLE;
emmcNORSRAMConfig->waitSignalPolarity = EMMC_WAIT_SIGNAL_POLARITY_LOW;
emmcNORSRAMConfig->wrapMode = EMMC_WRAP_MODE_DISABLE;
emmcNORSRAMConfig->waitSignalActive = EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT;
emmcNORSRAMConfig->writeOperation = EMMC_WRITE_OPERATION_ENABLE;
emmcNORSRAMConfig->waiteSignal = EMMC_WAITE_SIGNAL_ENABLE;
emmcNORSRAMConfig->extendedMode = EMMC_EXTENDEN_MODE_DISABLE;
emmcNORSRAMConfig->writeBurst = EMMC_WRITE_BURST_DISABLE;
emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF;
emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF;
emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF;
emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF;
emmcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF;
emmcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF;
emmcNORSRAMConfig->readWriteTimingStruct->accessMode = EMMC_ACCESS_MODE_A;
emmcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF;
emmcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF;
emmcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF;
emmcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF;
emmcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF;
emmcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF;
emmcNORSRAMConfig->writeTimingStruct->accessMode = EMMC_ACCESS_MODE_A;
}
/*!
* @brief Fills each emmcNANDConfig member with its default value.
*
* @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure.
*
* @retval None
*/
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig)
{
/** Reset NAND Init structure parameters values */
emmcNANDConfig->bank = EMMC_BANK2_NAND;
emmcNANDConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
emmcNANDConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT;
emmcNANDConfig->ECC = EMMC_ECC_DISABLE;
emmcNANDConfig->ECCPageSize = EMMC_ECC_PAGE_SIZE_BYTE_256;
emmcNANDConfig->TCLRSetupTime = 0x0;
emmcNANDConfig->TARSetupTime = 0x0;
emmcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC;
emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
emmcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
}
/*!
* @brief Fills each emmcPCCardConfig member with its default value.
*
* @param emmcPCCardConfig : Point to a EMMC_PCCARDConfig_T structure.
*
* @retval None
*/
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig)
{
/** Reset PCCARD Init structure parameters values */
emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
emmcPCCardConfig->TCLRSetupTime = 0x0;
emmcPCCardConfig->TARSetupTime = 0x0;
emmcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC;
emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
emmcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
emmcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC;
emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC;
emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC;
emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC;
}
/*!
* @brief Enables the specified NOR/SRAM Memory Bank.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1
* @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2
* @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3
* @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4
*
* @retval None
*/
void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank)
{
EMMC_Bank1->SNCTRL_T[bank] |= 0x00000001;
}
/*!
* @brief Disbles the specified NOR/SRAM Memory Bank.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1
* @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2
* @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3
* @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4
*
* @retval None
*/
void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank)
{
EMMC_Bank1->SNCTRL_T[bank] &= 0x000FFFFE;
}
/*!
* @brief Enables the specified NAND Memory Bank.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
*
* @retval None
*/
void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
}
else
{
EMMC_Bank3->CTRL3_B.MBKEN = BIT_SET;
}
}
/*!
* @brief Disbles the specified NAND Memory Bank.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
*
* @retval None
*/
void EMMC_DisableNAND(EMMC_BANK_NAND_T bank)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
}
else
{
EMMC_Bank3->CTRL3_B.MBKEN = BIT_RESET;
}
}
/*!
* @brief Enables the specified PC Card Memory Bank.
*
* @param None
*
* @retval None
*/
void EMMC_EnablePCCARD(void)
{
EMMC_Bank4->CTRL4_B.MBKEN = BIT_SET;
}
/*!
* @brief Disables the specified PC Card Memory Bank.
*
* @param None
*
* @retval None
*/
void EMMC_DisablePCCARD(void)
{
EMMC_Bank4->CTRL4_B.MBKEN = BIT_RESET;
}
/*!
* @brief Enbles the EMMC NAND ECC feature.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
*
* @retval None
*/
void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2 |= 0x00000040;
}
else
{
EMMC_Bank3->CTRL3 |= 0x00000040;
}
}
/*!
* @brief Disbles or disables the EMMC NAND ECC feature.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
*
* @retval None
*
*/
void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2 &= 0x000FFFBF;
}
else
{
EMMC_Bank3->CTRL3 &= 0x000FFFBF;
}
}
/*!
* @brief Read the error correction code register value.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
*
* @retval The value of Error Correction Code (ECC).
*/
uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank)
{
uint32_t eccval = 0x00000000;
if(bank == EMMC_BANK2_NAND)
{
eccval = EMMC_Bank2->ECCRS2;
}
else
{
eccval = EMMC_Bank3->ECCRS3;
}
return eccval;
}
/*!
* @brief Enables the specified EMMC interrupts.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
* @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
*
* @param interrupt: Select the EMMC interrupt sources.
* This parameter can be any combination of the following values:
* @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
* @arg EMMC_INT_LEVEL_HIGH : High level detection interrupt.
* @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
*
* @retval None
*/
void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 |= interrupt;
}
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 |= interrupt;
}
else
{
EMMC_Bank4->STSINT4 |= interrupt;
}
}
/*!
* @brief Enables the specified EMMC interrupts.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
* @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
*
* @param interrupt: Select the EMMC interrupt sources.
* This parameter can be any combination of the following values:
* @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
* @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt.
* @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
*
* @retval None
*/
void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 &= ~interrupt;
}
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 &= ~interrupt;
}
else
{
EMMC_Bank4->STSINT4 &= ~interrupt;
}
}
/*!
* @brief Read the status of specified EMMC flag.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
* @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
*
* @param flag: Select the EMMC interrupt sources.
* This parameter can be one of the following values:
* @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag.
* @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag.
* @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
* @arg EMMC_FLAG_FIFO_EMPTY : FIFO empty Flag.
*
* @retval SET or RESET
*
*/
uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
{
uint32_t tmpsr = 0x00000000;
if(bank == EMMC_BANK2_NAND)
{
tmpsr = EMMC_Bank2->STSINT2;
}
else if(bank == EMMC_BANK3_NAND)
{
tmpsr = EMMC_Bank3->STSINT3;
}
else
{
tmpsr = EMMC_Bank4->STSINT4;
}
/** Get the flag status */
if((tmpsr & flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*!
* @brief Clears the EMMC's pending flags.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
* @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
*
* @param flag: Select the EMMC interrupt sources.
* This parameter can be any combination of the following values:
* @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag.
* @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag.
* @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
*
* @retval None
*/
void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 &= ~flag;
}
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 &= ~flag;
}
else
{
EMMC_Bank4->STSINT4 &= ~flag;
}
}
/*!
* @brief Read the specified EMMC interrupt has occurred or not.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
* @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
*
* @param interrupt: Select the EMMC interrupt source.
* This parameter can be one of the following values:
* @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
* @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt.
* @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
*
* @retval The status of specified EMMC interrupt source.
*/
uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
{
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
if(bank == EMMC_BANK2_NAND)
{
tmpsr = EMMC_Bank2->STSINT2;
}
else if(bank == EMMC_BANK3_NAND)
{
tmpsr = EMMC_Bank3->STSINT3;
}
else
{
tmpsr = EMMC_Bank4->STSINT4;
}
itstatus = tmpsr & flag;
itenable = tmpsr & (flag >> 3);
if((itstatus != RESET) && (itenable != RESET))
{
return SET;
}
else
{
return RESET;
}
}
/*!
* @brief Clears the EMMC's interrupt Flag.
*
* @param bank: Selects the EMMMC Bank.
* The parameter can be one of following values:
* @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
* @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
* @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
*
* @param interrupt: Select the EMMC interrupt sources.
* This parameter can be any combination of the following values:
* @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
* @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt.
* @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
*
* @retval None
*/
void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
{
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 &= ~(flag >> 3);
}
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 &= ~(flag >> 3);
}
else
{
EMMC_Bank4->STSINT4 &= ~(flag >> 3);
}
}
/**@} end of group EMMC_Fuctions*/
/**@} end of group EMMC_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c
+768
View File
@@ -0,0 +1,768 @@
/*!
* @file apm32f10x_fmc.c
*
* @brief This file provides all the FMC firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_fmc.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup FMC_Driver FMC Driver
@{
*/
/** @addtogroup FMC_Fuctions Fuctions
@{
*/
/*!
* @brief Configs the code latency value.
*
* @param latency: the FMC Latency value.
*
* @retval None
*/
void FMC_ConfigLatency(FMC_LATENCY_T latency)
{
FMC->CTRL1_B.WS = latency;
}
/*!
* @brief Enables the Half cycle flash access.
*
* @param None
*
* @retval None
*/
void FMC_EnableHalfCycleAccess(void)
{
FMC->CTRL1_B.HCAEN = BIT_SET;
}
/*!
* @brief Disable the Half cycle flash access.
*
* @param None
*
* @retval None
*/
void FMC_DisableHalfCycleAccess(void)
{
FMC->CTRL1_B.HCAEN = BIT_RESET;
}
/*!
* @brief Enables the Prefetch Buffer.
*
* @param None
*
* @retval None
*/
void FMC_EnablePrefetchBuffer(void)
{
FMC->CTRL1_B.PBEN = ENABLE;
}
/*!
* @brief Disables the Prefetch Buffer.
*
* @param None
*
* @retval None
*/
void FMC_DisablePrefetchBuffer(void)
{
FMC->CTRL1_B.PBEN = DISABLE;
}
/*!
* @brief Unlocks the FMC Program Erase Controller
*
* @param None
*
* @retval None
*/
void FMC_Unlock(void)
{
FMC->KEY = 0x45670123;
FMC->KEY = 0xCDEF89AB;
}
/*!
* @brief Locks the FMC Program Erase Controller.
*
* @param None
*
* @retval None
*/
void FMC_Lock(void)
{
FMC->CTRL2_B.LOCK = BIT_SET;
}
/*!
* @brief Erases a specified FMC page.
*
* @param pageAddr: The page address to be erased.
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_BUSY
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.PAGEERA = BIT_SET;
FMC->ADDR = pageAddr;
FMC->CTRL2_B.STA = BIT_SET;
status = FMC_WaitForLastOperation(0x000B0000);
FMC->CTRL2_B.PAGEERA = BIT_RESET;
}
return status;
}
/*!
* @brief Erases all FMC pages.
*
* @param None
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_EraseAllPage(void)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.MASSERA = BIT_SET;
FMC->CTRL2_B.STA = BIT_SET;
status = FMC_WaitForLastOperation(0x000B0000);
FMC->CTRL2_B.MASSERA = BIT_RESET;
}
return status;
}
/*!
* @brief Erases the FMC option bytes.
*
* @param None
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_EraseOptionBytes(void)
{
uint16_t rdtemp = 0x00A5;
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
if(FMC_GetReadProtectionStatus() != RESET)
{
rdtemp = 0x00;
}
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
FMC->CTRL2_B.OBE = BIT_SET;
FMC->CTRL2_B.STA = BIT_SET;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBE = BIT_RESET;
FMC->CTRL2_B.OBP = BIT_SET;
OB->RDP = rdtemp;
status = FMC_WaitForLastOperation(0x000B0000);
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
else if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
return status;
}
/*!
* @brief Programs a word at a specified address.
*
* @param address:the address to be programmed.
*
* @param data: the data to be programmed.
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
__IOM uint32_t temp = 0;
#ifdef APM32F10X_HD
__set_PRIMASK(1);
#endif
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.PG = BIT_SET;
*(__IOM uint16_t *)address = data;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
temp = address + 2;
*(__IOM uint16_t*) temp = data >> 16;
status = FMC_WaitForLastOperation(0x000B0000);
FMC->CTRL2_B.PG = BIT_RESET;
}
else
{
FMC->CTRL2_B.PG = BIT_RESET;
}
}
#ifdef APM32F10X_HD
__set_PRIMASK(0);
#endif
return status;
}
/*!
* @brief Programs a half word at a specified address.
*
* @param address:the address to be programmed.
*
* @param data: the data to be programmed.
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
#ifdef APM32F10X_HD
__set_PRIMASK(1);
#endif
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.PG = BIT_SET;
*(__IOM uint16_t *)address = data;
status = FMC_WaitForLastOperation(0x000B0000);
FMC->CTRL2_B.PG = BIT_RESET;
}
#ifdef APM32F10X_HD
__set_PRIMASK(0);
#endif
return status;
}
/*!
* @brief Programs a half word at a specified Option Byte Data address.
*
* @param address:the address to be programmed.
*
* @param data: the data to be programmed.
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
FMC->CTRL2_B.OBP = BIT_SET;
*(__IOM uint16_t *)address = data;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
return status;
}
/*!
* @brief Write protects the desired pages
*
* @param page:the address of the pages to be write protection
* This parameter can be any combination of the following values:
* for APM32F10X_LD £º
* @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31
* for APM32F10X_MD £º
* @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127
* for APM32F10X_HD £º
* @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127
* @arg FMC_WRP_PAGE_ALL
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page)
{
uint16_t WPP0_Data = 0xFFFF, WPP1_Data = 0xFFFF, WPP2_Data = 0xFFFF, WPP3_Data = 0xFFFF;
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
page = ~page;
WPP0_Data = (page & 0x000000FF);
WPP1_Data = (page & 0x0000FF00) >> 8;
WPP2_Data = (page & 0x00FF0000) >> 16;
WPP3_Data = (page & 0xFF000000) >> 24;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
FMC->CTRL2_B.OBP = BIT_SET;
if(WPP0_Data != 0xFF)
{
OB->WRP0 = WPP0_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF))
{
OB->WRP1 = WPP1_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF))
{
OB->WRP2 = WPP2_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF))
{
OB->WRP3 = WPP3_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
return status;
}
/*!
* @brief Enables the read out protection.
*
* @param None
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_EnableReadOutProtection(void)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
FMC->CTRL2_B.OBE = BIT_SET;
FMC->CTRL2_B.STA = BIT_SET;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBE = BIT_RESET;
FMC->CTRL2_B.OBP = BIT_SET;
OB->RDP = 0x00A5;
status = FMC_WaitForLastOperation(0x000B0000);
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
else if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBE = BIT_RESET;
}
}
return status;
}
/*!
* @brief Disables the read out protection.
*
* @param None
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_DisableReadOutProtection(void)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
FMC->CTRL2_B.OBE = BIT_SET;
FMC->CTRL2_B.STA = BIT_SET;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBE = BIT_RESET;
FMC->CTRL2_B.OBP = BIT_SET;
OB->RDP = 0x00;
status = FMC_WaitForLastOperation(0x000B0000);
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
else if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBE = BIT_RESET;
}
}
return status;
}
/*!
* @brief Programs the FMC User Option Byte.
*
* @param userConfig: Point to a FMC_UserConfig_T structure.
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBP = BIT_SET;
OB->USER = (uint32_t)userConfig->iwdtSet | \
(uint32_t)userConfig->stopSet | \
(uint32_t)userConfig->stdbySet | 0xF8;
status = FMC_WaitForLastOperation(0x000B0000);
if(status == FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
return status;
}
/*!
* @brief Read the FMC User Option Bytes values.
*
* @param None
*
* @retval Returns User Option Bytes values
*/
uint32_t FMC_ReadUserOptionByte(void)
{
return (FMC->OBCS_B.UOB >> 2);
}
/*!
* @brief Read the FMC Write Protection Option Bytes Register value.
*
* @param None
*
* @retval Returns the value of Option Bytes Write Protection Register.
*/
uint32_t FMC_ReadOptionByteWriteProtection(void)
{
return FMC->WRTPROT;
}
/*!
* @brief Get the FMC Read Out Protection Status is set or not.
*
* @param None
*
* @retval status : set or reset.
*/
uint8_t FMC_GetReadProtectionStatus(void)
{
uint8_t flagstatus = RESET;
if(FMC->OBCS_B.READPROT != RESET)
{
flagstatus = SET;
}
else
{
flagstatus = RESET;
}
return flagstatus;
}
/*!
* @brief FMC Prefetch Buffer status is set or not.
*
* @param None
*
* @retval status : set or reset.
*/
uint8_t FMC_ReadPrefetchBufferStatus(void)
{
return FMC->CTRL1_B.PBSF;
}
/*!
* @brief Enables the specified FMC interrupts.
*
* @param interrupt: Select the FMC interrupt sources
* This parameter can be one of the following values:
* @arg FMC_INT_ERR : Error Interrupt
* @arg FMC_INT_OC : Operation Complete Interrupt
*
* @retval None
*/
void FMC_EnableInterrupt(FMC_INT_T interrupt)
{
if(interrupt == FMC_INT_ERR)
{
FMC->CTRL2_B.ERRIE = ENABLE;
}
else
{
FMC->CTRL2_B.OCIE = ENABLE;
}
}
/*!
* @brief Disable the specified FMC interrupts.
*
* @param interrupt: Select the FMC interrupt sources
* This parameter can be one of the following values:
* @arg FMC_INT_ERR : Error Interrupt
* @arg FMC_INT_OC : Operation Complete Interrupt
*
* @retval None
*/
void FMC_DisableInterrupt(FMC_INT_T interrupt)
{
if(interrupt == FMC_INT_ERR)
{
FMC->CTRL2_B.ERRIE = DISABLE;
}
else
{
FMC->CTRL2_B.OCIE = DISABLE;
}
}
/*!
* @brief Read FMC flag is set or not
*
* @param flag: status flag of FMC
* This parameter can be one of the following values:
* @arg FMC_FLAG_BUSY : FMC Busy flag
* @arg FMC_FLAG_OC : FMC Operation Complete flag
* @arg FMC_FLAG_PE : FMC Program error flag
* @arg FMC_FLAG_WPE : FMC Write protected error flag
* @arg FMC_FLAG_OBE : FMC Option Byte error flag
*
* @retval flag status : set or reset
*/
uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag)
{
if(flag == FMC_FLAG_OBE)
{
return FMC->OBCS_B.OBE;
}
else if((FMC->STS & flag ) != RESET)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the FMC's flag.
*
* @param flag: status flag of FMC
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_OC : FMC Operation Complete flag
* @arg FMC_FLAG_PE : FMC Program error flag
* @arg FMC_FLAG_WPE : FMC Write protected error flag
*
* @retval None
*
*/
void FMC_ClearStatusFlag(uint32_t flag)
{
FMC->STS = flag;
}
/*!
* @brief Read the FMC Status.
*
* @param None
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_BUSY
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
*/
FMC_STATUS_T FMC_ReadStatus(void)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
if(FMC->STS_B.BUSYF == BIT_SET)
{
status = FMC_STATUS_BUSY;
}
else if(FMC->STS_B.PEF == BIT_SET)
{
status = FMC_STATUS_ERROR_PG;
}
else if(FMC->STS_B.WPEF == BIT_SET)
{
status = FMC_STATUS_ERROR_WRP;
}
else
{
status = FMC_STATUS_COMPLETE;
}
return status;
}
/*!
* @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
*
* @param timeOut:FMC programming timeout value.
*
* @retval Returns the flash state.It can be one of value:
* @arg FMC_STATUS_ERROR_PG
* @arg FMC_STATUS_ERROR_WRP
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
/** Check for the Flash Status */
status = FMC_ReadStatus();
/** Wait for a Flash operation to complete or a TIMEOUT to occur */
while((status == FMC_STATUS_BUSY) && (timeOut !=0))
{
status = FMC_ReadStatus();
timeOut--;
}
if(timeOut == 0x00)
{
status = FMC_STATUS_TIMEOUT;
}
return status;
}
/**@} end of group FMC_Fuctions*/
/**@} end of group FMC_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c
+545
View File
@@ -0,0 +1,545 @@
/*!
* @file apm32f10x_gpio.c
*
* @brief This file provides all the GPIO firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_gpio.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup GPIO_Fuctions Fuctions
@{
*/
/*!
* @brief Reset GPIO peripheral registers to their default reset values
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @retval None
*/
void GPIO_Reset(GPIO_T* port)
{
RCM_APB2_PERIPH_T APB2Periph;
if (port == GPIOA)
{
APB2Periph = RCM_APB2_PERIPH_GPIOA;
}
else if (port == GPIOB)
{
APB2Periph = RCM_APB2_PERIPH_GPIOB;
}
else if (port == GPIOC)
{
APB2Periph = RCM_APB2_PERIPH_GPIOC;
}
else if (port == GPIOD)
{
APB2Periph = RCM_APB2_PERIPH_GPIOD;
}
else if (port == GPIOE)
{
APB2Periph = RCM_APB2_PERIPH_GPIOE;
}
else if (port == GPIOF)
{
APB2Periph = RCM_APB2_PERIPH_GPIOF;
}
else if (port == GPIOG)
{
APB2Periph = RCM_APB2_PERIPH_GPIOG;
}
RCM_EnableAPB2PeriphReset(APB2Periph);
RCM_DisableAPB2PeriphReset(APB2Periph);
}
/*!
* @brief Reset Alternate Functions registers to their default reset values
*
* @param None
*
* @retval None
*/
void GPIO_AFIOReset(void)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_AFIO);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_AFIO);
}
/*!
* @brief Config the GPIO peripheral according to the specified parameters in the gpioConfig
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param gpioConfig: pointer to a GPIO_Config_T structure
*
* @retval None
*/
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
{
uint8_t i;
uint32_t mode;
uint32_t CR;
uint32_t temp;
uint32_t shift;
mode = gpioConfig->mode & 0x0f;
if (gpioConfig->mode & 0x80)
{
mode |= gpioConfig->speed;
}
if (gpioConfig->pin & 0xff)
{
CR = port->CFGLOW;
for (i = 0, shift = 0x01; i < 8; i++, shift <<= 1)
{
if (gpioConfig->pin & shift)
{
temp = i << 2;
CR &= (uint32_t)~(0x0f << temp);
CR |= mode << temp;
if (gpioConfig->mode == GPIO_MODE_IN_PD)
{
port->BC = shift;
}
else if (gpioConfig->mode == GPIO_MODE_IN_PU)
{
port->BSC = shift;
}
}
}
port->CFGLOW = CR;
}
if (gpioConfig->pin & 0xff00)
{
CR = port->CFGHIG;
for (i = 8, shift = 0x100; i < 16; i++, shift <<= 1)
{
if (gpioConfig->pin & shift)
{
temp = (i - 8) << 2;
CR &= (uint32_t)~(0x0f << temp);
CR |= mode << temp;
if (gpioConfig->mode == GPIO_MODE_IN_PD)
{
port->BC = shift;
}
else if (gpioConfig->mode == GPIO_MODE_IN_PU)
{
port->BSC = shift;
}
}
}
port->CFGHIG = CR;
}
}
/*!
* @brief Fills each gpioConfig member with its default value.
*
* @param gpioConfig : pointer to a GPIO_Config_T structure which will be initialized.
*
* @retval None
*/
void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
{
gpioConfig->pin = GPIO_PIN_ALL;
gpioConfig->speed = GPIO_SPEED_20MHz;
gpioConfig->mode = GPIO_MODE_IN_FLOATING;
}
/*!
* @brief Reads the specified input port pin
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param pin : specifies pin to read.
* This parameter can be one of GPIO_PIN_x( x can be from 0 to 15).
*
* @retval The input port pin value
*/
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
{
uint8_t ret;
ret = (port->IDATA & pin) ? BIT_SET : BIT_RESET;
return ret;
}
/*!
* @brief Reads the specified GPIO input data port
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @retval GPIO input data port value
*/
uint16_t GPIO_ReadInputPort(GPIO_T* port)
{
return ((uint16_t)port->IDATA);
}
/*!
* @brief Reads the specified output data port bit
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param pin : specifies pin to read.
* This parameter can be one of GPIO_PIN_x( x can be from 0 to 15).
*
* @retval The output port pin value
*/
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
{
uint8_t ret;
ret = (port->ODATA & pin) ? BIT_SET : BIT_RESET;
return ret;
}
/*!
* @brief Reads the specified GPIO output data port
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @retval output data port value
*/
uint16_t GPIO_ReadOutputPort(GPIO_T* port)
{
return ((uint16_t)port->ODATA);
}
/*!
* @brief Sets the selected data port bits
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param pin : specifies pin to be written.
* This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15).
*
* @retval None
*/
void GPIO_SetBit(GPIO_T* port, uint16_t pin)
{
port->BSC = (uint32_t)pin;
}
/*!
* @brief Clears the selected data port bits
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param pin : specifies pin to be cleared.
* This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15).
*
* @retval None
*/
void GPIO_ResetBit(GPIO_T* port, uint16_t pin)
{
port->BC = (uint32_t)pin;
}
/*!
* @brief Writes data to the specified GPIO data port bit
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param pin : Select specifies pin.
* This parameter can be one of GPIO_PIN_x( x can be from 0 to 15).
*
*
* @param bitVal : specifies the value to be written to the port output data register
* This parameter can be one of the following values:
* @arg BIT_RESET: Reset the port pin
* @arg BIT_SET : Set the port pin
*
* @retval None
*/
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
{
if (bitVal != BIT_RESET)
{
port->BSC = pin;
}
else
{
port->BC = pin ;
}
}
/*!
* @brief Writes data to the specified GPIO data port
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param portValue : specifies the value to be written to the port output data register.
*
* @retval None
*/
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
{
port->ODATA = (uint32_t)portValue;
}
/*!
* @brief Locks GPIO Pins configuration registers
*
* @param port: Select the GPIO port.
* This parameter can be one of GPIOx( x can be from A to G).
*
* @param pin : Select specifies pin.
* This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15).
*
* @retval None
*/
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
{
uint32_t val = 0x00010000;
val |= pin;
/** Set LCKK bit */
port->LOCK = val ;
/** Reset LCKK bit */
port->LOCK = pin;
/** Set LCKK bit */
port->LOCK = val;
/** Read LCKK bit*/
val = port->LOCK;
/** Read LCKK bit*/
val = port->LOCK;
}
/*!
* @brief Selects the GPIO pin used as Event output
*
* @param portSource : selects the GPIO port to be used as source for Event output.
* This parameter can be one of GPIO_PORT_SOURCE_x( x can be from A to E).
*
* @param pinSource specifies the pin for the Event output
* This parameter can be GPIO_PIN_SOURCE_x( x can be from 0 to 15).
*
* @retval None
*/
void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource)
{
AFIO->EVCTRL_B.PORTSEL = portSource;
AFIO->EVCTRL_B.PINSEL = pinSource;
}
/*!
* @brief Enables the Event Output
*
* @param None
*
* @retval None
*/
void GPIO_EnableEventOutput(void)
{
AFIO->EVCTRL_B.EVOEN = BIT_SET;
}
/*!
* @brief Disable the Event Output
*
* @param None
*
* @retval None
*/
void GPIO_DisableEventOutput(void)
{
AFIO->EVCTRL_B.EVOEN = BIT_RESET;
}
/*!
* @brief Changes the mapping of the specified pin
*
* @param remap : selects the pin to remap
* This parameter can be one of the following values:
* @arg GPIO_NO_REMAP_SPI1 : No SPI1 Alternate Function mapping
* @arg GPIO_REMAP_SPI1 : SPI1 Alternate Function mapping
* @arg GPIO_NO_REMAP_I2C1 : No I2C1 Alternate Function mapping
* @arg GPIO_REMAP_I2C1 : I2C1 Alternate Function mapping
* @arg GPIO_NO_REMAP_USART1 : No USART1 Alternate Function mapping
* @arg GPIO_REMAP_USART1 : USART1 Alternate Function mapping
* @arg GPIO_NO_REMAP_USART2 : No USART2 Alternate Function mapping
* @arg GPIO_REMAP_USART2 : USART2 Alternate Function mapping
* @arg GPIO_NO_REMAP_USART3 : No USART3 Partial Alternate Function mapping
* @arg GPIO_PARTIAL_REMAP_USART3 : USART3 Partial Alternate Function mapping
* @arg GPIO_FULL_REMAP_USART3 : USART3 Full Alternate Function mapping
* @arg GPIO_NO_REMAP_TMR1 : No TIM1 Partial Alternate Function mapping
* @arg GPIO_PARTIAL_REMAP_TMR1 : TIM1 Partial Alternate Function mapping
* @arg GPIO_FULL_REMAP_TMR1 : TIM1 Full Alternate Function mapping
* @arg GPIO_NO_REMAP1_TMR2 : No TIM2 Partial1 Alternate Function mapping
* @arg GPIO_PARTIAL_REMAP1_TMR2 : TIM2 Partial1 Alternate Function mapping
* @arg GPIO_PARTIAL_REMAP2_TMR2 : TIM2 Partial2 Alternate Function mapping
* @arg GPIO_FULL_REMAP_TMR2 : TIM2 Full Alternate Function mapping
* @arg GPIO_NO_REMAP_TMR3 : No TIM3 Partial Alternate Function mapping
* @arg GPIO_PARTIAL_REMAP_TMR3 : TIM3 Partial Alternate Function mapping
* @arg GPIO_FULL_REMAP_TMR3 : TIM3 Full Alternate Function mapping
* @arg GPIO_NO_REMAP_TMR4 : No TIM4 Alternate Function mapping
* @arg GPIO_REMAP_TMR4 : TIM4 Alternate Function mapping
* @arg GPIO_NO_REMAP_CAN1 : No CAN1 Alternate Function mapping
* @arg GPIO_REMAP1_CAN1 : CAN1 Alternate Function mapping
* @arg GPIO_REMAP2_CAN1 : CAN1 Alternate Function mapping
* @arg GPIO_NO_REMAP_PD01 : No PD01 Alternate Function mapping
* @arg GPIO_REMAP_PD01 : PD01 Alternate Function mapping
* @arg GPIO_NO_REMAP_TMR5CH4_LSI : No LSI connected to TIM5 Channel4 input capture for calibration
* @arg GPIO_REMAP_TMR5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
* @arg GPIO_NO_REMAP_ADC1_ETRGINJ : No ADC1 External Trigger Injected Conversion remapping
* @arg GPIO_REMAP_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
* @arg GPIO_NO_REMAP_ADC1_ETRGREG : No ADC1 External Trigger Regular Conversion remapping
* @arg GPIO_REMAP_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
* @arg GPIO_NO_REMAP_ADC2_ETRGINJ : No ADC2 External Trigger Injected Conversion remapping
* @arg GPIO_REMAP_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
* @arg GPIO_NO_REMAP_ADC2_ETRGREG : No ADC2 External Trigger Regular Conversion remapping
* @arg GPIO_REMAP_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
* @arg GPIO_NO_REMAP_CAN2 : No CAN2 Alternate Function mapping
* @arg GPIO_REMAP_CAN2 : CAN2 Alternate Function mapping
* @arg GPIO_NO_REMAP_SWJ : Full SWJ Enabled (JTAG-DP + SW-DP)
* @arg GPIO_REMAP_SWJ_NOJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
* @arg GPIO_REMAP_SWJ_JTAGDISABLE : JTAG-DP Disabled and SW-DP Enabled
* @arg GPIO_REMAP_SWJ_DISABLE : Full SWJ Disabled (JTAG-DP + SW-DP)
*
* @retval When you use GPIO_REMAP_CAN2, you must put this function last of all other ConfigPinRemap Function.
*/
void GPIO_ConfigPinRemap(GPIO_REMAP_T remap)
{
uint32_t val, mask, bitOffset, regOffset;
uint32_t regVal;
val = remap & 0x0f;
mask = (remap >> 4) & 0x0f;
bitOffset = (remap >> 8) & 0xff;
regOffset = (remap >> 16) & 0x0f;
if (regOffset)
{
regVal = AFIO->REMAP2;
}
else
{
regVal = AFIO->REMAP1;
}
if(remap >> 8 == 0x18)
{
regVal &= 0xF0FFFFFF;
AFIO->REMAP1 &= 0xF0FFFFFF;
}
else
{
regVal |= 0x0F000000;
}
mask <<= bitOffset;
regVal &= (uint32_t)~mask;
val <<= bitOffset;
regVal |= val;
if (regOffset)
{
AFIO->REMAP2 = regVal;
}
else
{
AFIO->REMAP1 = regVal;
}
}
/*!
* @brief Selects the GPIO pin used as EINT Line
*
* @param portSource : selects the GPIO port to be used as source for EINT line.
* This parameter can be one of GPIO_PORT_SOURCE_x( x can be from A to G).
*
* @param pinSource : Specifies the EINT line to be configured.
* This parameter can be GPIO_PIN_SOURCE_x( x can be from 0 to 15).
*
* @retval None
*/
void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource)
{
uint32_t shift;
if (pinSource <= GPIO_PIN_SOURCE_3)
{
shift = pinSource << 2;
AFIO->EINTSEL1 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL1 |= portSource << shift;
}
else if (pinSource <= GPIO_PIN_SOURCE_7)
{
shift = (pinSource - GPIO_PIN_SOURCE_4) << 2;
AFIO->EINTSEL2 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL2 |= portSource << shift;
}
else if (pinSource <= GPIO_PIN_SOURCE_11)
{
shift = (pinSource - GPIO_PIN_SOURCE_8) << 2;
AFIO->EINTSEL3 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL3 |= portSource << shift;
}
else if (pinSource <= GPIO_PIN_SOURCE_15)
{
shift = (pinSource - GPIO_PIN_SOURCE_12) << 2;
AFIO->EINTSEL4 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL4 |= portSource << shift;
}
}
/**@} end of group GPIO_Fuctions*/
/**@} end of group GPIO_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c
+1024
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c
+148
View File
@@ -0,0 +1,148 @@
/*!
* @file apm32f10x_iwdt.c
*
* @brief This file provides all the IWDT firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_iwdt.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup IWDT_Driver IWDT Driver
@{
*/
/** @addtogroup IWDT_Fuctions Fuctions
@{
*/
/*!
* @brief Enable IWDT
*
* @param None
*
* @retval None
*/
void IWDT_Enable(void)
{
IWDT->KEY = IWDT_KEYWORD_ENABLE;
}
/*!
* @brief Reload the IWDT counter with value
*
* @param None
*
* @retval None
*/
void IWDT_Refresh(void)
{
IWDT->KEY = IWDT_KEYWORD_RELOAD;
}
/*!
* @brief Set IWDT count reload values
*
* @param reload: IWDT count reload values
*
* @retval None
*/
void IWDT_ConfigReload(uint16_t reload)
{
IWDT->CNTRLD = reload;
}
/*!
* @brief Enable the IWDT write access
*
* @param None
*
* @retval None
*/
void IWDT_EnableWriteAccess(void)
{
IWDT->KEY_B.KEY = IWDT_WRITEACCESS_ENABLE;
}
/*!
* @brief Disable the IWDT write access
*
* @param None
*
* @retval None
*/
void IWDT_DisableWriteAccess(void)
{
IWDT->KEY_B.KEY = IWDT_WRITEACCESS_DISABLE;
}
/*!
* @brief Set IWDT frequency divider values
*
* @param div: IWDT frequency divider values
* This parameter can be one of the following values:
* @arg IWDT_DIVIDER_4 : prescaler divider equal to 4
* @arg IWDT_DIVIDER_8 : prescaler divider equal to 8
* @arg IWDT_DIVIDER_16 : prescaler divider equal to 16
* @arg IWDT_DIVIDER_32 : prescaler divider equal to 32
* @arg IWDT_DIVIDER_64 : prescaler divider equal to 64
* @arg IWDT_DIVIDER_128: prescaler divider equal to 128
* @arg IWDT_DIVIDER_256: prescaler divider equal to 256
*
* @retval None
*/
void IWDT_ConfigDivider(uint8_t div)
{
IWDT->PSC = div;
}
/*!
* @brief Read the specified IWDT flag
*
* @param flag: specifies the flag to read
* This parameter can be one of the following values:
* @arg IWDT_FLAG_PSCU : Watchdog Prescaler Factor Update flag
* @arg IWDT_FLAG_CNTU : Watchdog Counter Reload Value Update flag
*
* @retval status of IWDT_FLAG (SET or RESET)
*
*/
uint8_t IWDT_ReadStatusFlag(uint16_t flag)
{
uint8_t bitStatus = RESET;
if((IWDT->STS & flag) != (uint32_t)RESET)
{
bitStatus = SET;
}
else
{
bitStatus = RESET;
}
return bitStatus;
}
/**@} end of group IWDT_Fuctions*/
/**@} end of group IWDT_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c
+220
View File
@@ -0,0 +1,220 @@
/*!
* @file apm32f10x_misc.c
*
* @brief This file provides all the miscellaneous firmware functions.
* Include NVIC,SystemTick and Power management.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_misc.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup MISC_Driver MISC Driver
@{
*/
/** @addtogroup MISC_Macros Macros
@{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**@} end of group MISC_Macros*/
/** @addtogroup MISC_Fuctions Fuctions
@{
*/
/*!
* @brief Configures the priority grouping: pre-emption priority and subpriority.
*
* @param priorityGroup : specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITY_GROUP_0
* @arg NVIC_PRIORITY_GROUP_1
* @arg NVIC_PRIORITY_GROUP_2
* @arg NVIC_PRIORITY_GROUP_3
* @arg NVIC_PRIORITY_GROUP_4
*
* @retval None
*/
void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
{
SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
}
/*!
* @brief Enable NVIC request
*
* @param irq: the NVIC interrupt request, detailed in IRQn_Type
* For the complete APM32 Devices IRQ Channels list,please refer to apm32f10x.h file
*
* @param preemptionPriority: the pre-emption priority needed to set
*
* @param subPriority: the subpriority needed to set
*
* @retval None
*/
void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority)
{
uint32_t tempPriority, tempPrePri, tempSubPri;
uint32_t priorityGrp;
/** Get priority group */
priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
/** get pre-emption priority and subpriority */
switch(priorityGrp)
{
case NVIC_PRIORITY_GROUP_0:
tempPrePri = 0;
tempSubPri = 4;
break;
case NVIC_PRIORITY_GROUP_1:
tempPrePri = 1;
tempSubPri = 3;
break;
case NVIC_PRIORITY_GROUP_2:
tempPrePri = 2;
tempSubPri = 2;
break;
case NVIC_PRIORITY_GROUP_3:
tempPrePri = 3;
tempSubPri = 1;
break;
case NVIC_PRIORITY_GROUP_4:
tempPrePri = 4;
tempSubPri = 0;
break;
default:
NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
tempPrePri = 0;
tempSubPri = 4;
break;
}
tempPrePri = 4 - tempPrePri;
tempSubPri = 4 - tempSubPri;
tempPriority = preemptionPriority << tempPrePri;
tempPriority |= subPriority & (0x0f >> tempSubPri);
tempPriority <<= 4;
NVIC->IP[irq] = (uint8_t)tempPriority;
/** enable the selected IRQ */
NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
}
/*!
* @brief Disable NVIC request
*
* @param irq: the NVIC interrupt request, detailed in IRQn_Type
*
* @retval None
*/
void NVIC_DisableIRQRequest(IRQn_Type irq)
{
/** disable the selected IRQ.*/
NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
}
/*!
* @brief Configs the vector table location and Offset.
*
* @param vectTab: specifies if the vector table is in RAM or FLASH memory
* This parameter can be one of the following values:
* @arg NVIC_VECT_TAB_RAM
* @arg NVIC_VECT_TAB_FLASH
*
* @param Offset Vector Table base offset field. This value must be a multiple of 0x200
*
* @retval None
*/
void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset)
{
SCB->VTOR = vectTab | (offset & (uint32_t)0x1FFFFF80);
}
/*!
* @brief set the state of the low power mode
*
* @param lowPowerMode: the low power mode state
* This parameter can be one of the following values:
* @arg NVIC_LOWPOWER_SEVONPEND
* @arg NVIC_LOWPOWER_SLEEPDEEP
* @arg NVIC_LOWPOWER_SLEEPONEXIT
*
* @retval None
*/
void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
{
SCB->SCR |= lowPowerMode;
}
/*!
* @brief reset the state of the low power mode
*
* @param lowPowerMode: the low power mode state
* This parameter can be one of the following values:
* @arg NVIC_LOWPOWER_SEVONPEND
* @arg NVIC_LOWPOWER_SLEEPDEEP
* @arg NVIC_LOWPOWER_SLEEPONEXIT
*
* @retval None
*/
void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
{
SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
}
/*!
* @brief Configures the SysTick clock source
*
* @param clkSource: specifies the SysTick clock source
* This parameter can be one of the following values:
* @arg SYSTICK_CLK_SOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLK_SOURCE_HCLK: AHB clock selected as SysTick clock source.
*
* @retval None
*/
void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource)
{
if (clkSource == SYSTICK_CLK_SOURCE_HCLK)
{
SysTick->CTRL |= (uint32_t)BIT2;
}
else
{
SysTick->CTRL &= (uint32_t)(~BIT2);
}
}
/**@} end of group MISC_Fuctions*/
/**@} end of group MISC_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c
+268
View File
@@ -0,0 +1,268 @@
/*!
* @file apm32f10x_pmu.c
*
* @brief This file provides all the PMU firmware functions.
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_pmu.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup PMU_Driver PMU Driver
@{
*/
/** @addtogroup PMU_Fuctions Fuctions
@{
*/
/*!
* @brief Reset the PMU peripheral register.
*
* @param None
*
* @retval None
*/
void PMU_Reset(void)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_PMU);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_PMU);
}
/*!
* @brief Enables access to the RTC and backup registers.
*
* @param None
*
* @retval None
*/
void PMU_EnableBackupAccess(void)
{
PMU->CTRL_B.BPWEN = ENABLE ;
}
/*!
* @brief Disables access to the RTC and backup registers.
*
* @param None
*
* @retval None
*/
void PMU_DisableBackupAccess(void)
{
PMU->CTRL_B.BPWEN = DISABLE;
}
/*!
* @brief Enables the Power Voltage Detector(PVD).
*
* @param None
*
* @retval None
*/
void PMU_EnablePVD(void)
{
PMU->CTRL_B.PVDEN = ENABLE;
}
/*!
* @brief Disables the Power Voltage Detector(PVD).
*
* @param None
*
* @retval None
*/
void PMU_DisablePVD(void)
{
PMU->CTRL_B.PVDEN = DISABLE;
}
/*!
* @brief Configure a voltage threshold detected by a power supply voltage detector (PVD).
*
* @param level£ºspecifies the PVD detection level
* This parameter can be one of the following values:
* @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V
* @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V
* @arg PMU_PVD_LEVEL_2V4 : Config PVD detection level to 2.4V
* @arg PMU_PVD_LEVEL_2V5 : Config PVD detection level to 2.5V
* @arg PMU_PVD_LEVEL_2V6 : Config PVD detection level to 2.6V
* @arg PMU_PVD_LEVEL_2V7 : Config PVD detection level to 2.7V
* @arg PMU_PVD_LEVEL_2V8 : Config PVD detection level to 2.8V
* @arg PMU_PVD_LEVEL_2V9 : Config PVD detection level to 2.9V
*
* @retval None
*/
void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level)
{
/** Clear PLS[7:5] bits */
PMU->CTRL_B.PLSEL = 0x0000;
/** Store the new value */
PMU->CTRL_B.PLSEL = level;
}
/*!
* @brief Enables the WakeUp Pin functionality.
*
* @param None
*
* @retval None
*/
void PMU_EnableWakeUpPin(void)
{
PMU->CSTS_B.WKUPCFG = ENABLE ;
}
/*!
* @brief Diaables the WakeUp Pin functionality.
*
* @param None
*
* @retval None
*/
void PMU_DisableWakeUpPin(void)
{
PMU->CSTS_B.WKUPCFG = DISABLE ;
}
/*!
* @brief Enters STOP mode.
*
* @param regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PMU_REGULATOR_ON : STOP mode with regulator ON
* @arg PMU_REGULATOR_LOWPOWER: STOP mode with regulator in low power mode
*
* @param entry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PMU_STOP_ENTRY_WFI: Enter STOP mode with WFI instruction
* @arg PMU_STOP_ENTRY_WFE: Enter STOP mode with WFE instruction
*
* @retval None
*/
void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
{
/** Clear PDDSCFG and LPDSCFG bits */
PMU->CTRL_B.PDDSCFG = 0x00;
PMU->CTRL_B.LPDSCFG = 0x00;
/** Set LPDSCFG bit according to regulator value */
PMU->CTRL_B.LPDSCFG = regulator;
/** Set Cortex System Control Register */
SCB->SCR |= (uint32_t )0x04;
/** Select STOP mode entry*/
if(entry == PMU_STOP_ENTRY_WFI)
{
/** Request Wait For Interrupt */
__WFI();
}
else
{
/** Request Wait For Event */
__WFE();
}
/** Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)0x04);
}
/*!
* @brief Enters STANDBY mode.
*
* @param None
*
* @retval None
*/
void PMU_EnterSTANDBYMode(void)
{
/** Clear Wake-up flag */
PMU->CTRL_B.WUFLGCLR = BIT_SET;
/** Select STANDBY mode */
PMU->CTRL_B.PDDSCFG = BIT_SET;
/** Set Cortex System Control Register */
SCB->SCR |= (uint32_t )0x04;
#if defined ( __CC_ARM )
__force_stores();
#endif
/** Request Wait For Interrupt */
__WFI();
}
/*!
* @brief Read the specified PWR flag is set or not.
*
* @param flag£ºReads the status of specifies the flag.
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUE : Wake Up flag
* @arg PMU_FLAG_SB : StandBy flag
* @arg PMU_FLAG_PVDO: PVD Output flag
*
* @retval The new state of PMU_FLAG (SET or RESET).
*/
uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
{
uint8_t BitStatus = BIT_RESET;
if(flag == PMU_FLAG_WUE)
{
BitStatus = PMU->CSTS_B.WUEFLG;
}
else if(flag == PMU_FLAG_SB)
{
BitStatus = PMU->CSTS_B.SBFLG;
}
else if(flag == PMU_FLAG_PVDO)
{
BitStatus = PMU->CSTS_B.PVDOFLG;
}
return BitStatus;
}
/*!
* @brief Clears the PWR's pending flags.
*
* @param flag£ºClears the status of specifies the flag.
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUE : Wake Up flag
* @arg PMU_FLAG_SB : StandBy flag
*
* @retval None
*/
void PMU_ClearStatusFlag(PMU_FLAG_T flag)
{
if(flag == PMU_FLAG_WUE)
{
PMU->CTRL_B.WUFLGCLR = BIT_SET;
}
else if(flag == PMU_FLAG_SB)
{
PMU->CTRL_B.SBFLGCLR = BIT_SET;
}
}
/**@} end of group PMU_Fuctions*/
/**@} end of group PMU_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c
+609
View File
@@ -0,0 +1,609 @@
/*!
* @file qpm32f10x_qspi.c
*
* @brief This file contains all the functions for the QSPI peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#if defined (APM32F10X_MD) || defined (APM32F10X_LD)
#include "apm32f10x_qspi.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup QSPI_Driver QSPI Driver
@{
*/
/** @addtogroup QSPI_Fuctions Fuctions
@{
*/
/*!
* @brief Reset QSPI peripheral registers to their default values
*
* @param None
*
* @retval None
*/
void QSPI_Reset(void)
{
volatile uint32_t dummy = 0;
QSPI->IOSW = QSPI_IOSW_RESET_VALUE;
QSPI->SSIEN = QSPI_SSIEN_RESET_VALUE;
QSPI->INTEN = QSPI_INTEN_RESET_VALUE;
dummy = QSPI->ICF;
QSPI->CTRL1 = QSPI_CTRL1_RESET_VALUE;
QSPI->CTRL2 = QSPI_CTRL2_RESET_VALUE;
QSPI->CTRL3 = QSPI_CTRL3_RESET_VALUE;
QSPI->SLAEN = QSPI_SLAEN_RESET_VALUE;
QSPI->BR = QSPI_BR_RESET_VALUE;
QSPI->TFL = QSPI_TFL_RESET_VALUE;
QSPI->RFL = QSPI_RFL_RESET_VALUE;
QSPI->TFTL = QSPI_TFTL_RESET_VALUE;
QSPI->RFTL = QSPI_RFTL_RESET_VALUE;
QSPI->STS = QSPI_STS_RESET_VALUE;
QSPI->RSD = QSPI_RSD_RESET_VALUE;
}
/*!
* @brief Config the QSPI peripheral according to the specified parameters in the qspiConfig
*
* @param qspiConfig: Pointer to a QSPI_Config_T structure that contains the configuration information
*
* @retval None
*/
void QSPI_Config(QSPI_Config_T * qspiConfig)
{
QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase;
QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity;
QSPI->CTRL1_B.FRF = qspiConfig->frameFormat;
QSPI->CTRL1_B.DFS = qspiConfig->dataFrameSize;;
QSPI->CTRL1_B.SSTEN = qspiConfig->selectSlaveToggle;
QSPI->BR = qspiConfig->clockDiv;
}
/*!
* @brief Fills each qspiConfig member with its default value
*
* @param qspiConfig: Pointer to a QSPI_Config_T structure which will be initialized
*
* @retval None
*/
void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig)
{
qspiConfig->clockPhase = QSPI_CLKPHA_2EDGE;
qspiConfig->clockPolarity = QSPI_CLKPOL_LOW;
qspiConfig->clockDiv = 0;
qspiConfig->frameFormat = QSPI_FRF_STANDARD;
qspiConfig->dataFrameSize = QSPI_DFS_8BIT;
qspiConfig->selectSlaveToggle = QSPI_SST_DISABLE;
}
/*!
* @brief Configs frame number
*
* @param num: Configs a 16bit frame number
*
* @retval None
*/
void QSPI_ConfigFrameNum(uint16_t num)
{
QSPI->CTRL2_B.NDF = num;
}
/*!
* @brief Configs data frame size
*
* @param dfs: Specifies the data frame size
* The parameter can be one of following values:
* @arg QSPI_DFS_4BIT : Specifies data frame size to 4bit
* @arg QSPI_DFS_5BIT : Specifies data frame size to 5bit
* @arg QSPI_DFS_6BIT : Specifies data frame size to 6bit
* @arg QSPI_DFS_7BIT : Specifies data frame size to 7bit
* @arg QSPI_DFS_8BIT : Specifies data frame size to 8bit
* @arg QSPI_DFS_9BIT : Specifies data frame size to 9bit
* @arg QSPI_DFS_10BIT : Specifies data frame size to 10bit
* @arg QSPI_DFS_11BIT : Specifies data frame size to 11bit
* @arg QSPI_DFS_12BIT : Specifies data frame size to 12bit
* @arg QSPI_DFS_13BIT : Specifies data frame size to 13bit
* @arg QSPI_DFS_14BIT : Specifies data frame size to 14bit
* @arg QSPI_DFS_15BIT : Specifies data frame size to 15bit
* @arg QSPI_DFS_16BIT : Specifies data frame size to 16bit
* @arg QSPI_DFS_17BIT : Specifies data frame size to 17bit
* @arg QSPI_DFS_18BIT : Specifies data frame size to 18bit
* @arg QSPI_DFS_19BIT : Specifies data frame size to 19bit
* @arg QSPI_DFS_20BIT : Specifies data frame size to 20bit
* @arg QSPI_DFS_21BIT : Specifies data frame size to 21bit
* @arg QSPI_DFS_22BIT : Specifies data frame size to 22bit
* @arg QSPI_DFS_23BIT : Specifies data frame size to 23bit
* @arg QSPI_DFS_24BIT : Specifies data frame size to 24bit
* @arg QSPI_DFS_25BIT : Specifies data frame size to 25bit
* @arg QSPI_DFS_26BIT : Specifies data frame size to 26bit
* @arg QSPI_DFS_27BIT : Specifies data frame size to 27bit
* @arg QSPI_DFS_28BIT : Specifies data frame size to 28bit
* @arg QSPI_DFS_29BIT : Specifies data frame size to 29bit
* @arg QSPI_DFS_30BIT : Specifies data frame size to 30bit
* @arg QSPI_DFS_31BIT : Specifies data frame size to 31bit
* @arg QSPI_DFS_32BIT : Specifies data frame size to 32bit
*
* @retval None
*/
void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs)
{
QSPI->CTRL1_B.DFS = dfs;
}
/*!
* @brief Configs frame format
*
* @param frameFormat
*
* @retval None
*/
void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat)
{
QSPI->CTRL1_B.FRF = frameFormat;
}
/*!
* @brief Enable QSPI
*
* @param None
*
* @retval None
*/
void QSPI_Enable(void)
{
QSPI->SSIEN_B.EN = BIT_SET;
}
/*!
* @brief Disable QSPI
*
* @param None
*
* @retval None
*/
void QSPI_Disable(void)
{
QSPI->SSIEN_B.EN = BIT_RESET;
}
/*!
* @brief Read Tx FIFO number of data
*
* @param None
*
* @retval None
*/
uint8_t QSPI_ReadTxFifoDataNum(void)
{
return (uint8_t)QSPI->TFL_B.TFL;
}
/*!
* @brief Read Rx FIFO number of data
*
* @param None
*
* @retval Returns Rx FIFO number of data
*/
uint8_t QSPI_ReadRxFifoDataNum(void)
{
return (uint8_t)QSPI->RFL_B.RFL;
}
/*!
* @brief Configs rx FIFO threshold
*
* @param threshold: Speicifes rx FIFO threshold with a 3bit value
*
* @retval None
*/
void QSPI_ConfigRxFifoThreshold(uint8_t threshold)
{
QSPI->RFTL_B.RFT = threshold;
}
/*!
* @brief Congfigs Tx FIFO threshold
*
* @param threshold: Speicifes Tx FIFO threshold with a 3bit value
*
* @retval None
*/
void QSPI_ConfigTxFifoThreshold(uint8_t threshold)
{
QSPI->TFTL_B.TFTH = threshold;
}
/*!
* @brief Congfigs Tx FIFO empty threshold
*
* @param threshold: Speicifes Tx FIFO empty threshold with a 3bit value
*
* @retval None
*/
void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold)
{
QSPI->TFTL_B.TFT = threshold;
}
/*!
* @brief Configs RX sample edge
*
* @param rse: Specifies the sample edge
* The parameter can be one of following values:
* @arg QSPI_RSE_RISING : rising edge sample
* @arg QSPI_RSE_FALLING: falling edge sample
*
* @retval None
*/
void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse)
{
QSPI->RSD_B.RSE = rse;
}
/*!
* @brief Set RX sample delay
*
* @param delay: Specifies the sample delay with a 8-bit value
*
* @retval None
*/
void QSPI_ConfigRxSampleDelay(uint8_t delay)
{
QSPI->RSD_B.RSD = delay;
}
/*!
* @brief Clock stretch enable
*
* @param None
*
* @retval None
*/
void QSPI_EnableClockStretch(void)
{
QSPI->CTRL3_B.CSEN = BIT_SET;
}
/*!
* @brief Clock stretch disable
*
* @param None
*
* @retval None
*/
void QSPI_DisableClockStretch(void)
{
QSPI->CTRL3_B.CSEN = BIT_RESET;
}
/*!
* @brief Configs instruction length
*
* @param len: Specifies the length of instruction
* The parameter can be one of following values:
* @arg QSPI_INST_LEN_0 : no instruction
* @arg QSPI_INST_LEN_4BIT : 4-bit instruction
* @arg QSPI_INST_LEN_8BIT : 8-bit instruction
* @arg QSPI_INST_LEN_16BIT : 16-bit instruction
*
* @retval None
*/
void QSPI_ConfigInstLen(QSPI_INST_LEN_T len)
{
QSPI->CTRL3_B.INSLEN = len;
}
/*!
* @brief Configs address length
*
* @param len: Specifies the address length
* The parameter can be one of following values:
* @arg QSPI_ADDR_LEN_0 : no address
* @arg QSPI_ADDR_LEN_4BIT : 4-bit address length
* @arg QSPI_ADDR_LEN_8BIT, : 8-bit address length
* @arg QSPI_ADDR_LEN_12BIT : 12-bit address length
* @arg QSPI_ADDR_LEN_16BIT : 16-bit address length
* @arg QSPI_ADDR_LEN_20BIT : 20-bit address length
* @arg QSPI_ADDR_LEN_24BIT : 24-bit address length
* @arg QSPI_ADDR_LEN_28BIT : 28-bit address length
* @arg QSPI_ADDR_LEN_32BIT : 32-bit address length
* @arg QSPI_ADDR_LEN_36BIT : 36-bit address length
* @arg QSPI_ADDR_LEN_40BIT : 40-bit address length
* @arg QSPI_ADDR_LEN_44BIT : 44-bit address length
* @arg QSPI_ADDR_LEN_48BIT : 48-bit address length
* @arg QSPI_ADDR_LEN_52BIT : 52-bit address length
* @arg QSPI_ADDR_LEN_56BIT : 56-bit address length
* @arg QSPI_ADDR_LEN_60BIT : 60-bit address length
*
* @retval None
*/
void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len)
{
QSPI->CTRL3_B.ADDRLEN = len;
}
/*!
* @brief Configs instruction and address type
*
* @param type: Specifies the instruction and address type
* The parameter can be one of following values:
* @arg QSPI_INST_ADDR_TYPE_STANDARD : Tx instruction in standard SPI mode,
* Tx address in standard SPI mode
* @arg QSPI_INST_TYPE_STANDARD : Tx instruction in standard SPI mode,
* Tx address in mode of SPI_FRF
* @arg QSPI_INST_ADDR_TYPE_FRF : Tx instruction in mode of SPI_FRF,
* Tx address in mode of SPI_FRF
*
* @retval None
*/
void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type)
{
QSPI->CTRL3_B.IAT = type;
}
/*!
* @brief Configs wait cycle number
*
* @param cycle: Specifies the wait cycle number with a 5-bit value
*
* @retval None
*/
void QSPI_ConfigWaitCycle(uint8_t cycle)
{
QSPI->CTRL3_B.WAITCYC = cycle;
}
/*!
* @brief Open QSPI GPIO
*
* @param None
*
* @retval None
*/
void QSPI_OpenIO(void)
{
QSPI->IOSW_B.IOSW = BIT_SET;
}
/*!
* @brief Close QSPI GPIO
*
* @param None
*
* @retval None
*/
void QSPI_CloseIO(void)
{
QSPI->IOSW_B.IOSW = BIT_RESET;
}
/*!
* @brief Set transmission mode
*
* @param mode: Specifies the transmission mode
* The parameter can be one of following values:
* @arg QSPI_TRANS_MODE_TX_RX : TX and RX mode
* @arg QSPI_TRANS_MODE_TX : TX mode only
* @arg QSPI_TRANS_MODE_RX : RX mode only
* @arg QSPI_TRANS_MODE_EEPROM_READ : EEPROM read mode
*
* @retval None
*/
void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode)
{
QSPI->CTRL1_B.TXMODE = mode;
}
/*!
* @brief Transmit data
*
* @param data: Data to be transmited
*
* @retval None
*/
void QSPI_TxData(uint32_t data)
{
QSPI->DATA = data;
}
/*!
* @brief Returns the most recent received data
*
* @param None
*
* @retval The received data
*/
uint32_t QSPI_RxData(void)
{
return (uint32_t)QSPI->DATA;
}
/*!
* @brief Enable Slave
*
* @param None
*
* @retval None
*/
void QSPI_EnableSlave(void)
{
QSPI->SLAEN_B.SLAEN = BIT_SET;
}
/*!
* @brief Disable slave
*
* @param None
*
* @retval None
*/
void QSPI_DisableSlave(void)
{
QSPI->SLAEN_B.SLAEN = BIT_RESET;
}
/*!
* @brief Enable the specified QSPI interrupts
*
* @param interrupt: Specifies the QSPI interrupt sources
* The parameter can be combination of following values:
* @arg QSPI_INT_TFE: TX FIFO empty interrupt
* @arg QSPI_INT_TFO: TX FIFO overflow interrupt
* @arg QSPI_INT_RFU: RX FIFO underflow interrupt
* @arg QSPI_INT_RFO: RX FIFO overflow interrupt
* @arg QSPI_INT_RFF: RX FIFO full interrupt
* @arg QSPI_INT_MST: Master interrupt
*
* @retval None
*/
void QSPI_EnableInterrupt(uint32_t interrupt)
{
QSPI->INTEN |= interrupt;
}
/*!
* @brief Disable the specified QSPI interrupts
*
* @param interrupt: Specifies the QSPI interrupt sources
* The parameter can be combination of following values:
* @arg QSPI_INT_TFE: TX FIFO empty interrupt
* @arg QSPI_INT_TFO: TX FIFO overflow interrupt
* @arg QSPI_INT_RFU: RX FIFO underflow interrupt
* @arg QSPI_INT_RFO: RX FIFO overflow interrupt
* @arg QSPI_INT_RFF: RX FIFO full interrupt
* @arg QSPI_INT_MST: Master interrupt
*
* @retval None
*/
void QSPI_DisableInterrupt(uint32_t interrupt)
{
QSPI->INTEN &= (uint32_t)~interrupt;
}
/*!
* @brief Read specified QSPI flag
*
* @param flag: Specifies the flag to be checked
* The parameter can be one of following values:
* @arg QSPI_FLAG_BUSY: Busy flag
* @arg QSPI_FLAG_TFNF: TX FIFO not full flag
* @arg QSPI_FLAG_TFE: TX FIFO empty flag
* @arg QSPI_FLAG_RFNE: RX FIFO not empty flag
* @arg QSPI_FLAG_RFF: RX FIFO full flag
* @arg QSPI_FLAG_DCE: Data collision error
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag)
{
uint8_t ret = RESET;
ret = QSPI->STS & flag ? SET : RESET;
return ret;
}
/*!
* @brief Clear specified QSPI flag
*
* @param None
*
* @retval None
*
* @note This funtion only clear Data collision error flag(QSPI_FLAG_DCE)
*/
void QSPI_ClearStatusFlag(void)
{
volatile uint32_t dummy = 0;
dummy = QSPI->STS;
}
/*!
* @brief Read specified QSPI interrupt flag
*
* @param flag: Specifies the interrupt flag to be checked
* The parameter can be one of following values:
* @arg QSPI_INT_FLAG_TFE: TX FIFO empty interrupt flag
* @arg QSPI_INT_FLAG_TFO: TX FIFO overflow interrupt flag
* @arg QSPI_INT_FLAG_RFU: RX FIFO underflow interrupt flag
* @arg QSPI_INT_FLAG_RFO: RX FIFO overflow interrupt flag
* @arg QSPI_INT_FLAG_RFF: RX FIFO full interrupt flag
* @arg QSPI_INT_FLAG_MST: Master interrupt flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag)
{
uint8_t ret = RESET;
ret = QSPI->ISTS & flag ? SET : RESET;
return ret;
}
/*!
* @brief Clear specified QSPI interrupt flag
*
* @param flag: Specifies the interrupt flag to be checked
* The parameter can be one of following values:
* @arg QSPI_INT_FLAG_TFO: TX FIFO overflow interrupt flag
* @arg QSPI_INT_FLAG_RFU: RX FIFO underflow interrupt flag
* @arg QSPI_INT_FLAG_RFO: RX FIFO overflow interrupt flag
* @arg QSPI_INT_FLAG_MST: Master interrupt flag
*
* @retval None
*/
void QSPI_ClearIntFlag(uint32_t flag)
{
volatile uint32_t dummy = 0;
if(flag & QSPI_INT_FLAG_TFO)
{
dummy = QSPI->TFOIC;
}
else if(flag & QSPI_INT_FLAG_RFO)
{
dummy = QSPI->RFOIC;
}
else if(flag & QSPI_INT_FLAG_RFU)
{
dummy = QSPI->RFUIC;
}
else if(flag & QSPI_INT_FLAG_MST)
{
dummy = QSPI->MIC;
}
}
#endif //defined APM32F10X_MD/LD
/**@} end of group QSPI_Fuctions*/
/**@} end of group QSPI_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c
+1077
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c
+263
View File
@@ -0,0 +1,263 @@
/*!
* @file apm32f10x_rtc.c
*
* @brief This file provides all the RTC firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_rtc.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup RTC_Driver RTC Driver
@{
*/
/** @addtogroup RTC_Fuctions Fuctions
@{
*/
/*!
* @brief Enter RTC configuration mode.
*
* @param None
*
* @retval None
*/
void RTC_EnableConfigMode(void)
{
RTC->CSTS_B.CFGMFLG = BIT_SET;
}
/*!
* @brief Exit RTC configuration mode.
*
* @param None
*
* @retval None
*/
void RTC_DisableConfigMode(void)
{
RTC->CSTS_B.CFGMFLG = BIT_RESET;
}
/*!
* @brief Read the RTC counter value.
*
* @param None
*
* @retval RTC counter value.
*/
uint32_t RTC_ReadCounter(void)
{
uint32_t reg = 0;
reg = (RTC->CNTH_B.CNTH) << 16;
reg |= (RTC->CNTL_B.CNTL);
return (reg);
}
/*!
* @brief Config the RTC counter value.
*
* @param value: RTC counter new value.
*
* @retval None
*/
void RTC_ConfigCounter(uint32_t value)
{
RTC_EnableConfigMode();
RTC->CNTH_B.CNTH = value >> 16;
RTC->CNTL_B.CNTL = value & 0x0000FFFF;
RTC_DisableConfigMode();
}
/*!
* @brief Config the RTC prescaler value.
*
* @param value: RTC prescaler new value.
*
* @retval None
*/
void RTC_ConfigPrescaler(uint32_t value)
{
RTC_EnableConfigMode();
RTC->PSCRLDH_B.PSCRLDH = value >> 16;
RTC->PSCRLDL_B.PSCRLDL = value & 0x0000FFFF;
RTC_DisableConfigMode();
}
/*!
* @brief Config the RTC alarm value.
*
* @param value: RTC alarm new value.
*
* @retval None
*/
void RTC_ConfigAlarm(uint32_t value)
{
RTC_EnableConfigMode();
RTC->ALRH_B.ALRH = value >> 16;
RTC->ALRL_B.ALRL = value & 0x0000FFFF;
RTC_DisableConfigMode();
}
/*!
* @brief Reads the RTC divider value.
*
* @param None
*
* @retval RTC Divider value.
*/
uint32_t RTC_ReadDivider(void)
{
uint32_t reg = 0;
reg = (RTC->PSCH_B.PSCH & 0x000F) << 16;
reg |= (RTC->PSCL_B.PSCL);
return (reg);
}
/*!
* @brief Waits until last write operation on RTC registers has finished.
*
* @param None
*
* @retval None
*/
void RTC_WaitForLastTask(void)
{
while(RTC->CSTS_B.OCFLG == BIT_RESET)
{
}
}
/*!
* @brief Waits until the RTC registers
*
* @param None
*
* @retval None
*/
void RTC_WaitForSynchor(void)
{
RTC->CSTS_B.RSYNCFLG = BIT_RESET;
while(RTC->CSTS_B.RSYNCFLG == BIT_RESET);
}
/*!
* @brief Enable RTC interrupts.
*
* @param interrupt: specifies the RTC interrupt sources to be enabled
* This parameter can be any combination of the following values:
* @arg RTC_INT_OVR : Overflow interrupt
* @arg RTC_INT_ALR : Alarm interrupt
* @arg RTC_INT_SEC : Second interrupt
*/
void RTC_EnableInterrupt(uint16_t interrupt)
{
RTC->CTRL |= interrupt;
}
/*!
* @brief Disable RTC interrupts.
*
* @param interrupt: specifies the RTC interrupt sources to be disabled
* This parameter can be any combination of the following values:
* @arg RTC_INT_OVR : Overflow interrupt
* @arg RTC_INT_ALR : Alarm interrupt
* @arg RTC_INT_SEC : Second interrupt
*
* @retval None
*/
void RTC_DisableInterrupt(uint16_t interrupt)
{
RTC->CTRL &= (uint32_t )~interrupt;
}
/*!
* @brief Read flag bit
*
* @param flag: specifies the flag to check.
* This parameter can be one of the following values:
* @arg RTC_FLAG_OC : RTC Operation Complete flag
* @arg RTC_FLAG_RSYNC: Registers Synchronized flag
* @arg RTC_FLAG_OVR : Overflow flag
* @arg RTC_FLAG_ALR : Alarm flag
* @arg RTC_FLAG_SEC : Second flag
*
* @retval SET or RESET
*/
uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag)
{
return (RTC->CSTS & flag) ? SET : RESET;
}
/*!
* @brief Clear flag bit
*
* @param flag: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg RTC_FLAG_OVR : Overflow flag
* @arg RTC_FLAG_ALR : Alarm flag
* @arg RTC_FLAG_SEC : Second flag
*
* @retval None
*/
void RTC_ClearStatusFlag(uint16_t flag)
{
RTC->CSTS &= (uint32_t)~flag;
}
/*!
* @brief Read interrupt flag bit is set
*
* @param flag: specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg RTC_INT_OVR : Overflow interrupt
* @arg RTC_INT_ALR : Alarm interrupt
* @arg RTC_INT_SEC : Second interrupt
*
* @retval None
*/
uint8_t RTC_ReadIntFlag(RTC_INT_T flag)
{
return (RTC->CSTS & flag) ? SET : RESET;
}
/*!
* @brief Clear RTC interrupt flag bit
*
* @param flag: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg RTC_INT_OVR : Overflow interrupt
* @arg RTC_INT_ALR : Alarm interrupt
* @arg RTC_INT_SEC : Second interrupt
*
* @retval None
*/
void RTC_ClearIntFlag(uint16_t flag)
{
RTC->CSTS &= (uint32_t)~flag;
}
/**@} end of group RTC_Fuctions*/
/**@} end of group RTC_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c
+910
View File
@@ -0,0 +1,910 @@
/*!
* @file apm32f10x_sci2c.c
*
* @brief This file contains all the functions for the SCI2C peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_sci2c.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SCI2C_Driver SCI2C Driver
@{
*/
/** @addtogroup SCI2C_Fuctions Fuctions
@{
*/
/*!
* @brief Set I2C peripheral registers to their default reset values
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_Reset(SCI2C_T *i2c)
{
if(i2c == I2C3)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
}
else
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2);
}
i2c->SW = 0;
i2c->SW = 1;
i2c->INTEN = 0;
}
/*!
* @brief Config the I2C peripheral according to the specified parameters in the sci2cConfig
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param sci2cConfig: pointer to a SCI2C_Config_T structure
*
* @retval None
*/
void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
{
i2c->SW = BIT_SET;
i2c->CTRL2_B.I2CEN = BIT_RESET;
if(sci2cConfig->mode == SCI2C_MODE_MASTER)
{
i2c->CTRL1_B.MST = BIT_SET;
i2c->CTRL1_B.SLADIS = BIT_SET;
}
else
{
i2c->CTRL1_B.MST = BIT_RESET;
}
i2c->CTRL1_B.SPD = sci2cConfig->speed;
i2c->CTRL1_B.RSTAEN = sci2cConfig->restart;
i2c->TFT = sci2cConfig->txFifoThreshold;
i2c->RFT = sci2cConfig->rxFifoThreshold;
i2c->TARADDR_B.MAM = sci2cConfig->addrMode;
i2c->CTRL1_B.SAM = sci2cConfig->addrMode;
i2c->SLAADDR = sci2cConfig->slaveAddr;
if(sci2cConfig->speed == SCI2C_SPEED_STANDARD)
{
i2c->SSCLC = sci2cConfig->clkLowPeriod;
i2c->SSCHC = sci2cConfig->clkHighPeriod;
}
else if(sci2cConfig->speed == SCI2C_SPEED_FAST)
{
i2c->FSCLC = sci2cConfig->clkLowPeriod;
i2c->FSCHC = sci2cConfig->clkHighPeriod;
}
else if(sci2cConfig->speed == SCI2C_SPEED_HIGH)
{
i2c->HSCLC = sci2cConfig->clkLowPeriod;
i2c->HSCHC = sci2cConfig->clkHighPeriod;
}
}
/*!
* @brief Fills each sci2cConfig member with its default value
*
* @param sci2cConfig: pointer to a SCI2C_Config_T structure
*
* @retval None
*/
void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig)
{
sci2cConfig->addrMode = SCI2C_ADDR_MODE_7BIT;
sci2cConfig->slaveAddr = 0x55;
sci2cConfig->clkHighPeriod = 0x3C;
sci2cConfig->clkLowPeriod = 0x82;
sci2cConfig->mode = SCI2C_MODE_MASTER;
sci2cConfig->restart = SCI2C_RESTART_ENABLE;
sci2cConfig->rxFifoThreshold = 0;
sci2cConfig->txFifoThreshold = 0;
sci2cConfig->speed = SCI2C_SPEED_FAST;
}
/*!
* @brief Read specified flag
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param flag: Specifies the flag to be checked
* The parameter can be one of following values:
* @arg SCI2C_FLAG_ACT: Activity flag
* @arg SCI2C_FLAG_TFNF: Tx FIFO not full flag
* @arg SCI2C_FLAG_TFE: TX FIFO empty flag
* @arg SCI2C_FLAG_RFNE: Rx FIFO not empty flag
* @arg SCI2C_FLAG_RFF: Rx FIFO full flag
* @arg SCI2C_FLAG_MA: Master activity flag
* @arg SCI2C_FLAG_SA: Slave activity flag
* @arg SCI2C_FLAG_I2CEN: I2C enable flag
* @arg SCI2C_FLAG_SDWB: Slave disable while busy flag
* @arg SCI2C_FLAG_SRDL: Slave receive data lost flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag)
{
uint8_t ret = RESET;
if(flag & BIT8)
{
ret = i2c->STS2 & flag ? SET : RESET;
}
else
{
ret = i2c->STS1 & flag ? SET : RESET;
}
return ret;
}
/*!
* @brief Read specified interrupt flag
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param flag: Specifies the interrupt flag to be checked
* The parameter can be one of following values:
* @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag
* @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag
* @arg SCI2C_INT_RFF: Rx FIFO full interrupt flag
* @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag
* @arg SCI2C_INT_TFE: Tx FIFO empty interrupt flag
* @arg SCI2C_INT_RR: Read request interrupt flag
* @arg SCI2C_INT_TA: Tx abort interrupt flag
* @arg SCI2C_INT_RD: Read done interrupt flag
* @arg SCI2C_INT_ACT: Activity interrupt flag
* @arg SCI2C_INT_STPD: Stop detect interrupt flag
* @arg SCI2C_INT_STAD: Start detect interrupt flag
* @arg SCI2C_INT_GC: Gernal call interrupt flag
* @arg SCI2C_INT_RSTAD: Restart detect interrupt flag
* @arg SCI2C_INT_MOH: Master on hold interrupt flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
{
uint8_t ret = RESET;
ret = i2c->INTSTS & flag ? SET : RESET;
return ret;
}
/*!
* @brief Clear specified interrupt flag
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param flag: Specifies the interrupt flag to be checked
* The parameter can be one of following values:
* @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag
* @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag
* @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag
* @arg SCI2C_INT_RR: Read request interrupt flag
* @arg SCI2C_INT_TA: Tx abort interrupt flag
* @arg SCI2C_INT_RD: Read done interrupt flag
* @arg SCI2C_INT_ACT: Activity interrupt flag
* @arg SCI2C_INT_STPD: Stop detect interrupt flag
* @arg SCI2C_INT_STAD: Start detect interrupt flag
* @arg SCI2C_INT_GC: Gernal call interrupt flag
* @arg SCI2C_INT_ALL: All interrupt flag
* @retval The new state of flag (SET or RESET)
*/
void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
{
volatile uint32_t dummy = 0;
if(flag == SCI2C_INT_ALL)
{
dummy = i2c->INTCLR;
}
else if(flag == SCI2C_INT_RFU)
{
dummy = i2c->RFUIC;
}
else if(flag == SCI2C_INT_RFO)
{
dummy = i2c->RFOIC;
}
else if(flag == SCI2C_INT_TFO)
{
dummy = i2c->TFOIC;
}
else if(flag == SCI2C_INT_RR)
{
dummy = i2c->RRIC;
}
else if(flag == SCI2C_INT_TA)
{
dummy = i2c->TAIC;
}
else if(flag == SCI2C_INT_RD)
{
dummy = i2c->RDIC;
}
else if(flag == SCI2C_INT_ACT)
{
dummy = i2c->AIC;
}
else if(flag == SCI2C_INT_STPD)
{
dummy = i2c->STPDIC;
}
else if(flag == SCI2C_INT_STAD)
{
dummy = i2c->STADIC;
}
else if(flag == SCI2C_INT_GC)
{
dummy = i2c->GCIC;
}
}
/*!
* @brief Read specified interrupt flag(Raw register)
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param flag: Specifies the interrupt flag to be checked
* The parameter can be one of following values:
* @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag
* @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag
* @arg SCI2C_INT_RFF: Rx FIFO full interrupt flag
* @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag
* @arg SCI2C_INT_TFE: Tx FIFO empty interrupt flag
* @arg SCI2C_INT_RR: Read request interrupt flag
* @arg SCI2C_INT_TA: Tx abort interrupt flag
* @arg SCI2C_INT_RD: Read done interrupt flag
* @arg SCI2C_INT_ACT: Activity interrupt flag
* @arg SCI2C_INT_STPD: Stop detect interrupt flag
* @arg SCI2C_INT_STAD: Start detect interrupt flag
* @arg SCI2C_INT_GC: Gernal call interrupt flag
* @arg SCI2C_INT_RSTAD: Restart detect interrupt flag
* @arg SCI2C_INT_MOH: Master on hold interrupt flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
{
uint8_t ret = RESET;
ret = i2c->RIS & flag ? SET : RESET;
return ret;
}
/*!
* @brief Enable the specified interrupts
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param interrupt: Specifies the interrupt sources
* The parameter can be any combination of following values:
* @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt
* @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt
* @arg SCI2C_INT_RFF: Rx FIFO full interrupt
* @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt
* @arg SCI2C_INT_TFE: Tx FIFO empty interrupt
* @arg SCI2C_INT_RR: Read request interrupt
* @arg SCI2C_INT_TA: Tx abort interrupt
* @arg SCI2C_INT_RD: Read done interrupt
* @arg SCI2C_INT_ACT: Activity interrupt
* @arg SCI2C_INT_STPD: Stop detect interrupt
* @arg SCI2C_INT_STAD: Start detect interrupt
* @arg SCI2C_INT_GC: Gernal call interrupt
* @arg SCI2C_INT_RSTAD: Restart detect interrupt
* @arg SCI2C_INT_MOH: Master on hold interrupt
*
* @retval None
*/
void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt)
{
i2c->INTEN |= interrupt;
}
/*!
* @brief Disable the specified interrupts
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param interrupt: Specifies the interrupt sources
* The parameter can be any combination of following values:
* @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt
* @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt
* @arg SCI2C_INT_RFF: Rx FIFO full interrupt
* @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt
* @arg SCI2C_INT_TFE: Tx FIFO empty interrupt
* @arg SCI2C_INT_RR: Read request interrupt
* @arg SCI2C_INT_TA: Tx abort interrupt
* @arg SCI2C_INT_RD: Read done interrupt
* @arg SCI2C_INT_ACT: Activity interrupt
* @arg SCI2C_INT_STPD: Stop detect interrupt
* @arg SCI2C_INT_STAD: Start detect interrupt
* @arg SCI2C_INT_GC: Gernal call interrupt
* @arg SCI2C_INT_RSTAD: Restart detect interrupt
* @arg SCI2C_INT_MOH: Master on hold interrupt
*
* @retval None
*/
void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt)
{
i2c->INTEN &= ~interrupt;
}
/*!
* @brief Enable stop detected only master in activity.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*/
void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c)
{
i2c->CTRL1_B.DSMA = BIT_SET;
}
/*!
* @brief Disable stop detected only master in activity.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*/
void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c)
{
i2c->CTRL1_B.DSMA = BIT_RESET;
}
/*!
* @brief Enable stop detected only address is matched in slave mode.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*/
void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c)
{
i2c->CTRL1_B.DSA = BIT_SET;
}
/*!
* @brief Disable stop detected only address is matched in slave mode.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*/
void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c)
{
i2c->CTRL1_B.DSA = BIT_RESET;
}
/*!
* @brief Enable restart
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_EnableRestart(SCI2C_T *i2c)
{
i2c->CTRL1_B.RSTAEN = BIT_SET;
}
/*!
* @brief Disable restart
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_DisableRestart(SCI2C_T *i2c)
{
i2c->CTRL1_B.RSTAEN = BIT_RESET;
}
/*!
* @brief Config speed.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param speed: Specifies the speed.
* @arg SCI2C_SPEED_STANDARD: Standard speed.
* @arg SCI2C_SPEED_FAST: Fast speed.
* @arg SCI2C_SPEED_HIGH: High speed.
*
* @retval None
*/
void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed)
{
i2c->CTRL1_B.SPD = speed;
}
/*!
* @brief Config master address.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param mode: Specifies the address mode.
* @arg SCI2C_ADDR_MODE_7BIT: 7-bit address mode.
* @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode.
*
* @param addr: Specifies the address.
*
* @retval None
*/
void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
{
i2c->TARADDR_B.MAM = mode;
i2c->TARADDR_B.ADDR = addr;
}
/*!
* @brief Config slave address.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param mode: Specifies the address mode.
* @arg SCI2C_ADDR_MODE_7BIT: 7-bit address mode.
* @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode.
*
* @param addr: Specifies the address.
*
* @retval None
*/
void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
{
i2c->CTRL1_B.SAM = mode;
i2c->SLAADDR = addr;
}
/*!
* @brief Enable master mode
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_EnableMasterMode(SCI2C_T *i2c)
{
i2c->CTRL1_B.MST = BIT_SET;
}
/*!
* @brief Disable master mode
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_DisableMasterMode(SCI2C_T *i2c)
{
i2c->CTRL1_B.MST = BIT_RESET;
}
/*!
* @brief Enable slave mode
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_EnableSlaveMode(SCI2C_T *i2c)
{
i2c->CTRL1_B.SLADIS = BIT_RESET;
}
/*!
* @brief Disable slave mode
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_DisableSlaveMode(SCI2C_T *i2c)
{
i2c->CTRL1_B.SLADIS = BIT_SET;
}
/*!
* @brief Config master code
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param code: Master code
*
* @retval None
*/
void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code)
{
i2c->HSMC = code;
}
/*!
* @brief Config data direction
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param dir: Data direction
* @arg SCI2C_DATA_DIR_WRITE: Write data
* @arg SCI2C_DATA_DIR_READ: Read data
*
* @retval None
*/
void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir)
{
i2c->DATA = (uint32_t)(dir << 8);
}
/*!
* @brief Transmit data
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param data: Data to be transmited
*
* @retval None
*/
void SCI2C_TxData(SCI2C_T *i2c, uint8_t data)
{
i2c->DATA_B.DATA = data;
}
/*!
* @brief Returns the most recent received data
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval Received data
*
*/
uint8_t SCI2C_RxData(SCI2C_T *i2c)
{
return (uint8_t)(i2c->DATA & 0XFF);
}
/*!
* @brief Config data register
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param stop: Enable or disable generate stop condition
*
* @param dataDir: Data direction. Read or write
* @arg SCI2C_DATA_DIR_WRITE: Write data
* @arg SCI2C_DATA_DIR_READ: Read data
*
* @param data: Data to be transmited
*
* @retval None
*/
void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data)
{
i2c->DATA = (uint32_t)((stop << 9) | (dataDir << 8) | data);
}
/*!
* @brief Read Rx FIFO data number
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c)
{
return (uint8_t)i2c->RFL;
}
/*!
* @brief Read Tx FIFO data number
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c)
{
return (uint8_t)i2c->TFL;
}
/*!
* @brief Config Rx FIFO threshold
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param threshold: FIFO threshold
*
* @retval None
*/
void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold)
{
i2c->RFT = threshold;
}
/*!
* @brief Config Tx FIFO threshold
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param threshold: FIFO threshold
*
* @retval None
*/
void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold)
{
i2c->TFT = threshold;
}
/*!
* @brief Enable I2C peripheral
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_Enable(SCI2C_T *i2c)
{
i2c->CTRL2_B.I2CEN = BIT_SET;
}
/*!
* @brief Disable I2C peripheral
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_Disable(SCI2C_T *i2c)
{
i2c->CTRL2_B.I2CEN = BIT_RESET;
}
/*!
* @brief Abort I2C transmit
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval None
*/
void SCI2C_Abort(SCI2C_T *i2c)
{
i2c->CTRL2_B.ABR = BIT_SET;
}
/*!
* @brief Tx command block
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param enable: ENABLE or DISABLE
*
* @retval None
*/
void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable)
{
i2c->CTRL2_B.TCB = enable;
}
/*!
* @brief Config SCL high and low period
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param speed: Specifies the speed.
* @arg SCI2C_SPEED_STANDARD: Standard speed.
* @arg SCI2C_SPEED_FAST: Fast speed.
* @arg SCI2C_SPEED_HIGH: High speed.
*
* @param highPeriod: SCL high period
*
* @param lowPeriod: SCL low period
*
* @retval None
*/
void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod)
{
if(speed == SCI2C_SPEED_STANDARD)
{
i2c->SSCLC = lowPeriod;
i2c->SSCHC = highPeriod;
}
else if(speed == SCI2C_SPEED_FAST)
{
i2c->FSCLC = lowPeriod;
i2c->FSCHC = highPeriod;
}
else if(speed == SCI2C_SPEED_HIGH)
{
i2c->HSCLC = lowPeriod;
i2c->HSCHC = highPeriod;
}
}
/*!
* @brief Config SDA hold time length
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param txHold: Tx SDA hold time length
*
* @param rxHold: Rx SDA hold time length
*
* @retval None
*/
void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold)
{
i2c->SDAHOLD_B.TXHOLD = txHold;
i2c->SDAHOLD_B.RXHOLD = rxHold;
}
/*!
* @brief Config SDA delay time
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param delay: SDA delay time
*
* @retval None
*/
void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay)
{
i2c->SDADLY = delay;
}
/*!
* @brief Enable or disable generate gernal call ack
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param enable: SDA delay time
*
* @retval None
*/
void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable)
{
i2c->GCA = enable;
}
/*!
* @brief When received data no ack generated in slave mode.
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param enable: ENABLE or DISABLE
*
* @retval None
*/
void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable)
{
i2c->SDNO = enable;
}
/*!
* @brief Read Tx abort source
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @retval Return Tx abort source
*/
uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c)
{
return (uint32_t)i2c->TAS;
}
/*!
* @brief Enable DMA
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param dma: DMA requst source
* @arg SCI2C_DMA_RX: DMA RX channel
* @arg SCI2C_DMA_TX: DMA TX channel
*
* @retval None
*/
void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma)
{
i2c->DMACTRL |= dma;
}
/*!
* @brief Disable DMA
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param dma: DMA requst source
* @arg SCI2C_DMA_RX: DMA RX channel
* @arg SCI2C_DMA_TX: DMA TX channel
*
* @retval None
*/
void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma)
{
i2c->DMACTRL &= (uint32_t)~dma;
}
/*!
* @brief Config DMA Tx data level
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param cnt: DMA Tx data level
*
* @retval None
*/
void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt)
{
i2c->DTDL = cnt;
}
/*!
* @brief Config DMA Rx data level
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param cnt: DMA Rx data level
*
* @retval None
*/
void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt)
{
i2c->DRDL = cnt;
}
/*!
* @brief Config spike suppressio limit
*
* @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
*
* @param speed: I2C speed mode
* @arg SCI2C_SPEED_STANDARD: Standard speed.
* @arg SCI2C_SPEED_FAST: Fast speed.
* @arg SCI2C_SPEED_HIGH: High speed.
*
* @param limit: Spike suppressio limit value
*
* @retval None
*/
void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit)
{
if(speed == SCI2C_SPEED_HIGH)
{
i2c->HSSSL = limit;
}
else
{
i2c->LSSSL = limit;
}
}
/**@} end of group SCI2C_Fuctions*/
/**@} end of group SCI2C_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c
+730
View File
@@ -0,0 +1,730 @@
/*!
* @file apm32f10x_sdio.c
*
* @brief This file provides all the SDIO firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_sdio.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SDIO_Driver SDIO Driver
@{
*/
/** @addtogroup SDIO_Fuctions Fuctions
@{
*/
/*!
* @brief Reset sdio peripheral registers to their default reset values
*
* @param None
*
* @retval None
*/
void SDIO_Reset(void)
{
SDIO->PWRCTRL = 0x00000000;
SDIO->CLKCTRL = 0x00000000;
SDIO->ARG = 0x00000000;
SDIO->CMD = 0x00000000;
SDIO->DATATIME = 0x00000000;
SDIO->DATALEN = 0x00000000;
SDIO->DCTRL = 0x00000000;
SDIO->ICF = 0x00C007FF;
SDIO->MASK = 0x00000000;
}
/*!
* @brief Config the SDIO peripheral according to the specified parameters in the sdioConfig
*
* @param sdioConfig: pointer to a SDIO_Config_T structure
*
* @retval None
*/
void SDIO_Config(SDIO_Config_T* sdioConfig)
{
uint32_t tmp = 0;
tmp = SDIO->CLKCTRL;
tmp &= 0xFFFF8100;
tmp |= (sdioConfig->clockDiv | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide |
sdioConfig->clockEdge | sdioConfig->hardwareFlowControl);
SDIO->CLKCTRL = tmp;
}
/*!
* @brief Fills each SDIO_Config_T member with its default value
*
* @param sdioConfig: pointer to a SDIO_Config_T structure
*
* @retval None
*/
void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig)
{
sdioConfig->clockDiv = 0x00;
sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE;
sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
sdioConfig->busWide = SDIO_BUS_WIDE_1B;
sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
}
/*!
* @brief Enables the SDIO clock
*
* @param None
*
* @retval None
*/
void SDIO_EnableClock(void)
{
*(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)SET;
}
/*!
* @brief Disables the SDIO clock
*
* @param None
*
* @retval None
*/
void SDIO_DisableClock(void)
{
*(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)RESET;
}
/*!
* @brief Sets the power status of the controller
*
* @param powerState: new state of the Power state
* The parameter can be one of following values:
* @arg SDIO_POWER_STATE_OFF
* @arg SDIO_POWER_STATE_ON
* @retval None
*/
void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState)
{
SDIO->PWRCTRL &= 0xFFFFFFFC;
SDIO->PWRCTRL |= powerState;
}
/*!
* @brief Reads the SDIO power state
*
* @param None
*
* @retval The new state SDIO power
*
* @note 0x00:Power OFF, 0x02:Power UP, 0x03:Power ON
*/
uint32_t SDIO_ReadPowerState(void)
{
return (SDIO->PWRCTRL & (~0xFFFFFFFC));
}
/*!
* @brief Enables the SDIO DMA request
*
* @param None
*
* @retval None
*/
void SDIO_EnableDMA(void)
{
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)SET;
}
/*!
* @brief Disables the SDIO DMA request
*
* @param None
*
* @retval None
*/
void SDIO_DisableDMA(void)
{
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)RESET;
}
/*!
* @brief Configs the SDIO Command and send the command
*
* @param cmdConfig: pointer to a SDIO_CmdConfig_T structure
*
* @retval None
*
*/
void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
{
uint32_t tmpreg = 0;
SDIO->ARG = cmdConfig->argument;
tmpreg = SDIO->CMD;
tmpreg &= 0xFFFFF800;
tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response
| cmdConfig->wait | cmdConfig->CPSM;
SDIO->CMD = tmpreg;
}
/*!
* @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value
*
* @param cmdConfig: pointer to a SDIO_CmdConfig_T structure
*
* @retval None
*
*/
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdConfig)
{
cmdConfig->argument = 0x00;
cmdConfig->cmdIndex = 0x00;
cmdConfig->response = SDIO_RESPONSE_NO;
cmdConfig->wait = SDIO_WAIT_NO;
cmdConfig->CPSM = SDIO_CPSM_DISABLE;
}
/*!
* @brief Reads the SDIO command response
*
* @param None
*
* @retval The command index of the last command response received
*
*/
uint8_t SDIO_ReadCommandResponse(void)
{
return (uint8_t)(SDIO->CMDRES);
}
/*!
* @brief Reads the SDIO response
*
* @param res: Specifies the SDIO response register
* The parameter can be one of following values:
* @arg SDIO_RES1: Response Register 1
* @arg SDIO_RES2: Response Register 2
* @arg SDIO_RES3: Response Register 3
* @arg SDIO_RES4: Response Register 4
*
* @retval The Corresponding response register value
*/
uint32_t SDIO_ReadResponse(SDIO_RES_T res)
{
__IO uint32_t tmp = 0;
tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
return (*(__IO uint32_t *) tmp);
}
/*!
* @brief Configs the SDIO Dataaccording to the specified parameters in the dataConfig
*
* @param dataConfig: pointer to a SDIO_DataConfig_T structure
*
* @retval None
*/
void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
{
uint32_t tmpreg = 0;
SDIO->DATATIME = dataConfig->dataTimeOut;
SDIO->DATALEN = dataConfig->dataLength;
tmpreg = SDIO->DCTRL;
tmpreg &= 0xFFFFFF08;
tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir
| dataConfig->transferMode | dataConfig->DPSM;
SDIO->DCTRL = tmpreg;
}
/*!
* @brief Fills each SDIO_DataConfig_T member with its default value
*
* @param dataConfig: pointer to a SDIO_DataConfig_T structure
*
* @retval None
*/
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig)
{
dataConfig->dataTimeOut = 0xFFFFFFFF;
dataConfig->dataLength = 0x00;
dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B;
dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD;
dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK;
dataConfig->DPSM = SDIO_DPSM_DISABLE;
}
/*!
* @brief Reads the SDIO Data counter
*
* @param None
*
* @retval The SDIO Data counter value
*/
uint32_t SDIO_ReadDataCounter(void)
{
return SDIO->DCNT;
}
/*!
* @brief Write the SDIO Data
*
* @param Data£ºWrite 32-bit data
*
* @retval None
*/
void SDIO_WriteData(uint32_t data)
{
SDIO->FIFODATA = data;
}
/*!
* @brief Reads the SDIO Data
*
* @param None
*
* @retval The SDIO FIFO Data value
*/
uint32_t SDIO_ReadData(void)
{
return SDIO->FIFODATA;
}
/*!
* @brief Reads the SDIO FIFO count value
*
* @param None
*
* @retval The SDIO FIFO count value
*/
uint32_t SDIO_ReadFIFOCount(void)
{
return SDIO->FIFOCNT;
}
/*!
* @brief Enables SDIO start read wait
*
* @param None
*
* @retval None
*/
void SDIO_EnableStartReadWait(void)
{
*(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) SET;
}
/*!
* @brief Disables SDIO start read wait
*
* @param None
*
* @retval None
*/
void SDIO_DisableStopReadWait(void)
{
*(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) RESET;
}
/*!
* @brief Enables SDIO stop read wait
*
* @param None
*
* @retval None
*/
void SDIO_EnableStopReadWait(void)
{
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) SET;
}
/*!
* @brief Disables SDIO stop read wait
*
* @param None
*
* @retval None
*/
void SDIO_DisableStartReadWait(void)
{
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) RESET;
}
/*!
* @brief Sets the read wait interval
*
* @param readWaitMode: SDIO read Wait Mode
* The parameter can be one of following values:
* @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
* @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
*
* @retval None
*
*/
void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
{
*(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
}
/*!
* @brief Enables SDIO SD I/O Mode Operation
*
* @param None
*
* @retval None
*/
void SDIO_EnableSDIO(void)
{
*(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
}
/*!
* @brief Disables SDIO SD I/O Mode Operation
*
* @param None
*
* @retval None
*/
void SDIO_DisableSDIO(void)
{
*(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
}
/*!
* @brief Ensables SDIO SD I/O Mode suspend command sending
*
* @param None
*
* @retval None
*/
void SDIO_EnableTxSDIOSuspend(void)
{
*(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)SET;
}
/*!
* @brief Disables SDIO SD I/O Mode suspend command sending
*
* @param None
*
* @retval None
*/
void SDIO_DisableTxSDIOSuspend(void)
{
*(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)RESET;
}
/*!
* @brief Enables the command completion signal
*
* @param None
*
* @retval None
*/
void SDIO_EnableCommandCompletion(void)
{
*(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)SET;
}
/*!
* @brief Disables the command completion signal
*
* @param None
*
* @retval None
*/
void SDIO_DisableCommandCompletion(void)
{
*(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)RESET;
}
/*!
* @brief Enables the CE-ATA interrupt
*
* @param None
*
* @retval None
*/
void SDIO_EnableCEATAInterrupt(void)
{
*(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1));
}
/*!
* @brief Disables the CE-ATA interrupt
*
* @param None
*
* @retval None
*/
void SDIO_DisableCEATAInterrupt(void)
{
*(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1));
}
/*!
* @brief Ensables Sends CE-ATA command
*
* @param None
*
* @retval None
*/
void SDIO_EnableTxCEATA(void)
{
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)SET;
}
/*!
* @brief Disables Sends CE-ATA command
*
* @param None
*
* @retval None
*/
void SDIO_DisableTxCEATA(void)
{
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)RESET;
}
/*!
* @brief Enables the specified SDIO interrupt
*
* @param interrupt: Select the SDIO interrupt source
* The parameter can be any combination of following values:
* @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt
* @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
* @arg SDIO_INT_DATATO: Data timeout interrupt
* @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt
* @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt
* @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt
* @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt
* @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt
* @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_INT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_INT_TXACT: Data transmit in progress interrupt
* @arg SDIO_INT_RXACT: Data receive in progress interrupt
* @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt
* @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt
* @arg SDIO_INT_TXFF: Transmit FIFO full interrupt
* @arg SDIO_INT_RXFF: Receive FIFO full interrupt
* @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt
* @arg SDIO_INT_RXFE: Receive FIFO empty interrupt
* @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt
* @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt
* @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
* @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @retval None
*/
void SDIO_EnableInterrupt(uint32_t interrupt)
{
SDIO->MASK |= interrupt;
}
/*!
* @brief Disables the specified SDIO interrupt
*
* @param interrupt: Select the SDIO interrupt source
* The parameter can be any combination of following values:
* @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt
* @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
* @arg SDIO_INT_DATATO: Data timeout interrupt
* @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt
* @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt
* @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt
* @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt
* @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt
* @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_INT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_INT_TXACT: Data transmit in progress interrupt
* @arg SDIO_INT_RXACT: Data receive in progress interrupt
* @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt
* @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt
* @arg SDIO_INT_TXFF: Transmit FIFO full interrupt
* @arg SDIO_INT_RXFF: Receive FIFO full interrupt
* @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt
* @arg SDIO_INT_RXFE: Receive FIFO empty interrupt
* @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt
* @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt
* @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
* @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @retval None
*/
void SDIO_DisableInterrupt(uint32_t interrupt)
{
SDIO->MASK &= ~interrupt;
}
/*!
* @brief Reads the specified SDIO flag
*
* @param flag: Select the flag to read
* The parameter can be one of following values:
* @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag
* @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag
* @arg SDIO_FLAG_CMDRESTO: Command response timeout flag
* @arg SDIO_FLAG_DATATO: Data timeout flag
* @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag
* @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag
* @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag
* @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag
* @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag
* @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag
* @arg SDIO_FLAG_CMDACT: Command transfer in progress flag
* @arg SDIO_FLAG_TXACT: Data transmit in progress flag
* @arg SDIO_FLAG_RXACT: Data receive in progress flag
* @arg SDIO_FLAG_TXFHF: Transmit FIFO Half Empty flag
* @arg SDIO_FLAG_RXFHF: Receive FIFO Half Full flag
* @arg SDIO_FLAG_TXFF: Transmit FIFO full flag
* @arg SDIO_FLAG_RXFF: Receive FIFO full flag
* @arg SDIO_FLAG_TXFE: Transmit FIFO empty flag
* @arg SDIO_FLAG_RXFE: Receive FIFO empty flag
* @arg SDIO_FLAG_TXDA: Data available in transmit FIFO flag
* @arg SDIO_FLAG_RXDA: Data available in receive FIFO flag
* @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
* @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag
*
* @retval SET or RESET
*/
uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag)
{
return (SDIO->STS & flag) ? SET : RESET;
}
/*!
* @brief Clears the specified SDIO flag
*
* @param flag: Select the flag to clear
* The parameter can be any combination of following values:
* @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag
* @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag
* @arg SDIO_FLAG_CMDRESTO: Command response timeout flag
* @arg SDIO_FLAG_DATATO: Data timeout flag
* @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag
* @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag
* @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag
* @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag
* @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag
* @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag
* @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
* @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag
*
* @retval None
*/
void SDIO_ClearStatusFlag(uint32_t flag)
{
SDIO->ICF = flag;
}
/*!
* @brief Reads the specified SDIO Interrupt flag
*
* @param flag: Select the SDIO interrupt source
* The parameter can be one of following values:
* @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt
* @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
* @arg SDIO_INT_DATATO: Data timeout interrupt
* @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt
* @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt
* @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt
* @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt
* @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt
* @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_INT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_INT_TXACT: Data transmit in progress interrupt
* @arg SDIO_INT_RXACT: Data receive in progress interrupt
* @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt
* @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt
* @arg SDIO_INT_TXFF: Transmit FIFO full interrupt
* @arg SDIO_INT_RXFF: Receive FIFO full interrupt
* @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt
* @arg SDIO_INT_RXFE: Receive FIFO empty interrupt
* @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt
* @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt
* @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
* @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
*
* @retval SET or RESET
*/
uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag)
{
uint32_t intEnable;
uint32_t intStatus;
intEnable = (uint32_t)(SDIO->MASK & flag);
intStatus = (uint32_t)(SDIO->STS & flag);
if (intEnable && intStatus)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the specified SDIO Interrupt pending bits
*
* @param flag: Select the SDIO interrupt source
* The parameter can be any combination of following values:
* @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt
* @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
* @arg SDIO_INT_DATATO: Data timeout interrupt
* @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt
* @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt
* @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt
* @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt
* @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt
* @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
* @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
*
* @retval None
*/
void SDIO_ClearIntFlag(uint32_t flag)
{
SDIO->ICF = flag;
}
/**@} end of group SDIO_Fuctions*/
/**@} end of group SDIO_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c
+618
View File
@@ -0,0 +1,618 @@
/*!
* @file apm32f10x_spi.c
*
* @brief This file provides all the SPI firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_spi.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup SPI_Driver SPI Driver
@{
*/
/** @addtogroup SPI_Fuctions Fuctions
@{
*/
/*!
* @brief Reset the specified SPIx peripheral
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_I2S_Reset(SPI_T* spi)
{
if(spi == SPI1)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
}
else if(spi == SPI2)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
}
else if(spi == SPI3)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
}
}
/*!
* @brief Config the SPI peripheral according to the specified parameters in the spiConfig
*
* @param spi: The SPIx can be 1,2,3
*
* @param spiConfig: pointer to a SPI_Config_T structure
*
* @retval None
*/
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
{
spi->CTRL1 &= 0x3040;
spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode |
spiConfig->length | spiConfig->polarity |
spiConfig->phase | spiConfig->nss |
spiConfig->baudrateDiv | spiConfig->firstBit);
spi->CRCPOLY = spiConfig->crcPolynomial;
}
/*!
* @brief Config the I2S peripheral according to the specified parameters in the spiConfig
*
* @param spi: The SPIx can be 2,3
*
* @param i2sConfig: pointer to a I2S_Config_T structure
*
* @retval None
*/
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
{
uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1;
uint32_t tmp = 0;
uint32_t sysClock = 0;
/** Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */
spi->I2SCFG &= 0xF040;
spi->I2SPSC = 0x0002;
if(i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
{
spi->I2SPSC_B.ODDPSC = 0;
spi->I2SPSC_B.I2SPSC = 2;
}
else
{
if(i2sConfig->length == I2S_DATA_LENGHT_16B)
{
packetSize = 1;
}
else
{
packetSize = 2;
}
sysClock = RCM_ReadSYSCLKFreq();
if(i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
{
tmp = (uint16_t)(((((sysClock / 256) * 10) / i2sConfig ->audioDiv)) + 5);
}
else
{
tmp = (uint16_t)(((((sysClock / (32 * packetSize)) *10 ) / i2sConfig ->audioDiv )) + 5);
}
tmp = tmp / 10;
i2sOdd = (uint16_t)(tmp & (uint16_t)0x0001);
i2sDiv = (uint16_t)((tmp - i2sOdd) / 2);
if ((i2sDiv < 2) || (i2sDiv > 0xFF))
{
i2sDiv = 2;
i2sOdd = 0;
}
}
spi->I2SPSC_B.I2SPSC = i2sDiv;
spi->I2SPSC_B.ODDPSC = i2sOdd;
spi->I2SPSC |= i2sConfig->MCLKOutput;
spi->I2SCFG = (uint32_t)i2sConfig->mode | \
(uint32_t)i2sConfig->standard | \
(uint32_t)i2sConfig->length | \
(uint32_t)i2sConfig->polarity;
/** select I2S mode */
spi->I2SCFG_B.MODESEL = BIT_SET;
}
/*!
* @brief Fills each SPI_Config_T member with its default value
*
* @param spiConfig: pointer to a SPI_Config_T structure
*
* @retval None
*/
void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
{
spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX;
spiConfig->mode = SPI_MODE_SLAVE;
spiConfig->length = SPI_DATA_LENGTH_8B;
spiConfig->polarity = SPI_CLKPOL_LOW;
spiConfig->phase = SPI_CLKPHA_1EDGE;
spiConfig->nss = SPI_NSS_HARD;
spiConfig->baudrateDiv = SPI_BAUDRATE_DIV_2;
spiConfig->firstBit = SPI_FIRSTBIT_MSB;
spiConfig->crcPolynomial = 7;
}
/*!
* @brief Fills each I2S_Config_T member with its default value
*
* @param i2sConfig: pointer to a I2S_Config_T structure
*
* @retval None
*/
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
{
i2sConfig->mode = I2S_MODE_SLAVE_TX;
i2sConfig->standard = I2S_STANDARD_PHILLIPS;
i2sConfig->length = I2S_DATA_LENGHT_16B;
i2sConfig->MCLKOutput = I2S_MCLK_OUTPUT_DISABLE;
i2sConfig->audioDiv = I2S_AUDIO_DIV_DEFAULT;
i2sConfig->polarity = I2S_CLKPOL_LOW;
}
/*!
* @brief Enables the specified SPI peripheral
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_Enable(SPI_T* spi)
{
spi->CTRL1_B.SPIEN = BIT_SET;
}
/*!
* @brief Disable the specified SPI peripheral
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_Disable(SPI_T* spi)
{
spi->CTRL1_B.SPIEN = BIT_RESET;
}
/*!
* @brief Enables the specified I2S peripheral
*
* @param spi: The I2S can be SPI2,SPI3
*
* @retval None
*/
void I2S_Enable(SPI_T* spi)
{
spi->I2SCFG_B.I2SEN = BIT_SET;
}
/*!
* @brief Disable the specified I2S peripheral
*
* @param spi: The I2S can be SPI2,SPI3
*
* @retval None
*/
void I2S_Disable(SPI_T* spi)
{
spi->I2SCFG_B.I2SEN = BIT_RESET;
}
/*!
* @brief Enables the SPIx/I2Sx DMA interface.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @param dmaReq: specifies the SPI/I2S DMA transfer request
* The parameter can be one of following values:
* @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request
* @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
* @retval None
*/
void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
{
if(dmaReq == SPI_I2S_DMA_REQ_TX)
{
spi->CTRL2_B.TXDEN = ENABLE;
}
else
{
spi->CTRL2_B.RXDEN = ENABLE;
}
}
/*!
* @brief Disables the SPIx/I2Sx DMA interface.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @param dmaReq: specifies the SPI/I2S DMA transfer request
* The parameter can be one of following values:
* @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request
* @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
* @retval None
*/
void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
{
if(dmaReq == SPI_I2S_DMA_REQ_TX)
{
spi->CTRL2_B.TXDEN = DISABLE;
}
else
{
spi->CTRL2_B.RXDEN = DISABLE;
}
}
/*!
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @param data: Data to be transmitted
*
* @retval None
*/
void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
{
spi->DATA = data;
}
/*!
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @retval data :The value of the received data
*
* @retval None
*/
uint16_t SPI_I2S_RxData(SPI_T* spi)
{
return spi->DATA;
}
/*!
* @brief Set the SPI NSS internal by Software
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_SetSoftwareNSS(SPI_T* spi)
{
spi->CTRL1_B.ISSEL = BIT_SET;
}
/*!
* @brief Reset the SPI NSS internal by Software
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_ResetSoftwareNSS(SPI_T* spi)
{
spi->CTRL1_B.ISSEL = BIT_RESET;
}
/*!
* @brief Enables the specified SPI SS output
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_EnableSSOutput(SPI_T* spi)
{
spi->CTRL2_B.SSOEN = BIT_SET;
}
/*!
* @brief Disable the specified SPI SS output
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_DisableSSOutput(SPI_T* spi)
{
spi->CTRL2_B.SSOEN = BIT_RESET;
}
/*!
* @brief Configures the specified SPI data size
*
* @param spi: The SPIx can be 1,2,3
*
* @param length: specifies the SPI data size.
* This parameter can be one of the following values:
* @arg SPI_DATA_LENGTH_16B: Set data frame format to 16bit
* @arg SPI_DATA_LENGTH_8B : Set data frame format to 8bit
*
* @retval None
*/
void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length)
{
spi->CTRL1_B.DFLSEL = BIT_RESET;
spi->CTRL1 |= length;
}
/*!
* @brief Transmit CRC value
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_TxCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCNXT = BIT_SET;
}
/*!
* @brief Enables the specified SPI CRC value calculation of the transferred bytes
*
* @param spi: The SPIx can be 1,2,3
*
* @retval None
*/
void SPI_EnableCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCEN = BIT_SET;
}
/*!
* @brief Disable the specified SPI CRC value calculation of the transferred bytes
*
* @param spi: The SPIx can be 1,2,3
*
*/
void SPI_DisableCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCEN = BIT_RESET;
}
/*!
* @brief Reads the specified SPI transmit CRC register value
*
* @param spi: The SPIx can be 1,2,3
*
* @retval The SPI transmit CRC register value
*/
uint16_t SPI_ReadTxCRC(SPI_T* spi)
{
return spi->TXCRC_B.TXCRC;
}
/*!
* @brief Reads the specified SPI receive CRC register value
*
* @param spi: The SPIx can be 1,2,3
*
* @retval The SPI receive CRC register value
*/
uint16_t SPI_ReadRxCRC(SPI_T* spi)
{
return spi->RXCRC_B.RXCRC;
}
/*!
* @brief Reads the specified SPI CRC Polynomial register value
*
* @param spi: The SPIx can be 1,2,3
*
* @retval The SPI CRC Polynomial register value
*/
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
{
return spi->CRCPOLY_B.CRCPOLY;
}
/*!
* @brief Configures the specified SPI data transfer direction
*
* @param spi: The SPIx can be 1,2,3
*
* @param direction: Select the SPI data transfer direction
* The parameter can be one of following values:
* @arg SPI_DIRECTION_RX: Selects Rx receive direction
* @arg SPI_DIRECTION_TX: Selects Tx transmission direction
* @retval None
*/
void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
{
if(direction == SPI_DIRECTION_TX)
{
spi->CTRL1 |= SPI_DIRECTION_TX;
}
else
{
spi->CTRL1 &= SPI_DIRECTION_RX;
}
}
/*!
* @brief Enables the specified SPI/I2S interrupts.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @param interrupt: specifies the TMR interrupts sources
* The parameter can be one of following values:
* @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt
* @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt
* @arg SPI_I2S_INT_ERR: Error interrupt
* @retval None
*/
void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
{
spi->CTRL2 |= (interrupt >> 8);
}
/*!
* @brief Disables the specified SPI/I2S interrupts.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @param interrupt: specifies the TMR interrupts sources
* The parameter can be one of following values:
* @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt
* @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt
* @arg SPI_I2S_INT_ERR: Error interrupt
* @retval None
*/
void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
{
spi->CTRL2 &= ~(interrupt >> 8);
}
/*!
* @brief Checks whether the specified SPI/I2S flag is set or not.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @param flag: specifies the SPI/I2S flag to check
* The parameter can be one of following values:
* @arg SPI_FLAG_RXBNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXBE: Transmit buffer empty flag
* @arg I2S_FLAG_SCHDIR: Side Channel flag
* @arg I2S_FLAG_UDR: Underrun Error flag
* @arg SPI_FLAG_CRCE: CRC Error flag
* @arg SPI_FLAG_ME: Mode Error flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
*
* @retval SET or RESET
*/
uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
{
if((spi->STS & flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*!
* @brief Clears the SPIx CRC Error flag
*
* @param spi: The SPIx can be 1,2,3
*
* @param flag: only clears SPI_FLAG_CRCE(CRC Error flag)
*
* @retval None
*
* @note 1)SPI_FLAG_OVR: (OverRun error) flag is cleared by software sequence:
* a read operation to SPI_DATA register (SPI_I2S_RxData())
* followed by a read operation to SPI_STS register (SPI_I2S_ReadStatusFlag()).
* 2)I2S_FLAG_UDR: (UnderRun error) flag is cleared:
* a read operation to SPI_STS register (SPI_I2S_ReadStatusFlag()).
* 3)SPI_FLAG_ME: (Mode Fault) flag is cleared by software sequence:
* a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag())
* followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
*/
void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
{
spi->STS_B.CRCEFLG = BIT_RESET;
}
/*!
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
*
* @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3
*
* @param flag: specifies the SPI/I2S interrupt flag to check.
* The parameter can be one of following values:
* @arg SPI_I2S_INT_RXBNE: Receive buffer not empty interrupt flag
* @arg SPI_I2S_INT_TXBE: Transmit buffer empty interrupt flag
* @arg SPI_I2S_INT_OVR: Overrun interrupt flag
* @arg SPI_INT_CRCE: CRC Error interrupt flag
* @arg SPI_INT_ME: Mode Error interrupt flag
* @arg I2S_INT_UDR: Underrun Error interrupt flag
*
* @retval SET or RESET
*/
uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
{
uint32_t intEnable;
uint32_t intStatus;
intEnable = (uint32_t)(spi->CTRL2 & (flag>>8));
intStatus = (uint32_t)(spi->STS & flag);
if (intEnable && intStatus)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the SPIx CRC Error interrupt flag
*
* @param spi: The SPIx can be 1,2,3
*
* @param flag: only clears SPI_INT_CRCE(CRC Error interrupt flag)
*
* @retval None
*
* @note 1)SPI_I2S_INT_OVR: (OverRun interrupt error) flag is cleared by software sequence:
* a read operation to SPI_DATA register (SPI_I2S_RxData())
* followed by a read operation to SPI_STS register (SPI_I2S_ReadIntFlag()).
* 2)I2S_INT_UDR: (UnderRun interrupt error) flag is cleared:
* a read operation to SPI_STS register (SPI_I2S_ReadIntFlag()).
* 3)SPI_INT_ME: (Mode interrupt Fault) flag is cleared by software sequence:
* a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag())
* followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
*/
void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
{
spi->STS_B.CRCEFLG = BIT_RESET;
}
/**@} end of group SPI_Fuctions*/
/**@} end of group SPI_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c
+2137
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c
+831
View File
@@ -0,0 +1,831 @@
/*!
* @file apm32f10x_usart.c
*
* @brief This file provides all the USART firmware functions
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_usart.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup USART_Driver USART Driver
@{
*/
/** @addtogroup USART_Fuctions Fuctions
@{
*/
/*!
* @brief Reset usart peripheral registers to their default reset values
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Reset(USART_T* usart)
{
if (USART1 == usart)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_USART1);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_USART1);
}
else if (USART2 == usart)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART2);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART2);
}
else if (USART3 == usart)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART3);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART3);
}
else if (UART4 == usart)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_UART4);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_UART4);
}
else if (UART5 == usart)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_UART5);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_UART5);
}
}
/*!
* @brief Config the USART peripheral according to the specified parameters in the usartConfig
*
* @param uart: Select the USART or the UART peripheral
*
* @param usartConfig: pointer to a USART_Config_T structure
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Config(USART_T* uart, USART_Config_T* usartConfig)
{
uint32_t temp, fCLK, intDiv, fractionalDiv;
temp = uart->CTRL1;
temp &= 0xE9F3;
temp |= (uint32_t)usartConfig->mode | \
(uint32_t)usartConfig->parity | \
(uint32_t)usartConfig->wordLength;
uart->CTRL1 = temp;
temp = uart->CTRL2;
temp &= 0xCFFF;
temp |= usartConfig->stopBits;
uart->CTRL2 = temp;
temp = uart->CTRL3;
temp &= 0xFCFF;
temp |= (uint32_t)usartConfig->hardwareFlow;
uart->CTRL3 = temp;
if (uart == USART1)
{
RCM_ReadPCLKFreq(NULL, &fCLK);
}
else
{
RCM_ReadPCLKFreq(&fCLK, NULL);
}
intDiv = ((25 * fCLK) / (4 * (usartConfig->baudRate)));
temp = (intDiv / 100) << 4;
fractionalDiv = intDiv - (100 * (temp >> 4));
temp |= ((((fractionalDiv * 16) + 50) / 100)) & ((uint8_t)0x0F);
uart->BR = temp;
}
/*!
* @brief Fills each USART_InitStruct member with its default value
*
* @param usartConfig: pointer to a USART_Config_T structure which will be initialized
*
* @retval None
*/
void USART_ConfigStructInit(USART_Config_T* usartConfig)
{
usartConfig->baudRate = 9600;
usartConfig->wordLength = USART_WORD_LEN_8B;
usartConfig->stopBits = USART_STOP_BIT_1;
usartConfig->parity = USART_PARITY_NONE ;
usartConfig->mode = USART_MODE_TX_RX;
usartConfig->hardwareFlow = USART_HARDWARE_FLOW_NONE;
}
/*!
* @brief Configuration communication clock
*
* @param usart: Select the USART or the UART peripheral
*
* @param clockConfig: Pointer to a USART_clockConfig_T structure
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3
*/
void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
{
usart->CTRL2_B.CLKEN = clockConfig->clock;
usart->CTRL2_B.CPHA = clockConfig->phase;
usart->CTRL2_B.CPOL = clockConfig->polarity;
usart->CTRL2_B.LBCPOEN = clockConfig->lastBit;
}
/*!
* @brief Fills each clockConfig member with its default value
*
* @param clockConfig: Pointer to a USART_clockConfig_T structure
*
* @retval None
*
*/
void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
{
clockConfig->clock = USART_CLKEN_DISABLE;
clockConfig->phase = USART_CLKPHA_1EDGE;
clockConfig->polarity = USART_CLKPOL_LOW;
clockConfig->lastBit = USART_LBCP_DISABLE;
}
/*!
* @brief Enables the specified USART peripheral
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Enable(USART_T* usart)
{
usart->CTRL1_B.UEN = BIT_SET;
}
/*!
* @brief Disable the specified USART peripheral
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Disable(USART_T* usart)
{
usart->CTRL1_B.UEN = BIT_RESET;
}
/*!
* @brief Enables the USART DMA interface
*
* @param usart: Select the USART or the UART peripheral
*
* @param dmaReq: Specifies the DMA request
* This parameter can be one of the following values:
* @arg USART_DMA_TX: USART DMA receive request
* @arg USART_DMA_RX: USART DMA transmit request
* @arg USART_DMA_TX_RX: USART DMA transmit/receive request
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
{
usart->CTRL3 |= dmaReq;
}
/*!
* @brief Disable the USART DMA interface
*
* @param usart: Select the USART or the UART peripheral
*
* @param dmaReq: Specifies the DMA request
* This parameter can be one of the following values:
* @arg USART_DMA_TX: USART DMA receive request
* @arg USART_DMA_RX: USART DMA transmit request
* @arg USART_DMA_TX_RX: USART DMA transmit/receive request
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
{
usart->CTRL3 &= (uint32_t)~dmaReq;
}
/*!
* @brief Configures the address of the USART node
*
* @param usart: Select the USART or the UART peripheral
*
* @param address: Indicates the address of the USART node
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Address(USART_T* usart, uint8_t address)
{
usart->CTRL2_B.ADDR = address;
}
/*!
* @brief Selects the USART WakeUp method.
*
* @param usart: Select the USART or the UART peripheral
*
* @param wakeup: Specifies the selected USART auto baud rate method
* This parameter can be one of the following values:
* @arg USART_WAKEUP_IDLE_LINE: WakeUp by an idle line detection
* @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
{
usart->CTRL1_B.WUPMCFG = wakeup;
}
/*!
* @brief Enable USART Receiver in mute mode
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableMuteMode(USART_T* usart)
{
usart->CTRL1_B.RXMUTEEN = BIT_SET;
}
/*!
* @brief Disable USART Receiver in active mode
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableMuteMode(USART_T* usart)
{
usart->CTRL1_B.RXMUTEEN = BIT_RESET;
}
/*!
* @brief Sets the USART LIN Break detection length
*
* @param usart: Select the USART or the UART peripheral
*
* @param length: Specifies the LIN break detection length
* This parameter can be one of the following values:
* @arg USART_LBDL_10B: 10-bit break detection
* @arg USART_LBDL_10B: 11-bit break detection
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
{
usart->CTRL2_B.LBDLCFG = length;
}
/*!
* @brief Enables the USART LIN MODE
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableLIN(USART_T* usart)
{
usart->CTRL2_B.LINMEN = BIT_SET;
}
/*!
* @brief Disable the USART LIN MODE
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableLIN(USART_T* usart)
{
usart->CTRL2_B.LINMEN = BIT_RESET;
}
/*!
* @brief Transmitter Enable
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableTx(USART_T* usart)
{
usart->CTRL1_B.TXEN = BIT_SET;
}
/*!
* @brief Transmitter Disable
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableTx(USART_T* usart)
{
usart->CTRL1_B.TXEN = BIT_RESET;
}
/*!
* @brief Receiver enable
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableRx(USART_T* usart)
{
usart->CTRL1_B.RXEN = BIT_SET;
}
/*!
* @brief Receiver disable
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableRx(USART_T* usart)
{
usart->CTRL1_B.RXEN = BIT_RESET;
}
/*!
* @brief Transmits single data
*
* @param usart: Select the USART or the UART peripheral
*
* @param data: the data to transmit
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_TxData(USART_T* usart, uint16_t data)
{
usart->DATA_B.DATA = data;
}
/*!
* @brief Returns the most recent received data
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
uint16_t USART_RxData(USART_T* usart)
{
return (uint16_t)(usart->DATA_B.DATA);
}
/*!
* @brief Transmits break characters
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_TxBreak(USART_T* usart)
{
usart->CTRL1_B.TXBF = BIT_SET;
}
/*!
* @brief Sets the specified USART guard time
*
* @param usart: Select the USART or the UART peripheral
*
* @param guardTime: Specifies the guard time
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3
*/
void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
{
usart->GTPSC_B.GRDT = guardTime;
}
/*!
* @brief Sets the system clock divider number
*
* @param usart: Select the USART or the UART peripheral
*
* @param div: specifies the divider number
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3
*/
void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
{
usart->GTPSC_B.PSC = div;
}
/*!
* @brief Enables the USART Smart Card mode
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_EnableSmartCard(USART_T* usart)
{
usart->CTRL3_B.SCEN = BIT_SET;
}
/*!
* @brief Disable the USART Smart Card mode
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_DisableSmartCard(USART_T* usart)
{
usart->CTRL3_B.SCEN = BIT_RESET;
}
/*!
* @brief Enables NACK transmission
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_EnableSmartCardNACK(USART_T* usart)
{
usart->CTRL3_B.SCNACKEN = BIT_SET;
}
/*!
* @brief Disable NACK transmission
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_DisableSmartCardNACK(USART_T* usart)
{
usart->CTRL3_B.SCNACKEN = BIT_RESET;
}
/*!
* @brief Enables USART Half Duplex communication
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableHalfDuplex(USART_T* usart)
{
usart->CTRL3_B.HDEN = BIT_SET;
}
/*!
* @brief Disable USART Half Duplex communication
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableHalfDuplex(USART_T* usart)
{
usart->CTRL3_B.HDEN = BIT_RESET;
}
/*!
* @brief Configures the USART's IrDA interface
*
* @param usart: Select the USART or the UART peripheral
*
* @param IrDAMode: Specifies the IrDA mode
* This parameter can be one of the following values:
* @arg USART_IRDALP_NORMAL: Normal
* @arg USART_IRDALP_LOWPOWER: Low-Power
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
{
usart->CTRL3_B.IRLPEN = IrDAMode;
}
/*!
* @brief Enables the USART's IrDA interface
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableIrDA(USART_T* usart)
{
usart->CTRL3_B.IREN = BIT_SET;
}
/*!
* @brief Disable the USART's IrDA interface
*
* @param usart: Select the USART or the UART peripheral
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableIrDA(USART_T* usart)
{
usart->CTRL3_B.IREN = BIT_RESET;
}
/*!
* @brief Enable the specified USART interrupts
*
* @param usart: Select the USART or the UART peripheral
*
* @param interrupt: Specifies the USART interrupts sources
* The parameter can be one of following values:
* @arg USART_INT_PE: Parity error interrupt
* @arg USART_INT_TXBE: Tansmit data buffer empty interrupt
* @arg USART_INT_TXC: Transmission complete interrupt
* @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
* @arg USART_INT_IDLE: Idle line detection interrupt
* @arg USART_INT_LBD: LIN break detection interrupt
* @arg USART_INT_CTS: CTS change interrupt
* @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error)
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
{
uint32_t temp;
temp = (uint32_t)(interrupt & 0xffff);
if (interrupt & 0x10000)
{
usart->CTRL1 |= temp;
}
if (interrupt & 0x20000)
{
usart->CTRL2 |= temp;
}
if (interrupt & 0x40000)
{
usart->CTRL3 |= temp;
}
}
/*!
* @brief Disables the specified USART interrupts
*
* @param usart: Select the USART or the UART peripheral
*
* @param interrupt: Specifies the USART interrupts sources
* The parameter can be one of following values:
* @arg USART_INT_PE: Parity error interrupt
* @arg USART_INT_TXBE: Tansmit data buffer empty interrupt
* @arg USART_INT_TXC: Transmission complete interrupt
* @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
* @arg USART_INT_IDLE: Idle line detection interrupt
* @arg USART_INT_LBD: LIN break detection interrupt
* @arg USART_INT_CTS: CTS change interrupt
* @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error)
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
{
uint32_t temp;
temp = (uint32_t)~(interrupt & 0xffff);
if (interrupt & 0x10000)
{
usart->CTRL1 &= temp;
}
if (interrupt & 0x20000)
{
usart->CTRL2 &= temp;
}
if (interrupt & 0x40000)
{
usart->CTRL3 &= temp;
}
}
/*!
* @brief Read the specified USART flag
*
* @param usart: Select the USART or the UART peripheral
*
* @param flag: Specifies the flag to check
* The parameter can be one of following values:
* @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
* @arg USART_FLAG_LBD: LIN Break detection flag
* @arg USART_FLAG_TXBE: Transmit data buffer empty flag
* @arg USART_FLAG_TXC: Transmission Complete flag
* @arg USART_FLAG_RXBNE: Receive data buffer not empty flag
* @arg USART_FLAG_IDLE: Idle Line detection flag
* @arg USART_FLAG_OVRE: OverRun Error flag
* @arg USART_FLAG_NE: Noise Error flag
* @arg USART_FLAG_FE: Framing Error flag
* @arg USART_FLAG_PE: Parity Error flag
*
* @retval The new state of flag (SET or RESET)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
{
return (usart->STS & flag) ? SET : RESET;
}
/*!
* @brief Clears the USARTx's pending flags
*
* @param usart: Select the USART or the UART peripheral
*
* @param flag: Specifies the flag to clear
* The parameter can be one of following values:
* @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
* @arg USART_FLAG_LBD: LIN Break detection flag
* @arg USART_FLAG_TXC: Transmission Complete flag
* @arg USART_FLAG_RXBNE: Receive data buffer not empty flag
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
{
usart->STS &= (uint32_t)~flag;
}
/*!
* @brief Read the specified USART interrupt flag
*
* @param usart: Select the USART or the UART peripheral
*
* @param flag: Specifies the USART interrupt source to check
* The parameter can be one of following values:
* @arg USART_INT_TXBE: Tansmit data buffer empty interrupt
* @arg USART_INT_TXC: Transmission complete interrupt
* @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
* @arg USART_INT_IDLE: Idle line detection interrupt
* @arg USART_INT_LBD: LIN break detection interrupt
* @arg USART_INT_CTS: CTS change interrupt
* @arg USART_INT_OVRE: OverRun Error interruptpt
* @arg USART_INT_NE: Noise Error interrupt
* @arg USART_INT_FE: Framing Error interrupt
* @arg USART_INT_PE: Parity error interrupt
*
* @retval The new state of flag (SET or RESET)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
{
uint32_t itFlag, srFlag;
if (flag & 0x10000)
{
itFlag = usart->CTRL1 & flag & 0xffff;
}
else if (flag & 0x20000)
{
itFlag = usart->CTRL2 & flag & 0xffff;
}
else
{
itFlag = usart->CTRL3 & flag & 0xffff;
}
srFlag = flag >> 24;
srFlag = (uint32_t)(1 << srFlag);
srFlag = usart->STS & srFlag;
if (srFlag && itFlag)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the USART interrupt pending bits
*
* @param usart: Select the USART or the UART peripheral
*
* @param flag: Specifies the interrupt pending bit to clear
* The parameter can be one of following values:
* @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
* @arg USART_INT_TXC: Transmission complete interrupt
* @arg USART_INT_LBD: LIN break detection interrupt
* @arg USART_INT_CTS: CTS change interrupt
*
* @retval None
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag)
{
uint32_t srFlag;
srFlag = flag >> 24;
srFlag = (uint32_t)(1 << srFlag);
usart->STS &= (uint32_t)~srFlag;
}
/**@} end of group USART_Fuctions*/
/**@} end of group USART_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c
+159
View File
@@ -0,0 +1,159 @@
/*!
* @file apm32f10x_wwdt.c
*
* @brief This file contains all the functions for the WWDT peripheral
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x_wwdt.h"
#include "apm32f10x_rcm.h"
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup WWDT_Fuctions Fuctions
@{
*/
/*!
* @brief Reset the WWDT peripheral registers
*
* @param None
*
* @retval None
*/
void WWDT_Reset(void)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT);
}
/*!
* @brief Config the WWDT Timebase
*
* @param timebase: WWDT Prescaler
* The parameter can be one of following values:
* @arg WWDT_TIME_BASE_1: WWDT counter clock = (PCLK1/4096)/1
* @arg WWDT_TIME_BASE_2: WWDT counter clock = (PCLK1/4096)/2
* @arg WWDT_TIME_BASE_4: WWDT counter clock = (PCLK1/4096)/4
* @arg WWDT_TIME_BASE_8: WWDT counter clock = (PCLK1/4096)/8
*
* @retval None
*/
void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase)
{
__IO uint32_t reg;
reg = WWDT->CFG & 0xFFFFFE7F;
reg |= timeBase;
WWDT->CFG = reg;
}
/*!
* @brief Config the WWDT Window data
*
* @param windowdata: window data which compare with the downcounter
*
* @retval None
*
* @note The windowdata must be lower than 0x80
*/
void WWDT_ConfigWindowData(uint8_t windowData)
{
__IO uint32_t reg;
reg = WWDT->CFG & 0xFFFFFF80;
reg |= windowData & 0x7F;
WWDT->CFG = reg;
}
/*!
* @brief Config the WWDT counter value
*
* @param counter: Specifies the watchdog counter value
*
* @retval None
*
* @note The counter between 0x40 and 0x7F
*/
void WWDT_ConfigCounter(uint8_t counter)
{
WWDT->CTRL = counter & 0x7F;
}
/*!
* @brief Enable the WWDT Early Wakeup interrupt
*
* @param None
*
* @retval None
*/
void WWDT_EnableEWI(void)
{
WWDT->CFG_B.EWIEN = SET;
}
/*!
* @brief Enable WWDT and set the counter value
*
* @param counter: the window watchdog counter value
*
* @retval None
*
* @note The counter between 0x40 and 0x7F
*/
void WWDT_Enable(uint8_t counter)
{
WWDT->CTRL = counter | 0x00000080;
}
/*!
* @brief Read the Early Wakeup interrupt flag
*
* @param None
*
* @retval the state of the Early Wakeup interrupt flagte
*/
uint8_t WWDT_ReadFlag(void)
{
return (uint8_t) (WWDT->STS);
}
/*!
* @brief Clear the Early Wakeup interrupt flag
*
* @param None
*
* @retval None
*/
void WWDT_ClearFlag(void)
{
WWDT->STS_B.EWIFLG = RESET;
}
/**@} end of group WWDT_Fuctions*/
/**@} end of group WWDT_Driver*/
/**@} end of group Peripherals_Library*/
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/LICENSE.txt
+176
View File
@@ -0,0 +1,176 @@
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all
other entities that control, are controlled by, or are under common
control with that entity. For the purposes of this definition,
"control" means (i) the power, direct or indirect, to cause the
direction or management of such entity, whether by contract or
otherwise, or (ii) ownership of fifty percent (50%) or more of the
outstanding shares, or (iii) beneficial ownership of such entity.
"You" (or "Your") shall mean an individual or Legal Entity
exercising permissions granted by this License.
"Source" form shall mean the preferred form for making modifications,
including but not limited to software source code, documentation
source, and configuration files.
"Object" form shall mean any form resulting from mechanical
transformation or translation of a Source form, including but
not limited to compiled object code, generated documentation,
and conversions to other media types.
"Work" shall mean the work of authorship, whether in Source or
Object form, made available under the License, as indicated by a
copyright notice that is included in or attached to the work
(an example is provided in the Appendix below).
"Derivative Works" shall mean any work, whether in Source or Object
form, that is based on (or derived from) the Work and for which the
editorial revisions, annotations, elaborations, or other modifications
represent, as a whole, an original work of authorship. For the purposes
of this License, Derivative Works shall not include works that remain
separable from, or merely link (or bind by name) to the interfaces of,
the Work and Derivative Works thereof.
"Contribution" shall mean any work of authorship, including
the original version of the Work and any modifications or additions
to that Work or Derivative Works thereof, that is intentionally
submitted to Licensor for inclusion in the Work by the copyright owner
or by an individual or Legal Entity authorized to submit on behalf of
the copyright owner. For the purposes of this definition, "submitted"
means any form of electronic, verbal, or written communication sent
to the Licensor or its representatives, including but not limited to
communication on electronic mailing lists, source code control systems,
and issue tracking systems that are managed by, or on behalf of, the
Licensor for the purpose of discussing and improving the Work, but
excluding communication that is conspicuously marked or otherwise
designated in writing by the copyright owner as "Not a Contribution."
"Contributor" shall mean Licensor and any individual or Legal Entity
on behalf of whom a Contribution has been received by Licensor and
subsequently incorporated within the Work.
2. Grant of Copyright License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
copyright license to reproduce, prepare Derivative Works of,
publicly display, publicly perform, sublicense, and distribute the
Work and such Derivative Works in Source or Object form.
3. Grant of Patent License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
(except as stated in this section) patent license to make, have made,
use, offer to sell, sell, import, and otherwise transfer the Work,
where such license applies only to those patent claims licensable
by such Contributor that are necessarily infringed by their
Contribution(s) alone or by combination of their Contribution(s)
with the Work to which such Contribution(s) was submitted. If You
institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the Work
or a Contribution incorporated within the Work constitutes direct
or contributory patent infringement, then any patent licenses
granted to You under this License for that Work shall terminate
as of the date such litigation is filed.
4. Redistribution. You may reproduce and distribute copies of the
Work or Derivative Works thereof in any medium, with or without
modifications, and in Source or Object form, provided that You
meet the following conditions:
(a) You must give any other recipients of the Work or
Derivative Works a copy of this License; and
(b) You must cause any modified files to carry prominent notices
stating that You changed the files; and
(c) You must retain, in the Source form of any Derivative Works
that You distribute, all copyright, patent, trademark, and
attribution notices from the Source form of the Work,
excluding those notices that do not pertain to any part of
the Derivative Works; and
(d) If the Work includes a "NOTICE" text file as part of its
distribution, then any Derivative Works that You distribute must
include a readable copy of the attribution notices contained
within such NOTICE file, excluding those notices that do not
pertain to any part of the Derivative Works, in at least one
of the following places: within a NOTICE text file distributed
as part of the Derivative Works; within the Source form or
documentation, if provided along with the Derivative Works; or,
within a display generated by the Derivative Works, if and
wherever such third-party notices normally appear. The contents
of the NOTICE file are for informational purposes only and
do not modify the License. You may add Your own attribution
notices within Derivative Works that You distribute, alongside
or as an addendum to the NOTICE text from the Work, provided
that such additional attribution notices cannot be construed
as modifying the License.
You may add Your own copyright statement to Your modifications and
may provide additional or different license terms and conditions
for use, reproduction, or distribution of Your modifications, or
for any such Derivative Works as a whole, provided Your use,
reproduction, and distribution of the Work otherwise complies with
the conditions stated in this License.
5. Submission of Contributions. Unless You explicitly state otherwise,
any Contribution intentionally submitted for inclusion in the Work
by You to the Licensor shall be under the terms and conditions of
this License, without any additional terms or conditions.
Notwithstanding the above, nothing herein shall supersede or modify
the terms of any separate license agreement you may have executed
with Licensor regarding such Contributions.
6. Trademarks. This License does not grant permission to use the trade
names, trademarks, service marks, or product names of the Licensor,
except as required for reasonable and customary use in describing the
origin of the Work and reproducing the content of the NOTICE file.
7. Disclaimer of Warranty. Unless required by applicable law or
agreed to in writing, Licensor provides the Work (and each
Contributor provides its Contributions) on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied, including, without limitation, any warranties or conditions
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
PARTICULAR PURPOSE. You are solely responsible for determining the
appropriateness of using or redistributing the Work and assume any
risks associated with Your exercise of permissions under this License.
8. Limitation of Liability. In no event and under no legal theory,
whether in tort (including negligence), contract, or otherwise,
unless required by applicable law (such as deliberate and grossly
negligent acts) or agreed to in writing, shall any Contributor be
liable to You for damages, including any direct, indirect, special,
incidental, or consequential damages of any character arising as a
result of this License or out of the use or inability to use the
Work (including but not limited to damages for loss of goodwill,
work stoppage, computer failure or malfunction, or any and all
other commercial damages or losses), even if such Contributor
has been advised of the possibility of such damages.
9. Accepting Warranty or Additional Liability. While redistributing
the Work or Derivative Works thereof, You may choose to offer,
and charge a fee for, acceptance of support, warranty, indemnity,
or other liability obligations and/or rights consistent with this
License. However, in accepting such obligations, You may act only
on Your own behalf and on Your sole responsibility, not on behalf
of any other Contributor, and only if You agree to indemnify,
defend, and hold each Contributor harmless for any liability
incurred by, or claims asserted against, such Contributor by reason
of your accepting any such warranty or additional liability.
END OF TERMS AND CONDITIONS
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/cmsis_armcc.h
+894
View File
@@ -0,0 +1,894 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/cmsis_armclang.h
+1444
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/cmsis_armclang_ltm.h
+1891
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/cmsis_compiler.h
+283
View File
@@ -0,0 +1,283 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/cmsis_gcc.h
+2085
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/cmsis_iccarm.h
+935
View File
@@ -0,0 +1,935 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/cmsis_version.h
+39
View File
@@ -0,0 +1,39 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/CMSIS/Include/core_cm3.h
+1937
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Include/apm32f10x.h
+6229
View File
File diff suppressed because it is too large Load Diff
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Include/system_apm32f10x.h
+43
View File
@@ -0,0 +1,43 @@
/*!
* @file system_apm32f10x.h
*
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __SYSTEM_APM32F10X_H
#define __SYSTEM_APM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock;
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_APM32F10X_H */
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s
+368
View File
@@ -0,0 +1,368 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
; *
; * @version V1.0.2
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD TMR8_BRK_IRQHandler ; TMR8 Break
DCD TMR8_UP_IRQHandler ; TMR8 Update
DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_IRQHandler ; TMR6
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD 0 ; Reserved
DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX
DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_IRQHandler [WEAK]
EXPORT TMR1_UP_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBDWakeUp_IRQHandler [WEAK]
EXPORT TMR8_BRK_IRQHandler [WEAK]
EXPORT TMR8_UP_IRQHandler [WEAK]
EXPORT TMR8_TRG_COM_IRQHandler [WEAK]
EXPORT TMR8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT EMMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TMR6_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT USBD2_HP_CAN2_TX_IRQHandler [WEAK]
EXPORT USBD2_LP_CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USBD1_HP_CAN1_TX_IRQHandler
USBD1_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_IRQHandler
TMR1_UP_IRQHandler
TMR1_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTCAlarm_IRQHandler
USBDWakeUp_IRQHandler
TMR8_BRK_IRQHandler
TMR8_UP_IRQHandler
TMR8_TRG_COM_IRQHandler
TMR8_CC_IRQHandler
ADC3_IRQHandler
EMMC_IRQHandler
SDIO_IRQHandler
TMR5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TMR6_IRQHandler
TMR7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
USBD2_HP_CAN2_TX_IRQHandler
USBD2_LP_CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;*******************************END OF FILE************************************
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s
+315
View File
@@ -0,0 +1,315 @@
;/*!
; * @file startup_apm32f10x_md.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md
; *
; * @version V1.0.2
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD FPU_IRQHandler ; FPU
DCD QSPI_IRQHandler ; QSPI
DCD USBD2_HP_IRQHandler ; USBD2 High Priority
DCD USBD2_LP_IRQHandler ; USBD2 Low Priority
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EINT9_5_IRQHandler [WEAK]
EXPORT TMR1_BRK_IRQHandler [WEAK]
EXPORT TMR1_UP_IRQHandler [WEAK]
EXPORT TMR1_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EINT15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBDWakeUp_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT USBD2_HP_IRQHandler [WEAK]
EXPORT USBD2_LP_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USBD1_HP_CAN1_TX_IRQHandler
USBD1_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EINT9_5_IRQHandler
TMR1_BRK_IRQHandler
TMR1_UP_IRQHandler
TMR1_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EINT15_10_IRQHandler
RTCAlarm_IRQHandler
USBDWakeUp_IRQHandler
FPU_IRQHandler
QSPI_IRQHandler
USBD2_HP_IRQHandler
USBD2_LP_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;*******************************END OF FILE************************************
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s
+281
View File
@@ -0,0 +1,281 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
// external interrupts handler
.word WWDT_IRQHandler // Window Watchdog
.word PVD_IRQHandler // PVD through EINT Line detect
.word TAMPER_IRQHandler // Tamper
.word RTC_IRQHandler // RTC
.word FLASH_IRQHandler // Flash
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line 0
.word EINT1_IRQHandler // EINT Line 1
.word EINT2_IRQHandler // EINT Line 2
.word EINT3_IRQHandler // EINT Line 3
.word EINT4_IRQHandler // EINT Line 4
.word DMA1_Channel1_IRQHandler // DMA1 Channel 1
.word DMA1_Channel2_IRQHandler // DMA1 Channel 2
.word DMA1_Channel3_IRQHandler // DMA1 Channel 3
.word DMA1_Channel4_IRQHandler // DMA1 Channel 4
.word DMA1_Channel5_IRQHandler // DMA1 Channel 5
.word DMA1_Channel6_IRQHandler // DMA1 Channel 6
.word DMA1_Channel7_IRQHandler // DMA1 Channel 7
.word ADC1_2_IRQHandler // ADC1 & ADC2
.word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX
.word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // EINT Line 9..5
.word TMR1_BRK_IRQHandler // TMR1 Break
.word TMR1_UP_IRQHandler // TMR1 Update
.word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // EINT Line 15..10
.word RTCAlarm_IRQHandler // RTC Alarm through EINT Line
.word USBDWakeUp_IRQHandler // USBD Wakeup from suspend
.word TMR8_BRK_IRQHandler // TMR8 Break
.word TMR8_UP_IRQHandler // TMR8 Update
.word TMR8_TRG_COM_IRQHandler // TMR8 Trigger and Commutation
.word TMR8_CC_IRQHandler // TMR8 Capture Compare
.word ADC3_IRQHandler // ADC3
.word EMMC_IRQHandler // EMMC
.word SDIO_IRQHandler // SDIO
.word TMR5_IRQHandler // TMR5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TMR6_IRQHandler // TMR6
.word TMR7_IRQHandler // TMR7
.word DMA2_Channel1_IRQHandler // DMA2 Channel1
.word DMA2_Channel2_IRQHandler // DMA2 Channel2
.word DMA2_Channel3_IRQHandler // DMA2 Channel3
.word DMA2_Channel4_5_IRQHandler // DMA2 Channel4 & Channel5
.word 0 // Reserved
.word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX
.word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.size g_pfnVectors, .-g_pfnVectors
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
b .
.size NMI_Handler, . - NMI_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
b .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
b .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
b .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
b .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
b .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
b .
.size SysTick_Handler, . - SysTick_Handler
/* IQR Handler */
.section .text.Default_Handler,"ax",%progbits
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WWDT_IRQHandler
IRQ PVD_IRQHandler
IRQ TAMPER_IRQHandler
IRQ RTC_IRQHandler
IRQ FLASH_IRQHandler
IRQ RCM_IRQHandler
IRQ EINT0_IRQHandler
IRQ EINT1_IRQHandler
IRQ EINT2_IRQHandler
IRQ EINT3_IRQHandler
IRQ EINT4_IRQHandler
IRQ DMA1_Channel1_IRQHandler
IRQ DMA1_Channel2_IRQHandler
IRQ DMA1_Channel3_IRQHandler
IRQ DMA1_Channel4_IRQHandler
IRQ DMA1_Channel5_IRQHandler
IRQ DMA1_Channel6_IRQHandler
IRQ DMA1_Channel7_IRQHandler
IRQ ADC1_2_IRQHandler
IRQ USBD1_HP_CAN1_TX_IRQHandler
IRQ USBD1_LP_CAN1_RX0_IRQHandler
IRQ CAN1_RX1_IRQHandler
IRQ CAN1_SCE_IRQHandler
IRQ EINT9_5_IRQHandler
IRQ TMR1_BRK_IRQHandler
IRQ TMR1_UP_IRQHandler
IRQ TMR1_TRG_COM_IRQHandler
IRQ TMR1_CC_IRQHandler
IRQ TMR2_IRQHandler
IRQ TMR3_IRQHandler
IRQ TMR4_IRQHandler
IRQ I2C1_EV_IRQHandler
IRQ I2C1_ER_IRQHandler
IRQ I2C2_EV_IRQHandler
IRQ I2C2_ER_IRQHandler
IRQ SPI1_IRQHandler
IRQ SPI2_IRQHandler
IRQ USART1_IRQHandler
IRQ USART2_IRQHandler
IRQ USART3_IRQHandler
IRQ EINT15_10_IRQHandler
IRQ RTCAlarm_IRQHandler
IRQ USBDWakeUp_IRQHandler
IRQ TMR8_BRK_IRQHandler
IRQ TMR8_UP_IRQHandler
IRQ TMR8_TRG_COM_IRQHandler
IRQ TMR8_CC_IRQHandler
IRQ ADC3_IRQHandler
IRQ EMMC_IRQHandler
IRQ SDIO_IRQHandler
IRQ TMR5_IRQHandler
IRQ SPI3_IRQHandler
IRQ UART4_IRQHandler
IRQ UART5_IRQHandler
IRQ TMR6_IRQHandler
IRQ TMR7_IRQHandler
IRQ DMA2_Channel1_IRQHandler
IRQ DMA2_Channel2_IRQHandler
IRQ DMA2_Channel3_IRQHandler
IRQ DMA2_Channel4_5_IRQHandler
IRQ USBD2_HP_CAN2_TX_IRQHandler
IRQ USBD2_LP_CAN2_RX0_IRQHandler
IRQ CAN2_RX1_IRQHandler
IRQ CAN2_SCE_IRQHandler
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s
+246
View File
@@ -0,0 +1,246 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
// external interrupts handler
.word WWDT_IRQHandler // Window Watchdog
.word PVD_IRQHandler // PVD through EINT Line detect
.word TAMPER_IRQHandler // Tamper
.word RTC_IRQHandler // RTC
.word FLASH_IRQHandler // Flash
.word RCM_IRQHandler // RCM
.word EINT0_IRQHandler // EINT Line 0
.word EINT1_IRQHandler // EINT Line 1
.word EINT2_IRQHandler // EINT Line 2
.word EINT3_IRQHandler // EINT Line 3
.word EINT4_IRQHandler // EINT Line 4
.word DMA1_Channel1_IRQHandler // DMA1 Channel 1
.word DMA1_Channel2_IRQHandler // DMA1 Channel 2
.word DMA1_Channel3_IRQHandler // DMA1 Channel 3
.word DMA1_Channel4_IRQHandler // DMA1 Channel 4
.word DMA1_Channel5_IRQHandler // DMA1 Channel 5
.word DMA1_Channel6_IRQHandler // DMA1 Channel 6
.word DMA1_Channel7_IRQHandler // DMA1 Channel 7
.word ADC1_2_IRQHandler // ADC1_2
.word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX
.word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0
.word CAN1_RX1_IRQHandler // CAN1 RX1
.word CAN1_SCE_IRQHandler // CAN1 SCE
.word EINT9_5_IRQHandler // EINT Line 9..5
.word TMR1_BRK_IRQHandler // TMR1 Break
.word TMR1_UP_IRQHandler // TMR1 Update
.word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation
.word TMR1_CC_IRQHandler // TMR1 Capture Compare
.word TMR2_IRQHandler // TMR2
.word TMR3_IRQHandler // TMR3
.word TMR4_IRQHandler // TMR4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EINT15_10_IRQHandler // EINT Line 15..10
.word RTCAlarm_IRQHandler // RTC Alarm through EINT Line
.word USBDWakeUp_IRQHandler // USBD Wakeup from suspend
.word FPU_IRQHandler // FPU
.word QSPI_IRQHandler // QSPI
.word USBD2_HP_IRQHandler // USBD2 High Priority
.word USBD2_LP_IRQHandler // USBD2 Low Priority
.size g_pfnVectors, .-g_pfnVectors
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
b .
.size NMI_Handler, . - NMI_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
b .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
b .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
b .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
b .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
b .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
b .
.size SysTick_Handler, . - SysTick_Handler
/* IQR Handler */
.section .text.Default_Handler,"ax",%progbits
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WWDT_IRQHandler
IRQ PVD_IRQHandler
IRQ TAMPER_IRQHandler
IRQ RTC_IRQHandler
IRQ FLASH_IRQHandler
IRQ RCM_IRQHandler
IRQ EINT0_IRQHandler
IRQ EINT1_IRQHandler
IRQ EINT2_IRQHandler
IRQ EINT3_IRQHandler
IRQ EINT4_IRQHandler
IRQ DMA1_Channel1_IRQHandler
IRQ DMA1_Channel2_IRQHandler
IRQ DMA1_Channel3_IRQHandler
IRQ DMA1_Channel4_IRQHandler
IRQ DMA1_Channel5_IRQHandler
IRQ DMA1_Channel6_IRQHandler
IRQ DMA1_Channel7_IRQHandler
IRQ ADC1_2_IRQHandler
IRQ USBD1_HP_CAN1_TX_IRQHandler
IRQ USBD1_LP_CAN1_RX0_IRQHandler
IRQ CAN1_RX1_IRQHandler
IRQ CAN1_SCE_IRQHandler
IRQ EINT9_5_IRQHandler
IRQ TMR1_BRK_IRQHandler
IRQ TMR1_UP_IRQHandler
IRQ TMR1_TRG_COM_IRQHandler
IRQ TMR1_CC_IRQHandler
IRQ TMR2_IRQHandler
IRQ TMR3_IRQHandler
IRQ TMR4_IRQHandler
IRQ I2C1_EV_IRQHandler
IRQ I2C1_ER_IRQHandler
IRQ I2C2_EV_IRQHandler
IRQ I2C2_ER_IRQHandler
IRQ SPI1_IRQHandler
IRQ SPI2_IRQHandler
IRQ USART1_IRQHandler
IRQ USART2_IRQHandler
IRQ USART3_IRQHandler
IRQ EINT15_10_IRQHandler
IRQ RTCAlarm_IRQHandler
IRQ USBDWakeUp_IRQHandler
IRQ FPU_IRQHandler
IRQ QSPI_IRQHandler
IRQ USBD2_HP_IRQHandler
IRQ USBD2_LP_IRQHandler
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s
+504
View File
@@ -0,0 +1,504 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD TMR8_BRK_IRQHandler ; TMR8 Break
DCD TMR8_UP_IRQHandler ; TMR8 Update
DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation
DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD EMMC_IRQHandler ; EMMC
DCD SDIO_IRQHandler ; SDIO
DCD TMR5_IRQHandler ; TMR5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TMR6_IRQHandler ; TMR6
DCD TMR7_IRQHandler ; TMR7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD 0 ; Reserved
DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX
DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_HP_CAN1_TX_IRQHandler
B USBD1_HP_CAN1_TX_IRQHandler
PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_LP_CAN1_RX0_IRQHandler
B USBD1_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_IRQHandler
B TMR1_BRK_IRQHandler
PUBWEAK TMR1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_IRQHandler
B TMR1_UP_IRQHandler
PUBWEAK TMR1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_IRQHandler
B TMR1_TRG_COM_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBDWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBDWakeUp_IRQHandler
B USBDWakeUp_IRQHandler
PUBWEAK TMR8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_BRK_IRQHandler
B TMR8_BRK_IRQHandler
PUBWEAK TMR8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_UP_IRQHandler
B TMR8_UP_IRQHandler
PUBWEAK TMR8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_TRG_COM_IRQHandler
B TMR8_TRG_COM_IRQHandler
PUBWEAK TMR8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR8_CC_IRQHandler
B TMR8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK EMMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EMMC_IRQHandler
B EMMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TMR5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR5_IRQHandler
B TMR5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TMR6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR6_IRQHandler
B TMR6_IRQHandler
PUBWEAK TMR7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR7_IRQHandler
B TMR7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
PUBWEAK USBD2_HP_CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_HP_CAN2_TX_IRQHandler
B USBD2_HP_CAN2_TX_IRQHandler
PUBWEAK USBD2_LP_CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_LP_CAN2_RX0_IRQHandler
B USBD2_LP_CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
END
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s
+404
View File
@@ -0,0 +1,404 @@
;/*!
; * @file startup_apm32f10x_hd.s
; *
; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103
; *
; * @version V1.0.0
; *
; * @date 2022-01-05
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be usefull and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCM_IRQHandler ; RCM
DCD EINT0_IRQHandler ; EINT Line 0
DCD EINT1_IRQHandler ; EINT Line 1
DCD EINT2_IRQHandler ; EINT Line 2
DCD EINT3_IRQHandler ; EINT Line 3
DCD EINT4_IRQHandler ; EINT Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX
DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EINT9_5_IRQHandler ; EINT Line 9..5
DCD TMR1_BRK_IRQHandler ; TMR1 Break
DCD TMR1_UP_IRQHandler ; TMR1 Update
DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR4_IRQHandler ; TMR4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EINT15_10_IRQHandler ; EINT Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line
DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend
DCD FPU_IRQHandler ; FPU
DCD QSPI_IRQHandler ; QSPI
DCD USBD2_HP_IRQHandler ; USBD2 High Priority
DCD USBD2_LP_IRQHandler ; USBD2 Low Priority
__Vectors_End
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCM_IRQHandler
B RCM_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT4_IRQHandler
B EINT4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_HP_CAN1_TX_IRQHandler
B USBD1_HP_CAN1_TX_IRQHandler
PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD1_LP_CAN1_RX0_IRQHandler
B USBD1_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EINT9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT9_5_IRQHandler
B EINT9_5_IRQHandler
PUBWEAK TMR1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_IRQHandler
B TMR1_BRK_IRQHandler
PUBWEAK TMR1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_UP_IRQHandler
B TMR1_UP_IRQHandler
PUBWEAK TMR1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_TRG_COM_IRQHandler
B TMR1_TRG_COM_IRQHandler
PUBWEAK TMR1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CC_IRQHandler
B TMR1_CC_IRQHandler
PUBWEAK TMR2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_IRQHandler
B TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR4_IRQHandler
B TMR4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EINT15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EINT15_10_IRQHandler
B EINT15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBDWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBDWakeUp_IRQHandler
B USBDWakeUp_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK QSPI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
QSPI_IRQHandler
B QSPI_IRQHandler
PUBWEAK USBD2_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_HP_IRQHandler
B USBD2_HP_IRQHandler
PUBWEAK USBD2_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBD2_LP_IRQHandler
B USBD2_LP_IRQHandler
END
Example/EpaperModuleTest_APM32F103/APM32F103/Device/Geehy/APM32F10x/Source/system_apm32f10x.c
+566
View File
@@ -0,0 +1,566 @@
/*!
* @file system_apm32f10x.c
*
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
*
* @version V1.0.2
*
* @date 2022-01-05
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f10x.h"
/*****************************************************************
* If SYSCLK source is PLL,SystemCoreClock will contain the *
* HSE_VALUE or HSI_VALUE multiplied/divided by the PLL factors. *
******************************************************************/
//#define SYSTEM_CLOCK_HSE HSE_VALUE
//#define SYSTEM_CLOCK_24MHz (24000000)
//#define SYSTEM_CLOCK_36MHz (36000000)
//#define SYSTEM_CLOCK_48MHz (48000000)
//#define SYSTEM_CLOCK_56MHz (56000000)
//#define SYSTEM_CLOCK_72MHz (72000000)
#define SYSTEM_CLOCK_96MHz (96000000)
/** #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00
#ifdef SYSTEM_CLOCK_HSE
uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE;
#elif defined SYSTEM_CLOCK_24MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz;
#elif defined SYSTEM_CLOCK_36MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz;
#elif defined SYSTEM_CLOCK_48MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz;
#elif defined SYSTEM_CLOCK_56MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz;
#elif defined SYSTEM_CLOCK_72MHz
uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz;
#else
uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz;
#endif
static void SystemClockConfig(void);
#ifdef SYSTEM_CLOCK_HSE
static void SystemClockHSE(void);
#elif defined SYSTEM_CLOCK_24MHz
static void SystemClock24M(void);
#elif defined SYSTEM_CLOCK_36MHz
static void SystemClock36M(void);
#elif defined SYSTEM_CLOCK_48MHz
static void SystemClock48M(void);
#elif defined SYSTEM_CLOCK_56MHz
static void SystemClock56M(void);
#elif defined SYSTEM_CLOCK_72MHz
static void SystemClock72M(void);
#elif defined SYSTEM_CLOCK_96MHz
static void SystemClock96M(void);
#endif
/*!
* @brief Setup the microcontroller system
*
* @param None
*
* @retval None
*
*/
void SystemInit (void)
{
/** Set HSIEN bit */
RCM->CTRL_B.HSIEN = BIT_SET;
/** Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
RCM->CFG &= (uint32_t)0xF8FF0000;
/** Reset HSEEN, CSSEN and PLLEN bits */
RCM->CTRL &= (uint32_t)0xFEF6FFFF;
/** Reset HSEBCFG bit */
RCM->CTRL_B.HSEBCFG = BIT_RESET;
/** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
RCM->CFG &= (uint32_t)0xFF80FFFF;
/** Disable all interrupts and clear pending bits */
RCM->INT = 0x009F0000;
SystemClockConfig();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else
SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET;
#endif
}
/*!
* @brief Update SystemCoreClock variable according to Clock Register Values
* The SystemCoreClock variable contains the core clock (HCLK)
*
* @param None
*
* @retval None
*
*/
void SystemCoreClockUpdate (void)
{
uint32_t sysClock, pllMull, pllSource, Prescaler;
uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
sysClock = RCM->CFG_B.SCLKSELSTS;
switch(sysClock)
{
/** sys clock is HSI */
case 0:
SystemCoreClock = HSI_VALUE;
break;
/** sys clock is HSE */
case 1:
SystemCoreClock = HSE_VALUE;
break;
/** sys clock is PLL */
case 2:
pllMull = RCM->CFG_B.PLLMULCFG + 2;
pllSource = RCM->CFG_B.PLLSRCSEL;
/** PLL entry clock source is HSE */
if(pllSource == BIT_SET)
{
SystemCoreClock = HSE_VALUE * pllMull;
/** HSE clock divided by 2 */
if(pllSource == RCM->CFG_B.PLLHSEPSC)
{
SystemCoreClock >>= 1;
}
}
/** PLL entry clock source is HSI/2 */
else
{
SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
}
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
Prescaler = AHBPrescTable[RCM->CFG_B.AHBPSC];
SystemCoreClock >>= Prescaler;
}
/*!
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClockConfig(void)
{
#ifdef SYSTEM_CLOCK_HSE
SystemClockHSE();
#elif defined SYSTEM_CLOCK_24MHz
SystemClock24M();
#elif defined SYSTEM_CLOCK_36MHz
SystemClock36M();
#elif defined SYSTEM_CLOCK_48MHz
SystemClock48M();
#elif defined SYSTEM_CLOCK_56MHz
SystemClock56M();
#elif defined SYSTEM_CLOCK_72MHz
SystemClock72M();
#elif defined SYSTEM_CLOCK_96MHz
SystemClock96M();
#endif
}
#if defined SYSTEM_CLOCK_HSE
/*!
* @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClockHSE(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 0 wait state */
FMC->CTRL1_B.WS = 0;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK */
RCM->CFG_B.APB1PSC = 0;
/** Select HSE as system clock source */
RCM->CFG_B.SCLKSEL = 1;
/** Wait till HSE is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x01);
}
}
#elif defined SYSTEM_CLOCK_24MHz
/*!
* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock24M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 0 wait state */
FMC->CTRL1_B.WS = 0;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK */
RCM->CFG_B.APB1PSC = 0;
/** PLL: (HSE / 2) * 6 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLHSEPSC = 1;
RCM->CFG_B.PLLMULCFG = 4;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_36MHz
/*!
* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock36M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 1 wait state */
FMC->CTRL1_B.WS = 1;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK */
RCM->CFG_B.APB1PSC = 0;
/** PLL: (HSE / 2) * 9 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLHSEPSC = 1;
RCM->CFG_B.PLLMULCFG = 7;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS != 0x02);
}
}
#elif defined SYSTEM_CLOCK_48MHz
/*!
* @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock48M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 1 wait state */
FMC->CTRL1_B.WS = 1;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 6 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 4;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_56MHz
/*!
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock56M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 2 wait state */
FMC->CTRL1_B.WS = 2;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 7 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 5;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_72MHz
/*!
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock72M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 2 wait state */
FMC->CTRL1_B.WS = 2;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 9 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 7;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#elif defined SYSTEM_CLOCK_96MHz
/*!
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers
*
* @param None
*
* @retval None
*
*/
static void SystemClock96M(void)
{
__IO uint32_t i;
RCM->CTRL_B.HSEEN= BIT_SET;
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
{
if(RCM->CTRL_B.HSERDYFLG)
{
break;
}
}
if(RCM->CTRL_B.HSERDYFLG)
{
/** Enable Prefetch Buffer */
FMC->CTRL1_B.PBEN = BIT_SET;
/** Flash 3 wait state */
FMC->CTRL1_B.WS = 3;
/** HCLK = SYSCLK */
RCM->CFG_B.AHBPSC= 0X00;
/** PCLK2 = HCLK */
RCM->CFG_B.APB2PSC= 0;
/** PCLK1 = HCLK / 2 */
RCM->CFG_B.APB1PSC = 4;
/** PLL: HSE * 12 */
RCM->CFG_B.PLLSRCSEL = 1;
RCM->CFG_B.PLLMULCFG = 10;
/** Enable PLL */
RCM->CTRL_B.PLLEN = 1;
/** Wait PLL Ready */
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
/** Select PLL as system clock source */
RCM->CFG_B.SCLKSEL = 2;
/** Wait till PLL is used as system clock source */
while(RCM->CFG_B.SCLKSELSTS!= 0x02);
}
}
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h
+33
View File
@@ -0,0 +1,33 @@
/*!
* @file usbd_class_cdc.h
*
* @brief CDC Class handler file head file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __CDC_CLASS_
#define __CDC_CLASS_
#include "usbd_core.h"
void USBD_ClassHandler(USBD_DevReqData_T* reqData);
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c
+71
View File
@@ -0,0 +1,71 @@
/*!
* @file usbd_class_cdc.c
*
* @brief CDC Class handler file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_class_cdc.h"
static uint8_t cmdBuf[8] = {0};
/*!
* @brief USB CDC Class request handler
*
* @param reqData : point to USBD_DevReqData_T structure
*
* @retval None
*/
void USBD_ClassHandler(USBD_DevReqData_T* reqData)
{
uint16_t length = ((uint16_t)reqData->byte.wLength[1] << 8) | \
reqData->byte.wLength[0] ;
if (!length)
{
if (!reqData->byte.bmRequestType.bit.dir)
{
USBD_CtrlTxStatus();
}
else
{
USBD_CtrlRxStatus();
}
}
else
{
switch (reqData->byte.bRequest)
{
case 0x20:
USBD_CtrlOutData(cmdBuf, length);
break;
case 0x21:
USBD_CtrlInData(cmdBuf, length);
break;
case 0x22:
USBD_CtrlOutData(cmdBuf, length);
break;
default:
break;
}
}
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h
+37
View File
@@ -0,0 +1,37 @@
/*!
* @file usbd_class_hid.h
*
* @brief HID Class handler file head file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_core.h"
#define HID_CLASS_REQ_SET_PROTOCOL 0x0B
#define HID_CLASS_REQ_GET_PROTOCOL 0x03
#define HID_CLASS_REQ_SET_IDLE 0x0A
#define HID_CLASS_REQ_GET_IDLE 0x02
#define HID_CLASS_REQ_SET_REPORT 0x09
#define HID_CLASS_REQ_GET_REPORT 0x01
void USBD_ClassHandler(USBD_DevReqData_T* reqData);
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c
+63
View File
@@ -0,0 +1,63 @@
/*!
* @file usbd_class_hid.c
*
* @brief HID Class handler file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_class_hid.h"
static uint8_t s_hidIdleState;
static uint8_t s_hidProtocol;
/*!
* @brief USB HID Class request handler
*
* @param reqData : point to USBD_DevReqData_T structure
*
* @retval None
*/
void USBD_ClassHandler(USBD_DevReqData_T* reqData)
{
switch (reqData->byte.bRequest)
{
case HID_CLASS_REQ_SET_IDLE:
s_hidIdleState = reqData->byte.wValue[1];
USBD_CtrlInData(NULL, 0);
break;
case HID_CLASS_REQ_GET_IDLE:
USBD_CtrlInData(&s_hidIdleState, 1);
break;
case HID_CLASS_REQ_SET_PROTOCOL:
s_hidProtocol = reqData->byte.wValue[0];
USBD_CtrlInData(NULL, 0);
break;
case HID_CLASS_REQ_GET_PROTOCOL:
USBD_CtrlInData(&s_hidProtocol, 1);
break;
default:
break;
}
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h
+37
View File
@@ -0,0 +1,37 @@
/*!
* @file usbd_class_msc.h
*
* @brief MSC Class handler file head file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __USBD_CLASS_MSC
#define __USBD_CLASS_MSC
#include "usbd_core.h"
#define BOT_GET_MAX_LUN 0xFE
#define BOT_RESET 0xFF
void USBD_MSC_ClassHandler(USBD_DevReqData_T* reqData);
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h
+106
View File
@@ -0,0 +1,106 @@
/*!
* @file usbd_msc_bot.h
*
* @brief MSC BOT protocol core functions
*
* @version V1.0.0
*
* @date 2021-12-25
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_core.h"
#ifndef __USBD_MSC_BOT_H
#define __USBD_MSC_BOT_H
#define MSC_BOT_CBW_SIGNATURE (uint32_t)(0x43425355)
#define MSC_BOT_CBW_LENGTH 31
#define MSC_BOT_CSW_SIGNATURE (uint32_t)(0x53425355)
#define MSC_BOT_CSW_LENGTH 13
typedef enum
{
BOT_STATE_IDLE, //!< Idle state
BOT_STATE_DATA_OUT, //!< Data Out state
BOT_STATE_DATA_IN, //!< Data In state
BOT_STATE_LAST_DATA_IN, //!< Last Data In Last
BOT_STATE_SEND_DATA //!< Send Immediate data
} BOT_STATE_T;
typedef enum
{
BOT_STATUS_NORMAL,
BOT_STATUS_RECOVERY,
BOT_STATUS_ERROR
} BOT_STATUS_T;
typedef enum
{
BOT_CSW_STATUS_CMD_OK,
BOT_CSW_STATUS_CMD_FAIL,
BOT_CSW_STATUS_PHASE_ERROR
} BOT_CSW_STATUS_T;
/**
* @brief Command Block Wrapper
*/
typedef struct
{
uint32_t dSignature;
uint32_t dTag;
uint32_t dDataXferLen;
uint8_t bmFlags;
uint8_t bLUN;
uint8_t bCBLen;
uint8_t CB[16];
} BOT_CBW_T;
/**
* @brief Command Status Wrapper
*/
typedef struct
{
uint32_t dSignature;
uint32_t dTag;
uint32_t dDataResidue;
uint8_t bStatus;
} BOT_CSW_T;
typedef struct
{
uint8_t state;
uint8_t status;
uint16_t dataLen;
BOT_CBW_T CBW;
BOT_CSW_T CSW;
uint8_t data[MSC_MEDIA_PACKET];
} BOT_Info_T;
extern BOT_Info_T g_BOTInfo;
void USBD_MSC_BOT_Reset(void);
void USBD_MSC_BOT_Init(void);
void USBD_MSC_BOT_OutData(uint8_t ep);
void USBD_MSC_BOT_InData(uint8_t ep);
void USBD_MSC_BOT_TxCSW(uint8_t cswStatus);
void USBD_MSC_BOT_Stall(void);
void USBD_MSV_BOT_ClearFeatureHandler(void);
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h
+131
View File
@@ -0,0 +1,131 @@
/*!
* @file usbd_msc_scsi.h
*
* @brief MSC scsi
*
* @version V1.0.0
*
* @date 2021-12-25
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_core.h"
#ifndef __USBD_MSC_SCSI_H_
#define __USBD_MSC_SCSI_H_
/**
* @brief SCSI function status
*/
enum
{
SCSI_OK,
SCSI_FAIL
};
/**
* @brief SCSI Sense Key
*/
typedef enum
{
SCSI_SKEY_NO_SENSE,
SCSI_SKEY_RECOVERED_ERROR,
SCSI_SKEY_NOT_READY,
SCSI_SKEY_MEDIUM_ERROR,
SCSI_SKEY_HARDWARE_ERROR,
SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_SKEY_UNIT_ATTENTION,
SCSI_SKEY_DATA_PROTECT,
SCSI_SKEY_BLANK_CHECK,
SCSI_SKEY_VENDOR_SPECIFIC,
SCSI_SKEY_COPY_ABORTED,
SCSI_SKEY_ABORTED_COMMAND,
SCSI_SKEY_VOLUME_OVERFLOW = 13,
SCSI_SKEY_MISCOMPARE = 14
} SCSI_SKEY_T;
/**
* @brief SCSI Sense
*/
typedef struct {
uint8_t sensekey;
uint8_t ASC;
uint8_t ASCQ;
} SCSI_Sense_T;
#define SCSI_SENSE_LIST_NUMBER 4
#define SCSI_INQUIRY_LENGTH 36
/** SCSI Commands */
#define SCSI_CMD_FORMAT_UNIT ((uint8_t)0x04)
#define SCSI_CMD_INQUIRY ((uint8_t)0x12)
#define SCSI_CMD_MODE_SELECT_6 ((uint8_t)0x15)
#define SCSI_CMD_MODE_SELECT_10 ((uint8_t)0x55)
#define SCSI_CMD_MODE_SENSE_6 ((uint8_t)0x1A)
#define SCSI_CMD_MODE_SENSE_10 ((uint8_t)0x5A)
#define SCSI_CMD_ALLOW_MEDIUM_REMOVAL ((uint8_t)0x1E)
#define SCSI_CMD_READ_6 ((uint8_t)0x08)
#define SCSI_CMD_READ_10 ((uint8_t)0x28)
#define SCSI_CMD_READ_12 ((uint8_t)0xA8)
#define SCSI_CMD_READ_16 ((uint8_t)0x88)
#define SCSI_CMD_READ_CAPACITY_10 ((uint8_t)0x25)
#define SCSI_CMD_READ_CAPACITY_16 ((uint8_t)0x9E)
#define SCSI_CMD_REQUEST_SENSE ((uint8_t)0x03)
#define SCSI_CMD_START_STOP_UNIT ((uint8_t)0x1B)
#define SCSI_CMD_TEST_UNIT_READY ((uint8_t)0x00)
#define SCSI_CMD_WRITE6 ((uint8_t)0x0A)
#define SCSI_CMD_WRITE10 ((uint8_t)0x2A)
#define SCSI_CMD_WRITE12 ((uint8_t)0xAA)
#define SCSI_CMD_WRITE16 ((uint8_t)0x8A)
#define SCSI_CMD_VERIFY_10 ((uint8_t)0x2F)
#define SCSI_CMD_VERIFY_12 ((uint8_t)0xAF)
#define SCSI_CMD_VERIFY_16 ((uint8_t)0x8F)
#define SCSI_CMD_SEND_DIAGNOSTIC ((uint8_t)0x1D)
#define SCSI_CMD_READ_FORMAT_CAPACITIES ((uint8_t)0x23)
#define SCSI_ASC_INVALID_CDB 0x20
#define SCSI_ASC_INVALID_FIELED_IN_COMMAND 0x24
#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR 0x1A
#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST 0x26
#define SCSI_ASC_ADDRESS_OUT_OF_RANGE 0x21
#define SCSI_ASC_MEDIUM_NOT_PRESENT 0x3A
#define SCSI_ASC_MEDIUM_HAVE_CHANGED 0x28
#define SCSI_ASC_WRITE_PROTECTED 0x27
#define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
#define SCSI_ASC_WRITE_FAULT 0x03
#define SCSI_READ_FORMAT_CAPACITY_DATA_LEN 0x0C
#define SCSI_READ_CAPACITY10_DATA_LEN 0x08
#define SCSI_MODE_SENSE10_DATA_LEN 0x08
#define SCSI_MODE_SENSE6_DATA_LEN 0x04
#define SCSI_REQUEST_SENSE_DATA_LEN 0x12
#define SCSI_STANDARD_INQUIRY_DATA_LEN 0x24
#define SCSI_BLKVFY 0x04
extern SCSI_Sense_T g_scsiSense[SCSI_SENSE_LIST_NUMBER];
extern uint8_t g_senseTxCnt;
extern uint8_t g_sensePutCnt;
uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *cmd);
void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ);
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c
+79
View File
@@ -0,0 +1,79 @@
/*!
* @file usbd_class_msc.c
*
* @brief MSC Class file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_class_msc.h"
#include "usbd_msc_bot.h"
static uint8_t s_mscMaxLen = 0;
/*!
* @brief USB MSC Class request handler
*
* @param reqData : point to USBD_DevReqData_T structure
*
* @retval None
*/
void USBD_MSC_ClassHandler(USBD_DevReqData_T* reqData)
{
uint16_t wValue = ((uint16_t)reqData->byte.wValue[1] << 8) | \
reqData->byte.wValue[0];
uint16_t wLength = ((uint16_t)reqData->byte.wLength[1] << 8) | \
reqData->byte.wLength[0];
switch (reqData->byte.bRequest)
{
case BOT_GET_MAX_LUN :
if ((wValue == 0) && (wLength == 1) && \
(reqData->byte.bmRequestType.bit.dir == 1))
{
s_mscMaxLen = STORAGE_MAX_LUN - 1;
USBD_CtrlInData(&s_mscMaxLen, 1);
}
else
{
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
}
break;
case BOT_RESET :
if ((wValue == 0) && (wLength == 0) && \
(reqData->byte.bmRequestType.bit.dir == 0))
{
USBD_CtrlInData(NULL, 0);
/** Reset */
USBD_MSC_BOT_Reset();
}
else
{
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
}
break;
default:
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
break;
}
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c
+242
View File
@@ -0,0 +1,242 @@
/*!
* @file usbd_msv_bot.c
*
* @brief MSC BOT protocol core functions
*
* @version V1.0.0
*
* @date 2021-12-25
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_msc_bot.h"
#include "usbd_core.h"
#include "usbd_storage_disk.h"
#include "usbd_msc_scsi.h"
BOT_Info_T g_BOTInfo;
static void USBD_MSC_BOT_DecodeCBW(void);
static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len);
static void USBD_MSC_BOT_Stall(void);
/*!
* @brief BOT Process Reset.
*
* @param None
*
* @retval None
*/
void USBD_MSC_BOT_Reset(void)
{
g_BOTInfo.state = BOT_STATE_IDLE;
g_BOTInfo.status = BOT_STATUS_RECOVERY;
USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
}
/*!
* @brief BOT Process initialization.
*
* @param None
*
* @retval None
*/
void USBD_MSC_BOT_Init(void)
{
g_BOTInfo.state = BOT_STATE_IDLE;
g_BOTInfo.status = BOT_STATUS_NORMAL;
g_storageCallBack.Init(0);
USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
}
/*!
* @brief Bulk OUT data handler.
*
* @param ep : OUT endpoint
*
* @retval None
*/
void USBD_MSC_BOT_OutData(uint8_t ep)
{
if (g_BOTInfo.state == BOT_STATE_IDLE)
{
USBD_MSC_BOT_DecodeCBW();
}
else if (g_BOTInfo.state == BOT_STATE_DATA_OUT)
{
if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
{
USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
}
}
}
/*!
* @brief Bulk IN data handler.
*
* @param ep : IN endpoint
*
* @retval None
*/
void USBD_MSC_BOT_InData(uint8_t ep)
{
if (g_BOTInfo.state == BOT_STATE_DATA_IN)
{
if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
{
USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
}
}
else if ((g_BOTInfo.state == BOT_STATE_SEND_DATA) || \
(g_BOTInfo.state == BOT_STATE_LAST_DATA_IN))
{
USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
}
}
/*!
* @brief Decode CBW.
*
* @param None
*
* @retval None
*/
static void USBD_MSC_BOT_DecodeCBW(void)
{
uint32_t xferCnt = g_usbDev.outBuf[MSC_OUT_EP & 0x7f].xferCnt;
g_BOTInfo.CSW.dTag = g_BOTInfo.CBW.dTag;
g_BOTInfo.CSW.dDataResidue = g_BOTInfo.CBW.dDataXferLen;
if ((xferCnt != MSC_BOT_CBW_LENGTH) || \
(g_BOTInfo.CBW.dSignature != MSC_BOT_CBW_SIGNATURE) || \
(g_BOTInfo.CBW.bLUN > 1) || (g_BOTInfo.CBW.bCBLen < 1) || \
(g_BOTInfo.CBW.bCBLen > 16))
{
SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_CDB, 0);
g_BOTInfo.status = BOT_STATUS_ERROR;
}
else
{
if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
{
USBD_MSC_BOT_Stall();
}
else if ((g_BOTInfo.state == BOT_STATE_IDLE) || \
(g_BOTInfo.state == BOT_STATE_SEND_DATA))
{
if (g_BOTInfo.dataLen)
{
USBD_MSC_BOT_TxData(g_BOTInfo.data, g_BOTInfo.dataLen);
}
else
{
USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
}
}
}
}
/*!
* @brief MSC send data.
*
* @param txBuf : buffer to send
*
* @param len : buffer length
*
* @retval None
*/
static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len)
{
len = USB_MIN(len, g_BOTInfo.CBW.dDataXferLen);
g_BOTInfo.CSW.dDataResidue -= len;
g_BOTInfo.CSW.bStatus = BOT_CSW_STATUS_CMD_OK;
g_BOTInfo.state = BOT_STATE_SEND_DATA;
USBD_TxData(MSC_IN_EP & 0x7f, txBuf, len);
}
/*!
* @brief Send CSW.
*
* @param cswStatus : status of CSW
*
* @retval None
*/
void USBD_MSC_BOT_TxCSW(uint8_t cswStatus)
{
g_BOTInfo.CSW.dSignature = MSC_BOT_CSW_SIGNATURE;
g_BOTInfo.CSW.bStatus = cswStatus;
g_BOTInfo.state = BOT_STATE_IDLE;
USBD_TxData(MSC_IN_EP & 0x7f, (uint8_t*)&g_BOTInfo.CSW,
MSC_BOT_CSW_LENGTH);
USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t*)&g_BOTInfo.CBW,
MSC_BOT_CBW_LENGTH);
}
/*!
* @brief handler clearFeature in standard request.
*
* @param None
*
* @retval None
*/
void USBD_MSV_BOT_ClearFeatureHandler(void)
{
if (g_BOTInfo.status == BOT_STATUS_ERROR)
{
USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_NAK);
g_BOTInfo.status = BOT_STATUS_NORMAL;
}
else if (((g_usbDev.reqData.byte.wIndex[0] & 0x80) == 0x80) && \
g_BOTInfo.status != BOT_STATUS_RECOVERY)
{
USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
}
}
/*!
* @brief Stall MSC.
*
* @param None
*
* @retval None
*/
static void USBD_MSC_BOT_Stall(void)
{
if ((g_BOTInfo.CBW.bmFlags == 0) && (g_BOTInfo.CBW.dDataXferLen != 0) && \
(g_BOTInfo.status == BOT_STATUS_NORMAL))
{
USBD_SetEPRxStatus(MSC_OUT_EP & 0x7f, USBD_EP_STATUS_STALL);
}
USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_STALL);
if (g_BOTInfo.status == BOT_STATUS_ERROR)
{
USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
MSC_BOT_CBW_LENGTH);
}
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c
+701
View File
@@ -0,0 +1,701 @@
/*!
* @file usbd_msc_scsi.c
*
* @brief MSC scsi
*
* @version V1.0.0
*
* @date 2021-12-25
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_msc_bot.h"
#include "usbd_msc_scsi.h"
#include "usbd_storage_disk.h"
SCSI_Sense_T g_scsiSenseCode[SCSI_SENSE_LIST_NUMBER];
uint8_t g_senseTxCnt;
uint8_t g_sensePutCnt;
static uint32_t s_blkSize;
static uint32_t s_blkNbr;
static uint32_t s_blkAddr;
static uint32_t s_blkLen;
/** USB Mass storage Page 0 Inquiry Data */
static const uint8_t s_page00InquiryData[] =
{
0x00,
0x00,
0x00,
(7 - 4),
0x00,
0x80,
0x83
};
/** USB Mass storage sense 6 Data */
static const uint8_t s_modeSense6Data[] =
{
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
/** USB Mass storage sense 10 Data */
static const uint8_t s_modeSense10Data[] =
{
0x00,
0x06,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
static uint8_t SCSI_TestUnitReady(uint8_t lun);
static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t* command);
static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t* command);
static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t* command);
static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t* command);
static uint8_t SCSI_Read10(uint8_t lun, uint8_t* command);
static uint8_t SCSI_Write10(uint8_t lun, uint8_t* command);
static uint8_t SCSI_Verify10(uint8_t lun, uint8_t* command);
static uint8_t SCSI_StartStopUnit(void);
static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t* command);
static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t* command);
static uint8_t SCSI_Read(uint8_t lun);
static uint8_t SCSI_Write(uint8_t lun);
static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr);
/*!
* @brief SCSI command handler.
*
* @param lun: Logical unit number
*
* @param command: Command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t* command)
{
uint8_t ret = SCSI_OK;
switch (command[0])
{
case SCSI_CMD_TEST_UNIT_READY:
ret = SCSI_TestUnitReady(lun);
break;
case SCSI_CMD_INQUIRY:
ret = SCSI_Inquiry(lun, command);
break;
case SCSI_CMD_REQUEST_SENSE:
ret = SCSI_RequestSense(lun, command);
break;
case SCSI_CMD_READ_FORMAT_CAPACITIES:
ret = SCSI_ReadFormatCapacity(lun, command);
break;
case SCSI_CMD_READ_CAPACITY_10:
ret = SCSI_ReadCapacity10(lun, command);
break;
case SCSI_CMD_READ_10:
ret = SCSI_Read10(lun, command);
break;
case SCSI_CMD_WRITE10:
ret = SCSI_Write10(lun, command);
break;
case SCSI_CMD_VERIFY_10:
ret = SCSI_Verify10(lun, command);
break;
case SCSI_CMD_ALLOW_MEDIUM_REMOVAL:
case SCSI_CMD_START_STOP_UNIT:
ret = SCSI_StartStopUnit();
break;
case SCSI_CMD_MODE_SENSE_6:
ret = SCSI_ModeSense6 (lun, command);
break;
case SCSI_CMD_MODE_SENSE_10:
ret = SCSI_ModeSense10 (lun, command);
break;
default:
SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_CDB, 0);
ret = SCSI_FAIL;
}
return ret;
}
/*!
* @brief Put the sense code to array.
*
* @param sKey: sense Key
*
* @param ASC: Additional Sense Code
*
* @param ASCQ: Additional Sense Code Qualifier
*
* @retval None
*/
void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ)
{
g_scsiSenseCode[g_sensePutCnt].sensekey = sKey;
g_scsiSenseCode[g_sensePutCnt].ASC = ASC;
g_scsiSenseCode[g_sensePutCnt].ASCQ = ASCQ;
if ((++g_sensePutCnt) == SCSI_SENSE_LIST_NUMBER)
{
g_sensePutCnt = 0;
}
}
/*!
* @brief SCSI Test Unit Ready handler.
*
* @param lun: Logical unit number
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_TestUnitReady(uint8_t lun)
{
if (g_BOTInfo.CBW.dDataXferLen)
{
SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_CDB, 0);
return SCSI_FAIL;
}
else if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
return SCSI_FAIL;
}
else
{
g_BOTInfo.dataLen = 0;
return SCSI_OK;
}
}
/*!
* @brief SCSI Inquiry handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t* command)
{
uint16_t i;
uint8_t* pInquiryData;
if (command[1] & 0x01)
{
pInquiryData = (uint8_t*)s_page00InquiryData;
g_BOTInfo.dataLen = s_page00InquiryData[3] + 4;
}
else
{
pInquiryData = &g_storageCallBack.pInquiryData[lun * SCSI_INQUIRY_LENGTH];
g_BOTInfo.dataLen = USB_MIN((pInquiryData[4] + 5), command[4]);
}
for (i = 0; i < g_BOTInfo.dataLen; i++)
{
g_BOTInfo.data[i] = pInquiryData[i];
}
return SCSI_OK;
}
/*!
* @brief SCSI Request Sense handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t* command)
{
uint8_t i = 0;
while (i < SCSI_REQUEST_SENSE_DATA_LEN)
{
g_BOTInfo.data[i++] = 0;
}
g_BOTInfo.data[0] = 0x70;
g_BOTInfo.data[7] = SCSI_REQUEST_SENSE_DATA_LEN - 6;
if (g_senseTxCnt != g_sensePutCnt)
{
g_BOTInfo.data[2] = g_scsiSenseCode[g_senseTxCnt].sensekey;
g_BOTInfo.data[12] = g_scsiSenseCode[g_senseTxCnt].ASC;
g_BOTInfo.data[13] = g_scsiSenseCode[g_senseTxCnt].ASCQ;
if ((++g_senseTxCnt) == SCSI_SENSE_LIST_NUMBER)
{
g_senseTxCnt = 0;
}
}
g_BOTInfo.dataLen = (SCSI_REQUEST_SENSE_DATA_LEN < command[4]) ? \
SCSI_REQUEST_SENSE_DATA_LEN : command[4];
return SCSI_OK;
}
/*!
* @brief SCSI Read Format Capacity handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t* command)
{
uint16_t i = 0;
uint32_t blkSize;
uint32_t blkNbr;
while (i < 12)
{
g_BOTInfo.data[i++] = 0;
}
if (g_storageCallBack.ReadCapacity(lun, &blkNbr, &blkSize) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
return SCSI_FAIL;
}
else
{
blkNbr--;
g_BOTInfo.data[3] = 0x08;
g_BOTInfo.data[4] = (uint8_t)(blkNbr >> 24);
g_BOTInfo.data[5] = (uint8_t)(blkNbr >> 16);
g_BOTInfo.data[6] = (uint8_t)(blkNbr >> 8);
g_BOTInfo.data[7] = (uint8_t)(blkNbr);
g_BOTInfo.data[8] = 0x02;
g_BOTInfo.data[9] = (uint8_t)(blkSize >> 16);
g_BOTInfo.data[10] = (uint8_t)(blkSize >> 8);
g_BOTInfo.data[11] = (uint8_t)blkSize;
g_BOTInfo.dataLen = 12;
return SCSI_OK;
}
}
/*!
* @brief SCSI Read Capacity10 handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t* command)
{
if (g_storageCallBack.ReadCapacity(lun, &s_blkNbr, &s_blkSize) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
return SCSI_FAIL;
}
else
{
g_BOTInfo.data[0] = (uint8_t)((s_blkNbr - 1) >> 24);
g_BOTInfo.data[1] = (uint8_t)((s_blkNbr - 1) >> 16);
g_BOTInfo.data[2] = (uint8_t)((s_blkNbr - 1) >> 8);
g_BOTInfo.data[3] = (uint8_t)(s_blkNbr - 1);
g_BOTInfo.data[4] = (uint8_t)(s_blkSize >> 24);
g_BOTInfo.data[5] = (uint8_t)(s_blkSize >> 16);
g_BOTInfo.data[6] = (uint8_t)(s_blkSize >> 8);
g_BOTInfo.data[7] = (uint8_t)(s_blkSize);
g_BOTInfo.dataLen = 8;
return SCSI_OK;
}
}
/*!
* @brief SCSI Read10 handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_Read10(uint8_t lun, uint8_t* command)
{
uint8_t ret = SCSI_OK;
if (g_BOTInfo.state == BOT_STATE_IDLE)
{
if ((g_BOTInfo.CBW.bmFlags & 0x80) != 0x80)
{
SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_CDB, 0);
return SCSI_FAIL;
}
if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
return SCSI_FAIL;
}
s_blkAddr = ((uint32_t)command[2] << 24) | \
((uint32_t)command[3] << 16) | \
((uint32_t)command[4] << 8) | \
(uint32_t)command[5];
s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t )command[8]);
if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
{
return SCSI_FAIL;
}
g_BOTInfo.state = BOT_STATE_DATA_IN;
s_blkAddr *= s_blkSize;
s_blkLen *= s_blkSize;
if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
{
SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_CDB, 0);
return SCSI_FAIL;
}
}
g_BOTInfo.dataLen = MSC_MEDIA_PACKET;
ret = SCSI_Read(lun);
return ret;
}
/*!
* @brief SCSI write10 handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_Write10(uint8_t lun, uint8_t* command)
{
uint8_t ret = SCSI_OK;
uint32_t len;
if (g_BOTInfo.state == BOT_STATE_IDLE)
{
if (g_BOTInfo.CBW.bmFlags & 0x80)
{
SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_CDB, 0);
return SCSI_FAIL;
}
if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
return SCSI_FAIL;
}
if (g_storageCallBack.CheckWPR(lun) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
SCSI_ASC_WRITE_PROTECTED, 0);
return SCSI_FAIL;
}
s_blkAddr = ((uint32_t)command[2] << 24) | \
((uint32_t)command[3] << 16) | \
((uint32_t)command[4] << 8) | \
(uint32_t)command[5];
s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t )command[8]);
if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
{
return SCSI_FAIL;
}
s_blkAddr *= s_blkSize;
s_blkLen *= s_blkSize;
if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
{
SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_CDB, 0);
return SCSI_FAIL;
}
g_BOTInfo.state = BOT_STATE_DATA_OUT;
len = USB_MIN(s_blkLen, MSC_MEDIA_PACKET);
USBD_RxData(MSC_OUT_EP & 0x7F, g_BOTInfo.data, len);
}
else
{
ret = SCSI_Write(lun);
}
return ret;
}
/*!
* @brief SCSI Verify10 Handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_Verify10(uint8_t lun, uint8_t* command)
{
if (command[1] & 0x02)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_FIELED_IN_COMMAND, 0);
return SCSI_FAIL;
}
s_blkAddr = ((uint32_t)command[2] << 24) | \
((uint32_t)command[3] << 16) | \
((uint32_t)command[4] << 8) | \
(uint32_t)command[5];
s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t )command[8]);
if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
{
return SCSI_FAIL;
}
g_BOTInfo.dataLen = 0;
return SCSI_OK;
}
/*!
* @brief SCSI Start Stop Unit Handler.
*
* @param None
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_StartStopUnit(void)
{
g_BOTInfo.dataLen = 0;
return SCSI_OK;
}
/*!
* @brief SCSI Mode Sense6 Handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t* command)
{
for (uint16_t i = 0; i < 8; i++)
{
g_BOTInfo.data[i] = s_modeSense6Data[i];
}
g_BOTInfo.dataLen = 8;
return SCSI_OK;
}
/*!
* @brief SCSI Mode Sense10 Handler.
*
* @param lun: Logical unit number
*
* @param command: command pointer
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t* command)
{
for (uint16_t i = 0; i < 8; i++)
{
g_BOTInfo.data[i] = s_modeSense10Data[i];
}
g_BOTInfo.dataLen = 8;
return SCSI_OK;
}
/*!
* @brief SCSI Read Process.
*
* @param lun: Logical unit number
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_Read(uint8_t lun)
{
uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
if (g_storageCallBack.ReadData(len, g_BOTInfo.data, (s_blkAddr / s_blkSize),
(len / s_blkSize)) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR,
SCSI_ASC_UNRECOVERED_READ_ERROR, 0);
return SCSI_FAIL;
}
USBD_TxData(MSC_IN_EP & 0x7F, g_BOTInfo.data, len);
s_blkAddr += len;
s_blkLen -= len;
g_BOTInfo.CSW.dDataResidue -= len;
if (s_blkLen == 0)
{
g_BOTInfo.state = BOT_STATE_LAST_DATA_IN;
}
return SCSI_OK;
}
/*!
* @brief SCSI Write Process.
*
* @param lun: Logical unit number
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_Write(uint8_t lun)
{
uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
if (s_blkLen - len)
{
__NOP();
}
if (g_storageCallBack.WriteData(lun, g_BOTInfo.data, s_blkAddr / s_blkSize,
len / s_blkSize) != SCSI_OK)
{
SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, SCSI_ASC_WRITE_FAULT, 0);
return SCSI_FAIL;
}
s_blkAddr += len;
s_blkLen -= len;
g_BOTInfo.CSW.dDataResidue -= len;
if (s_blkLen)
{
len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
USBD_RxData(MSC_OUT_EP & 0x7f, g_BOTInfo.data, len);
}
else
{
USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
}
return SCSI_OK;
}
/*!
* @brief SCSI Check Address Range.
*
* @param lun: Logical unit number
*
* @param blkOffset: first block address
*
* @param blkNbr: number of block to be processed
*
* @retval SCSI_OK or SCSI_FAILL
*/
static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr)
{
if (s_blkNbr < (blkNbr + blkOffset))
{
SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
SCSI_ASC_ADDRESS_OUT_OF_RANGE, 0);
return SCSI_FAIL;
}
return SCSI_OK;
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h
+312
View File
@@ -0,0 +1,312 @@
/*!
* @file usbd_core.h
*
* @brief USB protocol core handler head file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __USBD_CORE_H_
#define __USBD_CORE_H_
#include "drv_usb_device.h"
/** Get minimum value */
#define USB_MIN(a, b) (a >= b ? b : a)
/** Get maximum value */
#define USB_MAX(a, b) (a >= b ? a : b)
/**
* @brief USB request type
*/
enum
{
USBD_REQ_TYPE_STANDARD = 0,
USBD_REQ_TYPE_CLASS = 1,
USBD_REQ_TYPE_VENDOR = 2,
USBD_REQ_TYPE_RESERVED = 3
};
/**
* @brief USB recipient
*/
enum
{
USBD_RECIPIENT_DEVICE = 0,
USBD_RECIPIENT_INTERFACE = 1,
USBD_RECIPIENT_ENDPOINT = 2,
USBD_RECIPIENT_OTHER = 3,
};
/**
* @brief USB standard device requests
*/
enum
{
USBD_GET_STATUS = 0,
USBD_CLEAR_FEATURE = 1,
USBD_SET_FEATURE = 3,
USBD_SET_ADDRESS = 5,
USBD_GET_DESCRIPTOR = 6,
USBD_SET_DESCRIPTOR = 7,
USBD_GET_CONFIGURATION = 8,
USBD_SET_CONFIGURATION = 9,
USBD_GET_INTERFACE = 10,
USBD_SET_INTERFACE = 11,
USBD_SYNCH_FRAME = 12,
};
/**
* @brief USB descriptor types
*/
enum
{
USBD_DESC_DEVICE = 1,
USBD_DESC_CONFIGURATION = 2,
USBD_DESC_STRING = 3,
USBD_DESC_INTERFACE = 4,
USBD_DESC_ENDPOINT = 5,
USBD_DESC_DEVICE_QUALIFIER = 6,
USBD_DESC_OTHER_SPEED = 7,
USBD_INTERFACE_POWER = 8,
};
/**
* @brief USB standard feature
*/
enum
{
USBD_FEATURE_ENDPOINT_HALT = 0,
USBD_FEATURE_REMOTE_WAKEUP = 1,
USBD_FEATURE_TEST_MODE = 2
};
/**
* @brief USB internal state machine
*/
typedef enum
{
USBD_CTRL_STATE_WAIT_SETUP,
USBD_CTRL_STATE_DATA_IN,
USBD_CTRL_STATE_DATA_OUT,
USBD_CTRL_STATE_WAIT_STATUS_IN,
USBD_CTRL_STATE_WAIT_STATUS_OUT,
USBD_CTRL_STATE_STALLED,
}USBD_CTRL_STATE_T;
/**
* @brief USBD Endpoint type for USB protocol
*/
typedef enum
{
USBD_EP_TYPE_CONTROL,
USBD_EP_TYPE_ISO,
USBD_EP_TYPE_BULK,
USBD_EP_TYPE_INTERRUPT
}USBD_EP_TYPE_T;
/**
* @brief USB request type
*/
typedef union
{
uint8_t byte;
struct
{
uint8_t recipient : 5;
uint8_t type : 2;
uint8_t dir : 1;
}bit;
}USBD_REQ_TYPE_T;
/**
* @brief USB device request data
*/
typedef struct
{
union
{
uint8_t pack[8];
struct
{
USBD_REQ_TYPE_T bmRequestType;
uint8_t bRequest;
uint8_t wValue[2];
uint8_t wIndex[2];
uint8_t wLength[2];
} byte;
};
} USBD_DevReqData_T;
/**
* @brief Descriptor structure
*/
typedef struct
{
const uint8_t *pDesc;
uint8_t size;
}USBD_Descriptor_T;
/** USB standard request callback handler */
typedef void (*USBD_StdReqHandler_T)(void);
/** USB request handler */
typedef void (*USBD_ReqHandler_T)(USBD_DevReqData_T *);
/** Ctrl Tx Status handler function define */
typedef void (*USBD_CtrlTxStatusHandler_T)(void);
/** Ctrl Rx Status handler function define */
typedef void (*USBD_CtrlRxStatusHandler_T)(void);
/** Endpoint handler */
typedef void (*USBD_EPHandler_T)(uint8_t ep);
/** Reset handler */
typedef void (*USBD_ResetHandler_T)(void);
/** Interrupt handler function define */
typedef void (*USBD_InterruptHandler_T)(void);
/**
* @brief USB Class Request handler
*/
typedef struct
{
USBD_StdReqHandler_T getConfigurationHandler;
USBD_StdReqHandler_T getDescriptorHandler;
USBD_StdReqHandler_T getInterfaceHandler;
USBD_StdReqHandler_T getStatusHandler;
USBD_StdReqHandler_T setAddressHandler;
USBD_StdReqHandler_T setConfigurationHandler;
USBD_StdReqHandler_T setDescriptorHandler;
USBD_StdReqHandler_T setFeatureHandler;
USBD_StdReqHandler_T setInterfaceHandler;
USBD_StdReqHandler_T clearFeatureHandler;
} USBD_StdReqCallback_T;
/**
* @brief Control transfer buffer
*/
typedef struct
{
uint8_t *pBuf; //!< Data buffer
uint32_t bufLen; //!< Length of the data buffer
uint8_t packNum; //!< Packet number of the data
uint8_t zeroPackFill; //!< Fill a zero pack for IN transfer or not
uint16_t maxPackSize; //!< Max pack size of this endpoint
uint32_t xferCnt; //!< Data count of one pack on from tansfer
} USBD_CtrlBuf_T;
/**
* @brief USB init parameter
*/
typedef struct
{
USBD_Descriptor_T *pDeviceDesc; //!< Device descriptor pointer
USBD_Descriptor_T *pConfigurationDesc; //!< Configuration descriptor pointer
USBD_Descriptor_T *pStringDesc; //!< String descriptor pointer
USBD_Descriptor_T *pQualifierDesc; //!< Device Qualifier descriptor pointer
USBD_Descriptor_T *pHidReportDesc; //!< HID report descriptor pointer
USBD_StdReqCallback_T *pStdReqCallback;
USBD_ReqHandler_T stdReqExceptionHandler; //!< Standard request exception handler
USBD_ReqHandler_T classReqHandler; //!< Class request handler
USBD_ReqHandler_T vendorReqHandler; //!< vendor request handler
USBD_CtrlTxStatusHandler_T txStatusHandler; //!< Send IN status early handler
USBD_CtrlRxStatusHandler_T rxStatusHandler; //!< Receive OUT status early handler
USBD_EPHandler_T outEpHandler; //!< OUT EP transfer done handler except EP0
USBD_EPHandler_T inEpHandler; //!< IN EP transfer done handler except EP0
USBD_ResetHandler_T resetHandler; //!< Reset handler
USBD_InterruptHandler_T intHandler; //!< Hadler the rest of interrupt.
} USBD_InitParam_T;
/**
* @brief USB infomation
*/
typedef struct
{
USBD_CTRL_STATE_T ctrlState;
uint8_t curFeature;
uint8_t curInterface;
uint8_t curAlternateSetting;
uint8_t curConfiguration;
uint8_t configurationNum;
/** Setup request data buffer */
USBD_DevReqData_T reqData;
/** Endpoint buffer management */
USBD_CtrlBuf_T inBuf[USB_EP_MAX_NUM];
USBD_CtrlBuf_T outBuf[USB_EP_MAX_NUM];
/** Descriptor pointer */
USBD_Descriptor_T *pDeviceDesc;
USBD_Descriptor_T *pConfigurationDesc;
USBD_Descriptor_T *pStringDesc;
USBD_Descriptor_T *pQualifierDesc;
USBD_Descriptor_T *pHidReportDesc;
/** Setup request callback handler */
USBD_StdReqCallback_T *pStdReqCallback;
USBD_ReqHandler_T stdReqExceptionHandler;
USBD_ReqHandler_T classReqHandler;
USBD_ReqHandler_T vendorReqHandler;
/** Control transfer status stage handler */
USBD_CtrlTxStatusHandler_T txStatusHandler;
USBD_CtrlRxStatusHandler_T rxStatusHandler;
/** Endpoint transfer done handler */
USBD_EPHandler_T outEpHandler;
USBD_EPHandler_T inEpHandler;
USBD_ResetHandler_T resetHandler;
USBD_InterruptHandler_T intHandler;
} USBD_Info_T;
extern USBD_Info_T g_usbDev;
/** control status function */
#define USBD_CtrlTxStatus() USBD_CtrlInData(NULL, 0);
#define USBD_CtrlRxStatus() USBD_CtrlOutData(NULL, 0)
/** Handler Endpoint 0 control transfer */
void USBD_SetupProcess(void);
void USBD_CtrlInProcess(void);
void USBD_CtrlOutProcess(void);
void USBD_CtrlOutData(uint8_t *buf, uint32_t len);
void USBD_CtrlInData(uint8_t *buf, uint32_t len);
/** Handler other Endpoint data transfer */
void USBD_DataInProcess(USBD_EP_T ep);
void USBD_DataOutProcess(USBD_EP_T ep);
void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len);
void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len);
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h
+64
View File
@@ -0,0 +1,64 @@
/*!
* @file usbd_init.h
*
* @brief USB initialization management head file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef USBD_INIT_H_
#define USBD_INIT_H_
#include "usbd_core.h"
/**
* @brief Endpoint Configuration Info
*/
typedef struct
{
USBD_EP_T epNum; //!< endpoint number
USBD_EP_TYPE_T epType; //!< endpoint type
uint8_t epKind; /**
* Which could be ENABLE or DISABLE, it is valid only for
* control and bulk Endpoint. The mean of ENABLE for them like :
* 1. Control endpoint : Only for OUT status which is zero data.
* 2. Bulk endpoint : Enable the double-buffer feature
*/
USBD_EP_STATUS_T epStatus; //!< Endpoint status
uint16_t epBufAddr; //!< buffer address for the endpoint
uint16_t maxPackSize; //!< max packet size for the endpoint
} USBD_EPConfig_T;
/** USB init */
void USBD_Init(USBD_InitParam_T *param);
void USBD_InitParamStructInit(USBD_InitParam_T *param);
/** power */
void USBD_PowerOn(void);
void USBD_PowerOff(void);
/** Endpoint init */
void USBD_OpenOutEP(USBD_EPConfig_T *epConfig);
void USBD_OpenInEP(USBD_EPConfig_T *epConfig);
void USBD_CloseOutEP(USBD_EP_T ep);
void USBD_CloseInEP(USBD_EP_T ep);
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h
+31
View File
@@ -0,0 +1,31 @@
/*!
* @file usbd_interrupt.h
*
* @brief USB interrupt service routine header file
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __USBD_INTERRUPT_H_
#define __USBD_INTERRUPT_H_
#include "apm32f10x.h"
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h
+31
View File
@@ -0,0 +1,31 @@
/*!
* @file usbd_stdReq.h
*
* @brief USB standard request process head file
*
* @version V1.0.0
*
* @date 2021-12-30
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __USBD_STDREQ_H_
#define __USBD_STDREQ_H_
void USBD_StandardReqeust(void);
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c
+405
View File
@@ -0,0 +1,405 @@
/*!
* @file usbd_core.c
*
* @brief USB protocol core handler
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_core.h"
#include "usbd_stdReq.h"
/** USB information */
USBD_Info_T g_usbDev;
/*!
* @brief Endpoint 0 Setup process
*
* @param None
*
* @retval None
*/
void USBD_SetupProcess(void)
{
uint8_t reqType;
uint8_t dataBuf[8];
USBD_DevReqData_T *pReqData = &g_usbDev.reqData;
uint16_t xferLen = USBD_ReadEPRxCnt(USBD_EP_0);
if (xferLen)
{
USBD_ReadDataFromEP(USBD_EP_0, (uint8_t *)dataBuf, xferLen);
}
else
{
return;
}
pReqData->byte.bmRequestType.byte = dataBuf[0];
pReqData->byte.bRequest = dataBuf[1];
pReqData->byte.wValue[0] = dataBuf[2];
pReqData->byte.wValue[1] = dataBuf[3];
pReqData->byte.wIndex[0] = dataBuf[4];
pReqData->byte.wIndex[1] = dataBuf[5];
pReqData->byte.wLength[0] = dataBuf[6];
pReqData->byte.wLength[1] = dataBuf[7];
reqType = pReqData->byte.bmRequestType.bit.type;
if(reqType == USBD_REQ_TYPE_STANDARD)
{
USBD_StandardReqeust();
}
else if(reqType == USBD_REQ_TYPE_CLASS)
{
if(g_usbDev.classReqHandler)
{
g_usbDev.classReqHandler(pReqData);
}
}
else if(reqType == USBD_REQ_TYPE_VENDOR)
{
if(g_usbDev.vendorReqHandler)
{
g_usbDev.vendorReqHandler(pReqData);
}
}
else
{
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
}
}
/*!
* @brief Endpoint 0 USB Control in process
*
* @param None
*
* @retval None
*/
void USBD_CtrlInProcess(void)
{
uint32_t tmp;
if(g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_IN)
{
if(g_usbDev.inBuf[0].packNum)
{
tmp = USB_MIN(g_usbDev.inBuf[0].bufLen, g_usbDev.inBuf[0].maxPackSize);
USBD_WriteDataToEP(USBD_EP_0, g_usbDev.inBuf[0].pBuf, tmp);
USBD_SetEPTxCnt(USBD_EP_0, tmp);
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
g_usbDev.inBuf[0].pBuf += tmp;
g_usbDev.inBuf[0].bufLen -= tmp;
g_usbDev.inBuf[0].packNum--;
}
else
{
if (g_usbDev.inBuf[USBD_EP_0].zeroPackFill)
{
USBD_SetEPTxCnt(USBD_EP_0, 0);
USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID);
g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 0;
}
else
{
if (g_usbDev.rxStatusHandler)
{
g_usbDev.rxStatusHandler();
}
g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT;
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
}
}
}
else if(g_usbDev.ctrlState == USBD_CTRL_STATE_WAIT_STATUS_IN)
{
if(g_usbDev.reqData.byte.bRequest == USBD_SET_ADDRESS)
{
USBD_SetDeviceAddr(g_usbDev.reqData.byte.wValue[0]);
}
}
}
/*!
* @brief Endpoint 0 USB Control out process
*
* @param None
*
* @retval None
*/
void USBD_CtrlOutProcess(void)
{
uint32_t len;
if(g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_OUT)
{
if(g_usbDev.outBuf[0].packNum)
{
len = USB_MIN(g_usbDev.outBuf[0].bufLen, g_usbDev.outBuf[0].maxPackSize);
USBD_ReadDataFromEP(USBD_EP_0, g_usbDev.outBuf[0].pBuf, len);
g_usbDev.outBuf[0].bufLen -= len;
g_usbDev.outBuf[0].pBuf += len;
g_usbDev.outBuf[0].packNum--;
if (g_usbDev.outBuf[0].packNum)
{
USBD_CtrlOutData(g_usbDev.outBuf[0].pBuf, g_usbDev.outBuf[0].bufLen);
}
else
{
USBD_CtrlTxStatus();
}
}
else
{
if (g_usbDev.txStatusHandler)
{
g_usbDev.txStatusHandler();
}
USBD_CtrlTxStatus();
}
}
}
/*!
* @brief Send data or status in control in transation
*
* @param buf: Buffer pointer
*
* @param len: Buffer length
*
* @retval None
*/
void USBD_CtrlInData(uint8_t *buf, uint32_t len)
{
uint16_t maxPackSize = g_usbDev.inBuf[0].maxPackSize;
uint16_t reqLen = *(uint16_t*)g_usbDev.reqData.byte.wLength;
if(len)
{
if ((len < reqLen) && ((len % maxPackSize) == 0))
{
g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 1;
}
if(len >= g_usbDev.inBuf[0].maxPackSize)
{
/** Send a packet */
USBD_WriteDataToEP(USBD_EP_0, buf, g_usbDev.inBuf[0].maxPackSize);
USBD_SetEPTxCnt(USBD_EP_0, g_usbDev.inBuf[0].maxPackSize);
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
/** deal with buffer */
g_usbDev.inBuf[0].bufLen = len - g_usbDev.inBuf[0].maxPackSize;
g_usbDev.inBuf[0].pBuf = buf + g_usbDev.inBuf[0].maxPackSize;
g_usbDev.inBuf[0].packNum = (g_usbDev.inBuf[0].bufLen + (maxPackSize - 1)) / maxPackSize;
g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_IN;
}
else
{
USBD_WriteDataToEP(USBD_EP_0, buf, len);
USBD_SetEPTxCnt(USBD_EP_0, len);
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \
USBD_CTRL_STATE_DATA_IN : \
USBD_CTRL_STATE_WAIT_STATUS_IN;
}
}
else
{
USBD_SetEPTxCnt(USBD_EP_0, 0);
USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID);
g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \
USBD_CTRL_STATE_DATA_IN : \
USBD_CTRL_STATE_WAIT_STATUS_IN;
}
}
/*!
* @brief Read data or status in control out transation
*
* @param buf: Buffer pointer
*
* @param len: Buffer length
*
* @retval None
*/
void USBD_CtrlOutData(uint8_t *buf, uint32_t len)
{
uint16_t maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize;
if (len)
{
g_usbDev.outBuf[USBD_EP_0].pBuf = buf;
g_usbDev.outBuf[USBD_EP_0].bufLen = len;
g_usbDev.outBuf[USBD_EP_0].packNum = (len + (maxPackSize - 1)) / maxPackSize;
len = USB_MIN(g_usbDev.outBuf[0].bufLen, maxPackSize);
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_OUT;
}
else
{
g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT;
}
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
}
/*!
* @brief USB Data in process except endpoint 0
*
* @param ep : endpoint Number except endpoint 0
*
* @retval None
*/
void USBD_DataInProcess(USBD_EP_T ep)
{
uint16_t len;
if (g_usbDev.inBuf[ep].packNum)
{
len = g_usbDev.inBuf[ep].bufLen > g_usbDev.inBuf[ep].maxPackSize ? \
g_usbDev.inBuf[ep].maxPackSize : g_usbDev.inBuf[ep].bufLen;
USBD_WriteDataToEP(ep, g_usbDev.inBuf[ep].pBuf, len);
USBD_SetEPTxCnt(ep, len);
USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
g_usbDev.inBuf[ep].pBuf += len;
g_usbDev.inBuf[ep].bufLen -= len;
g_usbDev.inBuf[ep].packNum--;
}
else
{
if(g_usbDev.inEpHandler)
{
g_usbDev.inEpHandler(ep);
}
}
}
/*!
* @brief USB Data out process except endpoint 0
*
* @param ep : endpoint Number except endpoint 0
*
* @retval None
*/
void USBD_DataOutProcess(USBD_EP_T ep)
{
if (g_usbDev.outBuf[ep].packNum)
{
g_usbDev.outBuf[ep].xferCnt = USBD_ReadEPRxCnt(ep);
if ((g_usbDev.outBuf[ep].xferCnt != 0) && (g_usbDev.outBuf[ep].pBuf != NULL))
{
USBD_ReadDataFromEP(ep, g_usbDev.outBuf[ep].pBuf, g_usbDev.outBuf[ep].xferCnt);
g_usbDev.outBuf[ep].bufLen -= g_usbDev.outBuf[ep].xferCnt;
g_usbDev.outBuf[ep].pBuf += g_usbDev.outBuf[ep].xferCnt;
g_usbDev.outBuf[ep].packNum--;
}
if (g_usbDev.outBuf[ep].packNum)
{
USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID);
}
}
if(g_usbDev.outEpHandler && !g_usbDev.outBuf[ep].packNum)
{
g_usbDev.outEpHandler(ep);
}
}
/*!
* @brief Transfer data to host(except endpoint 0)
*
* @param ep: Endpoint number except endpoint 0
*
* @param buf: Buffer pointer
*
* @param len: Buffer length
*
* @retval None
*/
void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len)
{
uint16_t maxPackSize = g_usbDev.inBuf[ep].maxPackSize;
if (len >= maxPackSize)
{
USBD_WriteDataToEP(ep, buf, maxPackSize);
USBD_SetEPTxCnt(ep, maxPackSize);
USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
g_usbDev.inBuf[ep].pBuf = buf + maxPackSize;
g_usbDev.inBuf[ep].bufLen = len - maxPackSize;
g_usbDev.inBuf[ep].packNum =(g_usbDev.inBuf[ep].bufLen + (maxPackSize - 1)) / maxPackSize;
}
else
{
USBD_WriteDataToEP(ep, buf, len);
USBD_SetEPTxCnt(ep, len);
USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
g_usbDev.inBuf[ep].packNum = 0;
g_usbDev.inBuf[ep].bufLen = 0;
}
}
/*!
* @brief Receive data from host(except endpoint 0)
*
* @param ep: Endpoint number except endpoint 0
*
* @param buf: Buffer pointer
*
* @param len: Buffer length
*
* @retval None
*/
void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len)
{
uint16_t maxPackSize = g_usbDev.outBuf[ep].maxPackSize;
g_usbDev.outBuf[ep].pBuf = buf;
g_usbDev.outBuf[ep].bufLen = len;
g_usbDev.outBuf[ep].packNum = (len + (maxPackSize - 1)) / maxPackSize;
USBD_SetEPRxCnt(ep, USB_MIN(len, maxPackSize));
USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID);
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c
+237
View File
@@ -0,0 +1,237 @@
/*!
* @file usbd_init.c
*
* @brief USB initialization management
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_init.h"
#include "usb_bsp.h"
static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType);
/*!
* @brief USB initialization
*
* @param param: Initialization parameter
*
* @retval None
*/
void USBD_Init(USBD_InitParam_T *param)
{
g_usbDev.pDeviceDesc = param->pDeviceDesc;
g_usbDev.pConfigurationDesc = param->pConfigurationDesc;
g_usbDev.pStringDesc = param->pStringDesc;
g_usbDev.pQualifierDesc = param->pQualifierDesc;
g_usbDev.pHidReportDesc = param->pHidReportDesc;
g_usbDev.pStdReqCallback = param->pStdReqCallback;
g_usbDev.classReqHandler = param->classReqHandler;
g_usbDev.vendorReqHandler = param->vendorReqHandler;
g_usbDev.stdReqExceptionHandler = param->stdReqExceptionHandler;
g_usbDev.txStatusHandler = param->txStatusHandler;
g_usbDev.rxStatusHandler = param->rxStatusHandler;
g_usbDev.inEpHandler = param->inEpHandler;
g_usbDev.outEpHandler = param->outEpHandler;
g_usbDev.resetHandler = param->resetHandler;
g_usbDev.intHandler = param->intHandler;
USBD_HardWareInit();
#ifndef APM32F0xx_USB
#if USB_SELECT == USB1
USBD2_Disable();
#else
USB2_Enable();
#endif
#endif
USBD_PowerOn();
}
/*!
* @brief Init parameter in param
*
* @param param: Initialization parameter
*
* @retval None
*/
void USBD_InitParamStructInit(USBD_InitParam_T *param)
{
param->pStdReqCallback = NULL;
param->stdReqExceptionHandler = NULL;
param->classReqHandler = NULL;
param->vendorReqHandler = NULL;
param->txStatusHandler = NULL;
param->rxStatusHandler = NULL;
param->outEpHandler = NULL;
param->inEpHandler = NULL;
param->resetHandler = NULL;
param->intHandler = NULL;
}
/*!
* @brief USB Power on
*
* @param None
*
* @retval None
*/
void USBD_PowerOn(void)
{
USBD_ResetPowerDown();
USBD_SetForceReset();
USBD_ResetForceReset();
USBD_DisableInterrupt(USBD_INT_ALL);
USBD_ClearIntFlag(USBD_INT_ALL);
USBD_EnableInterrupt(USB_INT_SOURCE);
}
/*!
* @brief USB Power off
*
* @param None
*
* @retval None
*/
void USBD_PowerOff(void)
{
USBD_DisableInterrupt(USBD_INT_ALL);
USBD_ClearIntFlag(USBD_INT_ALL);
/** Power down and Force USB Reset */
USBD_SetRegCTRL(0X03);
}
/*!
* @brief Open OUT endpoint.
*
* @param epConfig: Point to USBD_EPConfig_T structure
*
* @retval None
*/
void USBD_OpenOutEP(USBD_EPConfig_T *epConfig)
{
g_usbDev.outBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize;
USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType));
if (epConfig->epKind)
{
USBD_SetEPKind(epConfig->epNum);
}
else
{
USBD_ResetEPKind(epConfig->epNum);
}
USBD_SetEPRxAddr(epConfig->epNum, epConfig->epBufAddr);
USBD_SetEPRxCnt(epConfig->epNum, epConfig->maxPackSize);
USBD_SetEPRxStatus(epConfig->epNum, epConfig->epStatus);
}
/*!
* @brief Open IN endpoint.
*
* @param epConfig: Point to USBD_EPConfig_T structure
*
* @retval None
*/
void USBD_OpenInEP(USBD_EPConfig_T *epConfig)
{
g_usbDev.inBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize;
USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType));
if (epConfig->epKind)
{
USBD_SetEPKind(epConfig->epNum);
}
else
{
USBD_ResetEPKind(epConfig->epNum);
}
USBD_SetEPTxAddr(epConfig->epNum, epConfig->epBufAddr);
USBD_SetEPTxStatus(epConfig->epNum, epConfig->epStatus);
}
/*!
* @brief Close OUT endpoint.
*
* @param ep: OUT endpoint Number
*
* @retval None
*/
void USBD_CloseOutEP(USBD_EP_T ep)
{
g_usbDev.outBuf[ep].maxPackSize = 0;
USBD_SetEPRxStatus(ep, USBD_EP_STATUS_DISABLE);
}
/*!
* @brief Close IN endpoint.
*
* @param ep: IN endpoint Number
*
* @retval None
*/
void USBD_CloseInEP(USBD_EP_T ep)
{
g_usbDev.inBuf[ep].maxPackSize = 0;
USBD_SetEPTxStatus(ep, USBD_EP_STATUS_DISABLE);
}
/*!
* @brief Convert endpoint Type.
*
* @param epType: endpoint type
*
* @retval Value of USBD_REG_EP_TYPE_T
*/
static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType)
{
switch (epType)
{
case USBD_EP_TYPE_CONTROL :
return USBD_REG_EP_TYPE_CONTROL;
case USBD_EP_TYPE_ISO :
return USBD_REG_EP_TYPE_ISO;
case USBD_EP_TYPE_BULK :
return USBD_REG_EP_TYPE_BULK;
case USBD_EP_TYPE_INTERRUPT :
return USBD_REG_EP_TYPE_INTERRUPT;
default :
return USBD_REG_EP_TYPE_CONTROL;
}
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c
+349
View File
@@ -0,0 +1,349 @@
/*!
* @file usbd_interrupt.c
*
* @brief USB interrupt service routine
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_init.h"
static void USBD_LowPriorityProc(void);
static void USBD_ResetIsrHandler(void);
static void USBD_SuspendIsrHandler(void);
static void USBD_ResumeIsrHandler(void);
/*!
* @brief USB interrupt service routine
*
* @param None
*
* @retval None
*/
#ifdef APM32F0xx_USB
void USB_IRQHandler(void)
#else //!< APM32F10x_USB
#if USB_SELECT == USB1
void USBD1_LP_CAN1_RX0_IRQHandler(void)
#else
void USB2_LP_IRQHandler(void)
#endif
#endif
{
#if (USB_INT_SOURCE & USBD_INT_CTR)
if(USBD_ReadIntFlag(USBD_INT_CTR))
{
USBD_LowPriorityProc();
}
#endif
#if (USB_INT_SOURCE & USBD_INT_RST)
if(USBD_ReadIntFlag(USBD_INT_RST))
{
USBD_ClearIntFlag(USBD_INT_RST);
USBD_ResetIsrHandler();
}
#endif
#if USB_INT_SOURCE & USBD_INT_PMAOU
if(USB_ReadIntFlag(USB_INT_PMAOU))
{
USB_ClearIntFlag(USB_INT_PMAOU);
}
#endif
#if USB_INT_SOURCE & USBD_INT_ERR
if(USB_ReadIntFlag(USB_INT_ERROR))
{
USB_ClearIntFlag(USB_INT_ERROR);
}
#endif
#if USB_INT_SOURCE & USBD_INT_WKUP
if(USBD_ReadIntFlag(USBD_INT_WKUP))
{
USBD_ResumeIsrHandler();
USBD_ClearIntFlag(USBD_INT_WKUP);
}
#endif
#if USB_INT_SOURCE & USBD_INT_SUS
if(USBD_ReadIntFlag(USBD_INT_SUS))
{
USBD_SuspendIsrHandler();
USBD_ClearIntFlag(USBD_INT_SUS);
}
#endif
#if USB_INT_SOURCE & USBD_INT_SOF
if(USB_ReadIntFlag(USB_INT_SOF))
{
USB_ClearIntFlag(USB_INT_SOF);
}
#endif
#if USB_INT_SOURCE & USBD_INT_ESOF
if(USB_ReadIntFlag(USB_INT_ESOF))
{
USB_ClearIntFlag(USB_INT_ESOF);
}
#endif
}
/*!
* @brief USB low priority process
*
* @param None
*
* @retval None
*/
static void USBD_LowPriorityProc(void)
{
USBD_EP_T ep;
while(USBD_ReadIntFlag(USBD_INT_CTR))
{
ep = (USBD_EP_T)USBD_ReadEP();
/** Endpoint 0 */
if(ep == 0)
{
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_NAK);
/** Control in */
if(USBD_ReadDir() == 0)
{
USBD_ResetEPTxFlag(USBD_EP_0);
USBD_CtrlInProcess();
}
else
{
/** Setup */
if(USBD_ReadEPSetup(USBD_EP_0) == SET)
{
USBD_ResetEPRxFlag(USBD_EP_0);
USBD_SetupProcess();
}
/** Control out */
else
{
USBD_ResetEPRxFlag(USBD_EP_0);
USBD_CtrlOutProcess();
}
}
}
/** Transfer Handler Except endpoint 0 */
else
{
if (USBD_ReadEPRxFlag(ep))
{
USBD_ResetEPRxFlag(ep);
USBD_DataOutProcess(ep);
}
if (USBD_ReadEPTxFlag(ep))
{
USBD_ResetEPTxFlag(ep);
USBD_DataInProcess(ep);
}
}
}
}
/*!
* @brief USB Device Reset
*
* @param None
*
* @retval None
*/
static void USBD_ResetIsrHandler(void)
{
uint8_t i;
USBD_EPConfig_T epConfig;
g_usbDev.configurationNum = USB_CONFIGURATION_NUM;
g_usbDev.curConfiguration = 0;
g_usbDev.curInterface = 0;
g_usbDev.curAlternateSetting = 0;
g_usbDev.curFeature = 0;
g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_SETUP;
g_usbDev.inBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE;
g_usbDev.outBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE;
USBD_SetBufferTable(USB_BUFFER_TABLE_ADDR);
/** Endpoint 0 IN */
epConfig.epNum = USBD_EP_0;
epConfig.epType = USBD_EP_TYPE_CONTROL;
epConfig.epKind = DISABLE;
epConfig.epBufAddr = USB_EP0_TX_ADDR;
epConfig.maxPackSize = g_usbDev.inBuf[USBD_EP_0].maxPackSize;
epConfig.epStatus = USBD_EP_STATUS_NAK;
USBD_OpenInEP(&epConfig);
/** Endpoint 0 OUT */
epConfig.epBufAddr = USB_EP0_RX_ADDR;
epConfig.maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize;
epConfig.epStatus = USBD_EP_STATUS_VALID;
USBD_OpenOutEP(&epConfig);
if(g_usbDev.resetHandler)
{
g_usbDev.resetHandler();
}
for(i = 0; i < USB_EP_MAX_NUM; i++)
{
USBD_SetEpAddr((USBD_EP_T)i, i);
}
USBD_SetDeviceAddr(0);
USBD_Enable();
}
/*!
* @brief USB Suspend
*
* @param None
*
* @retval None
*/
static void USBD_SuspendIsrHandler(void)
{
uint8_t i;
uint16_t bakEP[8];
#if USB_LOW_POWER_SWITCH
uint32_t bakPwrCR;
uint32_t tmp;
#endif
for(i = 0; i < 8; i++)
{
bakEP[i] = (uint16_t)USBD->EP[i].EP;
}
USBD_EnableInterrupt(USBD_INT_RST);
USBD_SetForceReset();
USBD_ResetForceReset();
while(USBD_ReadIntFlag(USBD_INT_RST) == RESET);
for(i = 0; i < 8; i++)
{
USBD->EP[i].EP = bakEP[i];
}
USBD_SetForceSuspend();
#if USB_LOW_POWER_SWITCH
USBD_SetLowerPowerMode();
bakPwrCR = PMU->CTRL;
tmp = PMU->CTRL;
tmp &= (uint32_t)0xfffffffc;
tmp |= PMU_REGULATOR_LOWPOWER;
PMU->CTRL = tmp;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
if(USBD_ReadIntFlag(USBD_INT_WKUP) == RESET)
{
__WFI();
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
else
{
USBD_ClearIntFlag(USBD_INT_WKUP);
USBD_ResetForceSuspend();
PMU->CTRL = bakPwrCR;
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
#endif
}
/*!
* @brief Resume
*
* @param None
*
* @retval None
*/
static void USBD_ResumeIsrHandler(void)
{
#if USB_LOW_POWER_SWITCH
USBD_ResetLowerPowerMode();
#endif
SystemInit();
USBD_SetRegCTRL(USB_INT_SOURCE);
}
#ifndef APM32F0xx_USB
/*!
* @brief USB High priority process
*
* @param None
*
* @retval None
*/
static void USBD_HighPriorityProc(void)
{
USBD_EP_T ep;
while(USBD_ReadIntFlag(USBD_INT_CTR))
{
USBD_ClearIntFlag(USBD_INT_CTR);
ep = USBD_ReadEP();
if(USBD_ReadEPRxFlag(ep))
{
USBD_ResetEPRxFlag(ep);
g_usbDev.outEpHandler(ep);
}
if(USBD_ReadEPTxFlag(ep))
{
USBD_ResetEPTxFlag(ep);
g_usbDev.inEpHandler(ep);
}
}
}
#if USB_SELECT == USB1
void USBD1_HP_CAN1_TX_IRQHandler(void)
#else
void USB2_HP_IRQHandler(void)
#endif
{
USBD_HighPriorityProc();
}
#endif
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c
+369
View File
@@ -0,0 +1,369 @@
/*!
* @file usbd_stdReq.c
*
* @brief USB standard request process
*
* @version V1.0.0
*
* @date 2021-12-30
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "usbd_stdReq.h"
#include "usbd_core.h"
#include "usbd_descriptor.h"
static uint8_t USBD_StandardGetConfiguration(void);
static uint8_t USBD_StandardGetDescriptor(void);
static uint8_t USBD_StandardGetInterface(void);
static uint8_t USBD_StandardGetStatus(void);
static uint8_t USBD_StandardSetAddress(void);
static uint8_t USBD_StandardSetConfiguration(void);
static uint8_t USBD_StandardSetDescriptor(void);
static uint8_t USBD_StandardSetFeature(void);
static uint8_t USBD_StandardSetInterface(void);
static uint8_t USBD_StandardClearFeature(void);
/*!
* @brief USB request standard request
*
* @param None
*
* @retval None
*/
void USBD_StandardReqeust(void)
{
uint8_t result = 1;
uint8_t bRequest = g_usbDev.reqData.byte.bRequest;
switch(bRequest)
{
case USBD_GET_CONFIGURATION:
result = USBD_StandardGetConfiguration();
break;
case USBD_GET_DESCRIPTOR:
result = USBD_StandardGetDescriptor();
break;
case USBD_GET_INTERFACE:
result = USBD_StandardGetInterface();
break;
case USBD_GET_STATUS:
result = USBD_StandardGetStatus();
break;
case USBD_SET_ADDRESS:
result = USBD_StandardSetAddress();
break;
case USBD_SET_CONFIGURATION:
result = USBD_StandardSetConfiguration();
break;
case USBD_SET_DESCRIPTOR:
result = USBD_StandardSetDescriptor();
break;
case USBD_SET_FEATURE:
result = USBD_StandardSetFeature();
break;
case USBD_SET_INTERFACE:
result = USBD_StandardSetInterface();
break;
case USBD_CLEAR_FEATURE:
result = USBD_StandardClearFeature();
break;
default:
break;
}
if(!result)
{
if(g_usbDev.stdReqExceptionHandler != NULL)
{
g_usbDev.stdReqExceptionHandler(&g_usbDev.reqData);
}
}
}
/*!
* @brief Standard request get configuration
*
* @param None
*
* @retval ERROR: 0; SUCCESS : 1
*/
static uint8_t USBD_StandardGetConfiguration(void)
{
uint8_t recipient = g_usbDev.reqData.byte.bmRequestType.bit.recipient;
if(recipient == USBD_RECIPIENT_DEVICE)
{
USBD_CtrlInData(&g_usbDev.curConfiguration, 1);
if (g_usbDev.pStdReqCallback->getConfigurationHandler)
{
g_usbDev.pStdReqCallback->getConfigurationHandler();
}
return SUCCESS;
}
return ERROR;
}
/*!
* @brief Standard request get descriptor
*
* @param None
*
* @retval ERROR: 0; SUCCESS : 1
*/
static uint8_t USBD_StandardGetDescriptor(void)
{
uint8_t ret = SUCCESS;
uint32_t len = 0;
uint8_t wValue0 = g_usbDev.reqData.byte.wValue[0];
uint8_t wValue1 = g_usbDev.reqData.byte.wValue[1];
if(wValue1 == USBD_DESC_DEVICE)
{
len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pDeviceDesc->size);
USBD_CtrlInData((uint8_t *)g_usbDev.pDeviceDesc->pDesc, len);
}
else if(wValue1 == USBD_DESC_CONFIGURATION)
{
len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pConfigurationDesc->size);
USBD_CtrlInData((uint8_t *)g_usbDev.pConfigurationDesc->pDesc, len);
}
else if(wValue1 == USBD_DESC_STRING)
{
if (wValue0 < SRTING_DESC_NUM)
{
len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pStringDesc[wValue0].size);
USBD_CtrlInData((uint8_t *)g_usbDev.pStringDesc[wValue0].pDesc, len);
}
else
{
ret = ERROR;
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
}
}
else
{
ret = ERROR;
USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
}
return ret;
}
/*!
* @brief Standard request get interface
*
* @param None
*
* @retval ERROR: 0; SUCCESS : 1
*/
static uint8_t USBD_StandardGetInterface(void)
{
return ERROR;
}
/*!
* @brief Standard request get status
*
* @param None
*
* @retval ERROR: 0; SUCCESS : 1
*/
static uint8_t USBD_StandardGetStatus(void)
{
uint8_t ret = 1;
uint8_t status[2] = {0, 0};
if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_DEVICE)
{
if(g_usbDev.curFeature & (1 << 5))
{
status[0] |= 0x02;
}
if(g_usbDev.curFeature & (1 << 6))
{
status[0] |= 0x01;
}
USBD_CtrlInData(status, 2);
}
else if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_INTERFACE)
{
USBD_CtrlInData(status, 2);
}
else if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_ENDPOINT)
{
if(g_usbDev.reqData.byte.wIndex[0] & 0x80)
{
if(USBD_ReadEPTxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL)
{
status[0] |= 0x01;
}
}
else
{
if(USBD_ReadEPRxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL)
{
status[0] |= 0x01;
}
}
USBD_CtrlInData(status, 2);
}
else
{
ret = 0;
}
return ret;
}
/*!
* @brief Standard request set address
*
* @param None
*
* @retval ERROR: 0; SUCCESS : 1
*/
static uint8_t USBD_StandardSetAddress(void)
{
USBD_DevReqData_T *reqData = &g_usbDev.reqData;
if((reqData->byte.wValue[0] < 127) && (reqData->byte.wValue[1] == 0) &&
(reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE))
{
USBD_CtrlInData((void *)0, 0);
return 1;
}
return 0;
}
/*!
* @brief Standard request set configuration
*
* @param None
*
* @retval ERROR: 0; SUCCESS : 1
*/
static uint8_t USBD_StandardSetConfiguration(void)
{
USBD_DevReqData_T *reqData = &g_usbDev.reqData;
if((reqData->byte.wValue[0] <= g_usbDev.configurationNum) && \
(reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE))
{
g_usbDev.curConfiguration = reqData->byte.wValue[0];
if (g_usbDev.pStdReqCallback->setConfigurationHandler)
{
g_usbDev.pStdReqCallback->setConfigurationHandler();
}
USBD_CtrlInData((void *)0, 0);
return 1;
}
return 0;
}
/*!
* @brief Standard request set descriptor
*
* @param None
*
* @retval 0: Failed; 1: Success
*/
static uint8_t USBD_StandardSetDescriptor(void)
{
return ERROR;
}
/*!
* @brief Standard request set feature
*
* @param None
*
* @retval 0: Failed; 1: Success
*/
static uint8_t USBD_StandardSetFeature(void)
{
uint8_t ret = 1;
return ret;
}
/*!
* @brief Standard request set interface
*
* @param None
*
* @retval 0: Failed; 1: Success
*/
static uint8_t USBD_StandardSetInterface(void)
{
return 0;
}
/*!
* @brief Standard request clear feature
*
* @param None
*
* @retval 0: Failed; 1: Success
*/
static uint8_t USBD_StandardClearFeature(void)
{
return 0;
}
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Driver/inc/drv_usb_device.h
+942
View File
@@ -0,0 +1,942 @@
/*!
* @file drv_usb_device.h
*
* @brief This file contains all the prototypes,enumeration and macros for USBD peripheral
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __DRV_USB_DEVICE_H_
#define __DRV_USB_DEVICE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if defined(APM32F070xB) || defined(APM32F072x8) || defined(APM32F072xB)
#define APM32F0xx_USB
#else
#define APM32F10x_USB
#endif
#ifdef APM32F0xx_USB
#include "apm32f0xx.h"
#include "apm32f0xx_pmu.h"
#include "apm32f0xx_eint.h"
#include "apm32f0xx_gpio.h"
#include "apm32f0xx_rcm.h"
#include "apm32f0xx_misc.h"
#include "usb_config.h"
#else
#include "apm32f10x.h"
#include "apm32f10x_pmu.h"
#include "apm32f10x_eint.h"
#include "apm32f10x_gpio.h"
#include "apm32f10x_rcm.h"
#include "apm32f10x_misc.h"
#include "usb_config.h"
#endif
/** @addtogroup Peripherals_Library Standard Peripheral Library
@{
*/
/** @addtogroup USBD_Driver USBD Driver
@{
*/
/** @addtogroup USBD_Enumerations Enumerations
@{
*/
/**
* @brief USBD Endpoint register bit definition
*/
typedef enum
{
USBD_EP_BIT_ADDR = (uint32_t)(BIT0 | BIT1 | BIT2 | BIT3),
USBD_EP_BIT_TXSTS = (uint32_t)(BIT4 | BIT5),
USBD_EP_BIT_TXDTOG = (uint32_t)(BIT6),
USBD_EP_BIT_CTFT = (uint32_t)(BIT7),
USBD_EP_BIT_KIND = (uint32_t)(BIT8),
USBD_EP_BIT_TYPE = (uint32_t)(BIT9 | BIT10),
USBD_EP_BIT_SETUP = (uint32_t)(BIT11),
USBD_EP_BIT_RXSTS = (uint32_t)(BIT12 | BIT13),
USBD_EP_BIT_RXDTOG = (uint32_t)(BIT14),
USBD_EP_BIT_CTFR = (uint32_t)(BIT15)
}USBD_EP_BIT_T;
/**
* @brief Endpoint id
*/
typedef enum
{
USBD_EP_0,
USBD_EP_1,
USBD_EP_2,
USBD_EP_3,
USBD_EP_4,
USBD_EP_5,
USBD_EP_6,
USBD_EP_7,
}USBD_EP_T;
/**
* @brief Endpoint status
*/
typedef enum
{
USBD_EP_STATUS_DISABLE = ((uint32_t)0),
USBD_EP_STATUS_STALL = ((uint32_t)1),
USBD_EP_STATUS_NAK = ((uint32_t)2),
USBD_EP_STATUS_VALID = ((uint32_t)3),
}USBD_EP_STATUS_T;
/**
* @brief USBD Endpoint type for register
*/
typedef enum
{
USBD_REG_EP_TYPE_BULK,
USBD_REG_EP_TYPE_CONTROL,
USBD_REG_EP_TYPE_ISO,
USBD_REG_EP_TYPE_INTERRUPT
}USBD_REG_EP_TYPE_T;
/**@} end of group USBD_Enumerations*/
/** @addtogroup USBD_Macros Macros
@{
*/
/** USBD packet memory area base address */
#define USBD_PMA_ADDR (0x40006000L)
/** Endpoint register mask value default */
#define USBD_EP_MASK_DEFAULT (USBD_EP_BIT_CTFR | USBD_EP_BIT_SETUP | USBD_EP_BIT_TYPE | USBD_EP_BIT_KIND | USBD_EP_BIT_CTFT |USBD_EP_BIT_ADDR)
/**
* @brief USBD interrupt source
*/
#define USBD_INT_ESOF 0X100
#define USBD_INT_SOF 0X200
#define USBD_INT_RST 0X400
#define USBD_INT_SUS 0x800
#define USBD_INT_WKUP 0X1000
#define USBD_INT_ERR 0X2000
#define USBD_INT_PMAOU 0X4000
#define USBD_INT_CTR 0X8000
#define USBD_INT_ALL 0XFF00
/**@} end of group USBD_Macros*/
/** @addtogroup USBD_Fuctions Fuctions
@{
*/
/*!
* @brief Set CTRL register
*
* @param val: Register value
*
* @retval None
*
*/
#define USBD_SetRegCTRL(val) (USBD->CTRL = val)
/*!
* @brief Set INTSTS register
*
* @param val: Register value
*
* @retval None
*/
#define USBD_SetRegINTSTS(val) (USBD->INTSTS = val)
/*!
* @brief Set force reset
*
* @param None
*
* @retval None
*/
#define USBD_SetForceReset() (USBD->CTRL_B.FORRST = BIT_SET)
/*!
* @brief Reset force reset
*
* @param None
*
* @retval None
*/
#define USBD_ResetForceReset() (USBD->CTRL_B.FORRST = BIT_RESET)
/*!
* @brief Set power down
*
* @param None
*
* @retval None
*/
#define USBD_SetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_SET)
/*!
* @brief Reset power down
*
* @param None
*
* @retval None
*/
#define USBD_ResetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_RESET)
/*!
* @brief Set low power mode
*
* @param None
*
* @retval None
*/
#define USBD_SetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_SET)
/*!
* @brief Ret low power mode
*
* @param None
*
* @retval None
*/
#define USBD_ResetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_RESET)
/*!
* @brief Set force suspend
*
* @param None
*
* @retval None
*/
#define USBD_SetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_SET)
/*!
* @brief Reset force suspend
*
* @param None
*
* @retval None
*/
#define USBD_ResetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_RESET)
/*!
* @brief Read force suspend status
*
* @param None
*
* @retval None
*/
#define USBD_ReadForceSuspend() (USBD->CTRL_B.FORSUS)
/*!
* @brief Set resume
*
* @param None
*
* @retval None
*/
#define USBD_SetResume() (USBD->CTRL_B.WUPREQ = BIT_SET)
/*!
* @brief Reset resume
*
* @param None
*
* @retval None
*/
#define USBD_ResetResume() (USBD->CTRL_B.WUPREQ = BIT_RESET)
/*!
* @brief Enable interrupt
*
* @param int: Interrupt source
*
* @retval None
*/
#define USBD_EnableInterrupt(int) (USBD->CTRL |= int)
/*!
* @brief Disable interrupt
*
* @param int: Interrupt source
*
* @retval None
*/
#define USBD_DisableInterrupt(int) (USBD->CTRL &= (uint32_t)~int)
/*!
* @brief Read the specified interrupt flag status
*
* @param int: Interrupt source
*
* @retval Flag status.0 or not 0
*/
#define USBD_ReadIntFlag(int) (USBD->INTSTS & int)
/*!
* @brief Clear the specified interrupt flag status
*
* @param int: Interrupt source
*
* @retval None
*/
#define USBD_ClearIntFlag(int) (USBD->INTSTS &= (uint32_t)~int)
/*!
* @brief Read DOT field value in INTSTS rigister
*
* @param None
*
* @retval DOT field value
*/
#define USBD_ReadDir() (USBD->INTSTS_B.DOT)
/*!
* @brief Read EPID field value in INTSTS rigister
*
* @param None
*
* @retval EPIDfield value
*/
#define USBD_ReadEP() ((USBD_EP_T)(USBD->INTSTS_B.EPID))
/*!
* @brief Read EP type
*
* @param ep: EP number
*
* @retval EP type
*/
#define USBD_ReadEPType(ep) (USBD->EP[ep].EP_B.TYPE)
/*!
* @brief Read EP Tx status
*
* @param ep: EP number
*
* @retval EP Tx status
*/
#define USBD_ReadEPTxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.TXSTS))
/*!
* @brief Read EP Rx status
*
* @param ep: EP number
*
* @retval EP Rx status
*/
#define USBD_ReadEPRxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.RXSTS))
/*!
* @brief Read SETUP field value in EP register
*
* @param ep: EP number
*
* @retval SETUP field value
*/
#define USBD_ReadEPSetup(ep) (USBD->EP[ep].EP_B.SETUP)
/*!
* @brief Set buffer table value
*
* @param tab: Buffer table value
*
* @retval None
*/
#define USBD_SetBufferTable(tab) (USBD->BUFFTB_B.BUFFTB = tab)
/*!
* @brief Set device address
*
* @param addr: Device address
*
* @retval None
*/
#define USBD_SetDeviceAddr(addr) (USBD->ADDR_B.ADDR = addr)
/*!
* @brief Read CTFR field value in EP register
*
* @param ep: Endpoint number
*
* @retval CTFR field value
*/
#define USBD_ReadEPRxFlag(ep) (USBD->EP[ep].EP_B.CTFR)
/*!
* @brief Read CTFT field value in EP register
*
* @param ep: Endpoint number
*
* @retval CTFT field value
*/
#define USBD_ReadEPTxFlag(ep) (USBD->EP[ep].EP_B.CTFT)
/*!
* @brief Enable USBD peripheral
*
* @param None
*
* @retval None
*/
#define USBD_Enable() (USBD->ADDR_B.USBDEN = BIT_SET)
/*!
* @brief Disable USBD peripheral
*
* @param None
*
* @retval None
*/
#define USBD_Disable() (USBD->ADDR_B.USBDEN = BIT_RESET)
/*!
* @brief Enable USBD2 peripheral
*
* @param None
*
* @retval None
*/
#define USBD2_Enable() (USBD->SWITCH = BIT_SET)
/*!
* @brief Disable USBD2 peripheral
*
* @param None
*
* @retval None
*/
#define USBD2_Disable() (USBD->SWITCH = BIT_RESET)
/*!
* @brief Read RXDPSTS field value in FRANUM register
*
* @param None
*
* @retval RXDPSTS field value
*/
#define USBD_ReadRDPS() (USBD->FRANUM_B.RXDPSTS)
/*!
* @brief Read RXDMSTS field value in FRANUM register
*
* @param None
*
* @retval RXDMSTS field value
*/
#define USBD_ReadRDMS() (USBD->FRANUM_B.RXDMSTS)
/*!
* @brief Read LOCK field value in FRANUM register
*
* @param None
*
* @retval LOCK field value
*/
#define USBD_ReadLOCK() (USBD->FRANUM_B.LOCK)
/*!
* @brief Read LSOFNUM field value in FRANUM register
*
* @param None
*
* @retval LSOFNUM field value
*/
#define USBD_ReadLSOF() (USBD->FRANUM_B.LSOFNUM)
/*!
* @brief Read FRANUM field value in FRANUM register
*
* @param None
*
* @retval FRANUM field value
*/
#define USBD_ReadFRANUM() (USBD->FRANUM_B.FRANUM)
#ifdef APM32F0xx_USB
/*!
* @brief Read EP Tx address pointer
*
* @param ep: EP number
*
* @retval EP Tx address pointer
*/
#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) + USBD_PMA_ADDR)
/*!
* @brief Read EP Tx count pointer
*
* @param ep: EP number
*
* @retval EP Tx count pointer
*/
#define USBD_ReadEPTxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) + USBD_PMA_ADDR)
/*!
* @brief Read EP Rx address pointer
*
* @param ep: EP number
*
* @retval EP Rx address pointer
*/
#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) + USBD_PMA_ADDR)
/*!
* @brief Read EP Rx count pointer
*
* @param ep: EP number
*
* @retval EP Rx count pointer
*/
#define USBD_ReadEPRxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) + USBD_PMA_ADDR)
/*!
* @brief Set EP Tx addr
*
* @param ep: EP number
*
* @param addr: Tx addr
*
* @retval None
*/
#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1)
/*!
* @brief Set EP Rx addr
*
* @param ep: EP number
*
* @param addr: Rx addr
*
* @retval None
*/
#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1)
/*!
* @brief Read EP Tx addr
*
* @param ep: EP number
*
* @retval EP Tx addr
*/
#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep))
/*!
* @brief Read EP Rx addr
*
* @param ep: EP number
*
* @retval EP Rx addr
*/
#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep))
/*!
* @brief Read EP Tx Buffer Pointer
*
* @param ep: EP number
*
* @retval EP Tx Buffer Pointer
*/
#define USBD_ReadEPTxBufferPointer(ep) (uint16_t *)(USBD_ReadEPTxAddr(ep) + USBD_PMA_ADDR)
/*!
* @brief Read EP Rx Buffer Pointer
*
* @param ep: EP number
*
* @retval EP Rx Buffer Pointer
*/
#define USBD_ReadEPRxBufferPointer(ep) (uint16_t *)(USBD_ReadEPRxAddr(ep) + USBD_PMA_ADDR)
/*!
* @brief Set EP Tx Count
*
* @param ep: EP number
*
* @param cnt: Tx count
*
* @retval None
*/
#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt)
/*!
* @brief Read EP Tx count
*
* @param ep: EP number
*
* @retval EP Tx count
*/
#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff)
/*!
* @brief Read EP Rx count
*
* @param ep: EP number
*
* @retval EP Rx count
*/
#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff)
/*!
* @brief Set BESL Value
*
* @param val: 4-bits BESL Value to be set
*
* @retval None
*/
#define USBD_SetBESL(val) (USBD->LPMCTRLSTS_B.BESL = val)
/*!
* @brief Set bRemoteWakew Value
*
* @param val: 1-bit bRemoteWakew Value to be set
*
* @retval None
*/
#define USBD_SetRemoteWakeVal(val) (USBD->LPMCTRLSTS_B.REMWAKE = val)
/*!
* @brief Enable LPM ACK
*
* @param None
*
* @retval None
*/
#define USBD_EnableAckLPM() (USBD->LPMCTRLSTS_B.LPMACKEN = 1)
/*!
* @brief Disable LPM ACK
*
* @param None
*
* @retval None
*/
#define USBD_DisableAckLPM() (USBD->LPMCTRLSTS_B.LPMACKEN = 0)
/*!
* @brief Disable LPM
*
* @param None
*
* @retval None
*/
#define USBD_EnableLPM() (USBD->LPMCTRLSTS_B.LPMEN = 1)
/*!
* @brief Disable LPM
*
* @param None
*
* @retval None
*/
#define USBD_DisableLPM() (USBD->LPMCTRLSTS_B.LPMEN = 0)
/*!
* @brief Enable Pull-up of DP line
*
* @param None
*
* @retval None
*/
#define USBD_EnablePullUpDP() (USBD->BCD_B.DPPUCTRL = 1)
/*!
* @brief Disable Pull-up of DP line
*
* @param None
*
* @retval None
*/
#define USBD_DisablePullUpDP() (USBD->BCD_B.DPPUCTRL = 0)
/*!
* @brief Read DM Pull-up Detection Status Flag
*
* @param None
*
* @retval DM Pull-up Detection Status Flag
*/
#define USBD_DMPullUpStatus() (USBD->BCD_B.DMPUDFLG)
/*!
* @brief Read Secondary Detection Status Flag
*
* @param None
*
* @retval Secondary Detection Status Flag
*/
#define USBD_SDStatus() (USBD->BCD_B.SDFLG)
/*!
* @brief Read Primary Detection Status Flag
*
* @param None
*
* @retval Primary Detection Status Flag
*/
#define USBD_PDStatus() (USBD->BCD_B.PDFLG)
/*!
* @brief Read Data Contact Detection Status Flag
*
* @param None
*
* @retval Data Contact Detection Status Flag
*/
#define USBD_DCDStatus() (USBD->BCD_B.DCDFLG)
/*!
* @brief Enable Secondary Detection Mode
*
* @param None
*
* @retval None
*/
#define USBD_EnableSDMode() (USBD->BCD_B.SDEN = 1)
/*!
* @brief Disable Secondary Detection Mode
*
* @param None
*
* @retval None
*/
#define USBD_DisableSDMode() (USBD->BCD_B.SDEN = 0)
/*!
* @brief Enable Primary Detection Mode
*
* @param None
*
* @retval None
*/
#define USBD_EnablePDMode() (USBD->BCD_B.PDEN = 1)
/*!
* @brief Disable Primary Detection Mode
*
* @param None
*
* @retval None
*/
#define USBD_DisablePDMode() (USBD->BCD_B.PDEN = 0)
/*!
* @brief Enable Data Contact Detection Mode
*
* @param None
*
* @retval None
*/
#define USBD_EnableDCDMode() (USBD->BCD_B.DCDEN = 1)
/*!
* @brief Disable Data Contact Detection Mode
*
* @param None
*
* @retval None
*/
#define USBD_DisableDCDMode() (USBD->BCD_B.DCDEN = 0)
/*!
* @brief Enable Battery Charging Detector
*
* @param None
*
* @retval None
*/
#define USBD_EnableBCD() (USBD->BCD_B.BCDEN = 1)
/*!
* @brief Disable Battery Charging Detector
*
* @param None
*
* @retval None
*/
#define USBD_DisableBCD() (USBD->BCD_B.BCDEN = 0)
#else //!< APM32F10x_USB
/*!
* @brief Read EP Tx address pointer
*
* @param ep: EP number
*
* @retval EP Tx address pointer
*/
#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR)
/*!
* @brief Read EP Tx count pointer
*
* @param ep: EP number
*
* @retval EP Tx count pointer
*/
#define USBD_ReadEPTxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR)
/*!
* @brief Read EP Rx address pointer
*
* @param ep: EP number
*
* @retval EP Rx address pointer
*/
#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR)
/*!
* @brief Read EP Rx count pointer
*
* @param ep: EP number
*
* @retval EP Rx count pointer
*/
#define USBD_ReadEPRxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR)
/*!
* @brief Set EP Tx addr
*
* @param ep: EP number
*
* @param addr: Tx addr
*
* @retval None
*/
#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1)
/*!
* @brief Set EP Rx addr
*
* @param ep: EP number
*
* @param addr: Rx addr
*
* @retval None
*/
#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1)
/*!
* @brief Read EP Tx addr
*
* @param ep: EP number
*
* @retval EP Tx addr
*/
#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep))
/*!
* @brief Read EP Rx addr
*
* @param ep: EP number
*
* @retval EP Rx addr
*/
#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep))
/*!
* @brief Read EP Tx Buffer Pointer
*
* @param ep: EP number
*
* @retval EP Tx Buffer Pointer
*/
#define USBD_ReadEPTxBufferPointer(ep) (uint32_t *)(((uint32_t)USBD_ReadEPTxAddr(ep) << 1) + USBD_PMA_ADDR)
/*!
* @brief Read EP Rx Buffer Pointer
*
* @param ep: EP number
*
* @retval EP Rx Buffer Pointer
*/
#define USBD_ReadEPRxBufferPointer(ep) (uint32_t *)(((uint32_t)USBD_ReadEPRxAddr(ep) << 1) + USBD_PMA_ADDR)
/*!
* @brief Set EP Tx Count
*
* @param ep: EP number
*
* @param cnt: Tx count
*
* @retval None
*/
#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt)
/*!
* @brief Read EP Tx count
*
* @param ep: EP number
*
* @retval EP Tx count
*/
#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff)
/*!
* @brief Read EP Rx count
*
* @param ep: EP number
*
* @retval EP Rx count
*/
#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff)
#endif
void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type);
void USBD_SetEPKind(uint8_t ep);
void USBD_ResetEPKind(uint8_t ep);
void USBD_ResetEPRxFlag(uint8_t ep);
void USBD_ResetEPTxFlag(uint8_t ep);
void USBD_ToggleTx(uint8_t ep);
void USBD_ToggleRx(uint8_t ep);
void USBD_ResetTxToggle(uint8_t ep);
void USBD_ResetRxToggle(uint8_t ep);
void USBD_SetEpAddr(uint8_t ep, uint8_t addr);
void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status);
void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status);
void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus);
void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt);
void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen);
void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen);
/**@} end of group USBD_Fuctions*/
/**@} end of group USBD_Driver*/
/**@} end of group Peripherals_Library*/
#ifdef __cplusplus
}
#endif
#endif /* __DRV_USB_DEVICE_H */
Example/EpaperModuleTest_APM32F103/APM32F103/USB_Device_Lib/Driver/src/drv_usb_device.c
+403
View File
@@ -0,0 +1,403 @@
/*!
* @file drv_usb_device.c
*
* @brief This file contains all the functions for the USBD peripheral
*
* @version V1.0.0
*
* @date 2021-12-06
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "drv_usb_device.h"
/*!
* @brief Set Endpoint type
*
* @param ep: Endpoint number
*
* @param type: Endpoint type
*
* @retval None
*/
void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg &= ~USBD_EP_BIT_TYPE;
reg |= type << 9;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Set EP kind
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_SetEPKind(uint8_t ep)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg |= USBD_EP_BIT_KIND;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Reset EP kind
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_ResetEPKind(uint8_t ep)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg &= ~USBD_EP_BIT_KIND;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Reset EP CTFR bit
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_ResetEPRxFlag(uint8_t ep)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg &= ~USBD_EP_BIT_CTFR;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Reset EP CTFT bit
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_ResetEPTxFlag(uint8_t ep)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg &= ~USBD_EP_BIT_CTFT;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Toggle Tx DTOG
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_ToggleTx(uint8_t ep)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg |= USBD_EP_BIT_TXDTOG;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Toggle Rx DTOG
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_ToggleRx(uint8_t ep)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg |= USBD_EP_BIT_RXDTOG;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Reset Toggle Tx DTOG
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_ResetTxToggle(uint8_t ep)
{
if(USBD->EP[ep].EP_B.TXDTOG)
{
USBD_ToggleTx(ep);
}
}
/*!
* @brief Reset Toggle Rx DTOG
*
* @param ep: Endpoint number
*
* @retval None
*/
void USBD_ResetRxToggle(uint8_t ep)
{
if(USBD->EP[ep].EP_B.RXDTOG)
{
USBD_ToggleRx(ep);
}
}
/*!
* @brief Set EP address
*
* @param ep: Endpoint number
*
* @param addr: Address
*
* @retval None
*/
void USBD_SetEpAddr(uint8_t ep, uint8_t addr)
{
__IOM uint32_t reg;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
reg &= ~USBD_EP_BIT_ADDR;
reg |= addr;
USBD->EP[ep].EP = reg;
}
/*!
* @brief Set EP Tx status
*
* @param ep: Endpoint number
*
* @param status: status
*
* @retval None
*/
void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status)
{
__IOM uint32_t reg;
status <<= 4;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_TXSTS);
reg ^= ((uint32_t)status & (uint32_t)USBD_EP_BIT_TXSTS);
USBD->EP[ep].EP = reg;
}
/*!
* @brief Set EP Rx status
*
* @param ep: Endpoint number
*
* @param status: status
*
* @retval None
*/
void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status)
{
__IOM uint32_t reg;
uint32_t tmp;
tmp = status << 12;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS);
reg ^= (tmp & USBD_EP_BIT_RXSTS);
USBD->EP[ep].EP = reg;
}
/*!
* @brief Set EP Tx and Rx status
*
* @param ep: Endpoint number
*
* @param status: status
*
* @retval None
*/
void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus)
{
__IOM uint32_t reg;
uint32_t tmp;
reg = USBD->EP[ep].EP;
reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS | USBD_EP_BIT_TXSTS);
tmp = rxStatus << 12;
reg ^= (tmp & USBD_EP_BIT_RXSTS);
tmp = txStatus << 4;
reg ^= (tmp & USBD_EP_BIT_TXSTS);
USBD->EP[ep].EP = reg;
}
/*!
* @brief Set EP Rx Count
*
* @param ep: Endpoint number
*
* @param cnt: Rx count
*
* @retval None
*/
void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt)
{
__IOM uint16_t *p;
__IOM uint16_t block = 0;
p = USBD_ReadEPRxCntPointer(ep);
if(cnt > 62)
{
block = cnt >> 5;
if(!(cnt & 0x1f))
{
block -= 1;
}
*p = (block << 10) | 0x8000;
}
else
{
block = cnt >> 1;
if(cnt & 0x01)
{
block += 1;
}
*p = (block << 10);
}
}
/*!
* @brief Write a buffer of data to a selected endpoint
*
* @param ep: Endpoint number
*
* @retval wBuf: The pointer to the buffer of data to be written to the endpoint
*
* @param wLen: Number of data to be written (in bytes)
*
* @retval None
*/
void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen)
{
uint32_t i;
#ifdef APM32F0xx_USB
uint16_t *epAddr;
uint16_t tmp;
#else
uint32_t *epAddr;
uint32_t tmp;
#endif
wLen = (wLen + 1) >> 1;
epAddr = USBD_ReadEPTxBufferPointer(ep);
for(i = 0; i < wLen; i++)
{
tmp = *wBuf++;
tmp = ((*wBuf++) << 8) | tmp;
*epAddr++ = tmp;
}
}
/*!
* @brief Read a buffer of data to a selected endpoint
*
* @param ep: Endpoint number
*
* @retval wBuf: The pointer to the buffer of data to be read to the endpoint
*
* @param wLen: Number of data to be read (in bytes)
*
* @retval None
*/
void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen)
{
#ifdef APM32F0xx_USB
uint16_t *epAddr;
#else
uint32_t *epAddr;
#endif
uint32_t i, tmp, cnt;
cnt = rLen >> 1;
epAddr = USBD_ReadEPRxBufferPointer(ep);
for(i = 0; i < cnt; i++)
{
tmp = *epAddr++;
*rBuf++ = tmp & 0xFF;
*rBuf++ = (tmp >> 8) & 0xFF;
}
if (rLen & 1)
{
tmp = *epAddr;
*rBuf = tmp & 0xFF;
}
}